From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EE2E5A0562; Fri, 3 Apr 2020 04:20:28 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 890501BFC3; Fri, 3 Apr 2020 04:20:28 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 55DE81BFBA for ; Fri, 3 Apr 2020 04:20:26 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0332F5rb011608 for ; Thu, 2 Apr 2020 19:20:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=tMRbRG3gboECqPM4Ja9BzqNlDqh6mbtWTAiBZN04v8A=; b=vVVCKXhYi5LBPB6YfzpsgaYJ6NQH9X4IyhPFolqVXMfnP8xmbVPO0ybudEKPPhv9jLbg WyY+j7SwyTR+KQJoGs9E2g0KfQMW02pXjYvJ1PfSdvGW9uKBpI/+nvE9Yl5UdyhEO8b2 DY0PW6Q1b+fzzlPtVR87aPiQnXfEwi/TuZWFNpz/7GuRwSvBq+Mk6QPJmfieqdOEZA6z OLOEsB0sccAqPHxvHwlYnMqG/2bBVXLrQ7eoZzp30KtHUCbdrJ5e7gW4ZekxDnu5c5Qy WBuREnjugJ5Kh8XOJH4fQkjheGPnF7bsSsdADH0upKN+ivBRpFtF2hzhUfCVxlx9PPMi pg== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3046h6517a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 02 Apr 2020 19:20:25 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 2 Apr 2020 19:20:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 2 Apr 2020 19:20:24 -0700 Received: from hyd1vattunuru-dt.caveonetworks.com (unknown [10.29.52.72]) by maili.marvell.com (Postfix) with ESMTP id 977C73F703F; Thu, 2 Apr 2020 19:20:22 -0700 (PDT) From: To: CC: , Vamsi Attunuru Date: Fri, 3 Apr 2020 07:50:16 +0530 Message-ID: <20200403022016.2676-1-vattunuru@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-02_13:2020-04-02, 2020-04-02 signatures=0 Subject: [dpdk-dev] [PATCH] [v1 1/1] net/octeontx2: add routines to set/clear interrupt enable registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vamsi Attunuru Patch adds routines to set/clear nix lf error & ras interrupt enable registers. These nix lf error interrupts get triggered if there are any failures during nix lf configuration. This interrupts are enabled before any hardware configurations initiated on the allocated nix lf. Signed-off-by: Vamsi Attunuru --- drivers/net/octeontx2/otx2_ethdev.c | 3 +++ drivers/net/octeontx2/otx2_ethdev.h | 2 ++ drivers/net/octeontx2/otx2_ethdev_irq.c | 35 +++++++++++++++++++++++++++------ 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index e60f490..1a7ca2a 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -1660,6 +1660,9 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) goto fail_offloads; } + otx2_nix_err_intr_enb_dis(eth_dev, true); + otx2_nix_ras_intr_enb_dis(eth_dev, true); + if (dev->ptp_en && dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) { otx2_err("Both PTP and switch header enabled"); diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index e5684f9..22a4ea9 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -445,6 +445,8 @@ int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev); void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev); void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev); void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev); +void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb); +void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb); int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id); diff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c index 2256e40..96b848a 100644 --- a/drivers/net/octeontx2/otx2_ethdev_irq.c +++ b/drivers/net/octeontx2/otx2_ethdev_irq.c @@ -41,11 +41,11 @@ nix_lf_register_err_irq(struct rte_eth_dev *eth_dev) vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT; /* Clear err interrupt */ - otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C); + otx2_nix_err_intr_enb_dis(eth_dev, false); /* Set used interrupt vectors */ rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec); /* Enable all dev interrupt except for RQ_DISABLED */ - otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S); + otx2_nix_err_intr_enb_dis(eth_dev, true); return rc; } @@ -61,7 +61,7 @@ nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev) vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT; /* Clear err interrupt */ - otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C); + otx2_nix_err_intr_enb_dis(eth_dev, false); otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec); } @@ -97,11 +97,11 @@ nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev) vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON; /* Clear err interrupt */ - otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C); + otx2_nix_ras_intr_enb_dis(eth_dev, false); /* Set used interrupt vectors */ rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec); /* Enable dev interrupt */ - otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S); + otx2_nix_ras_intr_enb_dis(eth_dev, true); return rc; } @@ -117,7 +117,7 @@ nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev) vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON; /* Clear err interrupt */ - otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C); + otx2_nix_ras_intr_enb_dis(eth_dev, false); otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec); } @@ -466,3 +466,26 @@ otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, return 0; } + +void +otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + + /* Enable all nix lf error interrupts except for RQ_DISABLED */ + if (enb) + otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S); + else + otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C); +} + +void +otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + + if (enb) + otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S); + else + otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C); +} -- 2.8.4