From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DCB37A0598; Fri, 10 Apr 2020 18:42:11 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1CA411D5E3; Fri, 10 Apr 2020 18:41:58 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 5B2FE1D5DF; Fri, 10 Apr 2020 18:41:56 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E252830E; Fri, 10 Apr 2020 09:41:55 -0700 (PDT) Received: from net-arm-thunderx2-01.shanghai.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.41.214]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7393D3F52E; Fri, 10 Apr 2020 09:41:51 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com, stable@dpdk.org Date: Sat, 11 Apr 2020 00:41:23 +0800 Message-Id: <20200410164127.54229-4-gavin.hu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200410164127.54229-1-gavin.hu@arm.com> References: <20200410164127.54229-1-gavin.hu@arm.com> In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com> References: <20200213123854.203566-1-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH RFC v2 3/7] net/mlx5: relax barrier to order UAR writes on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To order the writes to host memory and the MMIO device memory, 'DMB' is sufficient on aarch64, as a 'other-multi-copy' architecture. 'DSB' is over-killing, especially in the fast path. Using the rte_dma_wmb can take the advantage on aarch64 while no impacting x86 and ppc. Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems") Cc: stable@dpdk.org Signed-off-by: Gavin Hu Reviewed-by: Phil Yang --- drivers/net/mlx5/mlx5_rxtx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index e509f3b88..da5d81350 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -546,7 +546,7 @@ __mlx5_uar_write64_relaxed(uint64_t val, void *addr, static __rte_always_inline void __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) { - rte_io_wmb(); + rte_dma_wmb(); __mlx5_uar_write64_relaxed(val, addr, lock); } -- 2.17.1