From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0CC76A00BE; Mon, 27 Apr 2020 09:59:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 70A351C1A6; Mon, 27 Apr 2020 09:59:30 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 7820A1C132 for ; Mon, 27 Apr 2020 09:59:28 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EBD831063; Mon, 27 Apr 2020 00:59:27 -0700 (PDT) Received: from net-arm-thunderx2-03.shanghai.arm.com (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B3DC43F68F; Mon, 27 Apr 2020 00:59:23 -0700 (PDT) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, phil.yang@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Mon, 27 Apr 2020 15:58:51 +0800 Message-Id: <20200427075856.12098-2-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200427075856.12098-1-joyce.kong@arm.com> References: <20200427075856.12098-1-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v10 1/6] lib/eal: implement the family of common bit operation APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Bitwise operation APIs are defined and used in a lot of PMDs, which caused a huge code duplication. To reduce duplication, this patch consolidates them into a common API family. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang Acked-by: Morten Brørup --- MAINTAINERS | 4 + doc/api/doxy-api-index.md | 3 +- lib/librte_eal/include/meson.build | 1 + lib/librte_eal/include/rte_bitops.h | 258 ++++++++++++++++++++++++++++ 4 files changed, 265 insertions(+), 1 deletion(-) create mode 100644 lib/librte_eal/include/rte_bitops.h diff --git a/MAINTAINERS b/MAINTAINERS index d31a80929..c8d4b99a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -250,6 +250,10 @@ M: Cristian Dumitrescu F: lib/librte_eal/include/rte_bitmap.h F: app/test/test_bitmap.c +Bitops +M: Joyce Kong +F: lib/librte_eal/include/rte_bitops.h + MCSlock - EXPERIMENTAL M: Phil Yang F: lib/librte_eal/include/generic/rte_mcslock.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index 845a53491..edc5d166c 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -165,7 +165,8 @@ The public API headers are grouped by topics: [random] (@ref rte_random.h), [config file] (@ref rte_cfgfile.h), [key/value args] (@ref rte_kvargs.h), - [string] (@ref rte_string_fns.h) + [string] (@ref rte_string_fns.h), + [bitops] (@ref rte_bitops.h) - **debug**: [jobstats] (@ref rte_jobstats.h), diff --git a/lib/librte_eal/include/meson.build b/lib/librte_eal/include/meson.build index e9537c91f..89a6485a4 100644 --- a/lib/librte_eal/include/meson.build +++ b/lib/librte_eal/include/meson.build @@ -6,6 +6,7 @@ includes += include_directories('.') headers += files( 'rte_alarm.h', 'rte_bitmap.h', + 'rte_bitops.h', 'rte_branch_prediction.h', 'rte_bus.h', 'rte_class.h', diff --git a/lib/librte_eal/include/rte_bitops.h b/lib/librte_eal/include/rte_bitops.h new file mode 100644 index 000000000..debadabcc --- /dev/null +++ b/lib/librte_eal/include/rte_bitops.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2020 Arm Limited + */ + +#ifndef _RTE_BITOPS_H_ +#define _RTE_BITOPS_H_ + +/** + * @file + * Bit Operations + * + * This file defines a family of APIs for bit operations + * without enforcing memory ordering. + */ + +#include +#include +#include + +/*------------------------ 32 bit relaxed operations ------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_bit_relaxed_get32(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return (*addr) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_bit_relaxed_set32(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + *addr = (*addr) | mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_bit_relaxed_clear32(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + *addr = (*addr) & (~mask); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_bit_relaxed_test_and_set32(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + uint32_t val = *addr; + *addr = val | mask; + return val & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_bit_relaxed_test_and_clear32(unsigned int nr, volatile uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + uint32_t val = *addr; + *addr = val & (~mask); + return val & mask; +} + +/*------------------------ 64 bit relaxed operations ------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_bit_relaxed_get64(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return (*addr) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_bit_relaxed_set64(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + (*addr) = (*addr) | mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_bit_relaxed_clear64(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + *addr = (*addr) & (~mask); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_bit_relaxed_test_and_set64(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + uint64_t val = *addr; + *addr = val | mask; + return val; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_bit_relaxed_test_and_clear64(unsigned int nr, volatile uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + uint64_t val = *addr; + *addr = val & (~mask); + return val & mask; +} + +#endif /* _RTE_BITOPS_H_ */ -- 2.17.1