From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 254E5A0093; Tue, 19 May 2020 01:48:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4710F1D55C; Tue, 19 May 2020 01:48:01 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id E3FD61D54F; Tue, 19 May 2020 01:47:58 +0200 (CEST) IronPort-SDR: okOnl9pglf9l8LvvN2lZ0P+Y/KS83K5bENAV7SYuOhzXJBLxclEzh3BfhpVd6zpHwrZo2fYmCD xjrEU7ukG5wg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2020 16:47:57 -0700 IronPort-SDR: 5STKo4c+D1LtPbY8D8WcxMFZ6gGoO0WRmxRry5lOptCBzX9Ty4bVlPtDfQeeK6BytPI9Z5PSz0 Y7cbnkF4p/1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,408,1583222400"; d="scan'208";a="288757818" Received: from yexl-server.sh.intel.com (HELO localhost) ([10.67.116.183]) by fmsmga004.fm.intel.com with ESMTP; 18 May 2020 16:47:53 -0700 Date: Tue, 19 May 2020 07:39:24 +0800 From: Ye Xiaolong To: "Zhao1, Wei" Cc: "Sun, GuinanX" , "dev@dpdk.org" , "stable@dpdk.org" , "Min, JiaqiX" , "Yigit, Ferruh" Message-ID: <20200518233923.GD93932@intel.com> References: <20200508015913.48764-1-guinanx.sun@intel.com> <20200508044618.70535-1-guinanx.sun@intel.com> <20200508044618.70535-3-guinanx.sun@intel.com> <20200518012453.GA93575@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v2 2/2] net/e1000: fix defects of macro in VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, wei On 05/18, Zhao1, Wei wrote: >Hi, xiaolong > >> -----Original Message----- >> From: dev On Behalf Of Ye Xiaolong >> Sent: Monday, May 18, 2020 9:25 AM >> To: Sun, GuinanX >> Cc: dev@dpdk.org; stable@dpdk.org >> Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v2 2/2] net/e1000: fix defects of >> macro in VF >> >> Hi, guinan >> >> On 05/08, Guinan Sun wrote: >> >The defects in the macros UPDATE_VF_STAT and UPDATE_VF_STAT_36BIT >> exist. >> >If latest is less than last, we will get wrong result. >> >The patch fixes the defect. >> >> There was similar patch before, https://patches.dpdk.org/patch/65131/, if I >> understand it correctly, you are trying to solve the rollover issue, right? >> Could you find the Ferruh's comment and check if this is a real issue? > >this issue has not been fixed by now, we need this patch to fix it. >If (latest < last), there will be issue, is that right? Actually the rollover case has been covered by original code. Thanks, Xiaolong > > >> >> > >> >Fixes: d15fcf76c8b7 ("e1000: move to drivers/net/") >> >> This fix commit isn't correct. >> >> Thanks, >> Xiaolong >> >> >Cc: stable@dpdk.org >> >> >> >> > >> >Signed-off-by: Guinan Sun >> >--- >> >v2 changes: >> >* Aligned line-continuation character "\". >> >--- >> > drivers/net/e1000/igb_ethdev.c | 18 +++++++++++++----- >> > 1 file changed, 13 insertions(+), 5 deletions(-) >> > >> >diff --git a/drivers/net/e1000/igb_ethdev.c >> >b/drivers/net/e1000/igb_ethdev.c index 520fba8fa..4cd4e55c0 100644 >> >--- a/drivers/net/e1000/igb_ethdev.c >> >+++ b/drivers/net/e1000/igb_ethdev.c >> >@@ -47,6 +47,8 @@ >> > #define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t) >> > #define IGB_8_BIT_WIDTH CHAR_BIT >> > #define IGB_8_BIT_MASK UINT8_MAX >> >+#define IGB_32_BIT_WIDTH (CHAR_BIT * 4) #define IGB_32_BIT_MASK >> >+RTE_LEN2MASK(IGB_32_BIT_WIDTH, uint32_t) >> > >> > /* Additional timesync values. */ >> > #define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL >> >@@ -261,11 +263,17 @@ static int igb_filter_restore(struct rte_eth_dev >> >*dev); >> > /* >> > * Define VF Stats MACRO for Non "cleared on read" register >> > */ >> >-#define UPDATE_VF_STAT(reg, last, cur) \ >> >-{ \ >> >-u32 latest = E1000_READ_REG(hw, reg); \ >> >-cur += (latest - last) & UINT_MAX; \ >> >-last = latest; \ >> >+#define UPDATE_VF_STAT(reg, last, cur) >> \ >> >+{ >> \ >> >+uint64_t latest = E1000_READ_REG(hw, reg); \ >> >+uint64_t stat = 0; \ >> >+if (latest >= last) \ >> >+stat = latest - last; \ >> >+else \ >> >+stat = (uint64_t)((latest + \ >> >+((uint64_t)1 << IGB_32_BIT_WIDTH)) - last);\ >> >+cur += stat & IGB_32_BIT_MASK; \ >> >+last = latest; \ >> > } >> > >> > #define IGB_FC_PAUSE_TIME 0x0680 >> >-- >> >2.17.1 >> >