From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0A525A04FE; Tue, 9 Jun 2020 21:43:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E011F29C6; Tue, 9 Jun 2020 21:43:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 1C29B1B53 for ; Tue, 9 Jun 2020 21:42:59 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 059JZ2QL013005; Tue, 9 Jun 2020 12:42:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=9ZVILo+X6Ftu5347Eloj972rp1Kjvxrqgw275UgHKIg=; b=V73m3uzQuynVRFd6EtKV4f+wTrMYIMWVgFv0j8RW1gj6MBgVay1U6T+hQJ7c++c5nIaP bdRwzAcwmwlZzpMV9MexkSKsGdzR+XNgbyfg96qB4BLTr62StdK5rHeTx05cJgZXs0hI 4l3mJYqQnZFPxxI7RLt6VtXBWLxw+IILAoruNDhfJQndV3hFkYbrJsq4HG9/1QEHgnKa Df98TRohKOYXKuBb3x2LQuIRK2NFsHqEBWcQRMn6xI/XOSugqZV9tX5CZQ3M8MLCEwSF zFSK8zAK0uJE+e7iXy4qTWMNippqujgkavnYfnm4L4ZBTx3zOyLplcFFxaRR9QYsUmiN BA== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 31j77dj5k2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 09 Jun 2020 12:42:59 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Jun 2020 12:42:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Jun 2020 12:42:58 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id 20AAC3F7040; Tue, 9 Jun 2020 12:42:58 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 059JgvCR024379; Tue, 9 Jun 2020 12:42:57 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 059Jgvax024378; Tue, 9 Jun 2020 12:42:57 -0700 From: Manish Chopra To: , , CC: , , , Date: Tue, 9 Jun 2020 12:42:02 -0700 Message-ID: <20200609194207.24328-2-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200609194207.24328-1-manishc@marvell.com> References: <20200609194207.24328-1-manishc@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-09_13:2020-06-09, 2020-06-09 signatures=0 Subject: [dpdk-dev] [PATCH 1/6] net/qede: define PCI config space specific osals X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch defines various PCI config space access APIs in order to read and find IOV specific PCI capabilities. With these definitions implemented, it enables the base driver to do SR-IOV specific initialization and HW specific configuration required from PF-PMD driver instance. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- drivers/net/qede/base/bcm_osal.c | 38 ++++++++++++++++++++++++++++++++ drivers/net/qede/base/bcm_osal.h | 15 +++++++++---- drivers/net/qede/base/ecore.h | 23 +++++++++++++++++++ drivers/net/qede/qede_main.c | 1 + 4 files changed, 73 insertions(+), 4 deletions(-) diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index 48d016e24..3cf33a9a7 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -14,6 +14,44 @@ #include "ecore_iov_api.h" #include "ecore_mcp_api.h" #include "ecore_l2_api.h" +#include +#include + +int osal_pci_find_next_ext_capability(struct rte_pci_device *dev, + int cap) +{ + int pos = PCI_CFG_SPACE_SIZE; + uint32_t header; + int ttl; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (rte_pci_read_config(dev, &header, 4, pos) < 0) + return -1; + + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + + if (pos < PCI_CFG_SPACE_SIZE) + break; + + if (rte_pci_read_config(dev, &header, 4, pos) < 0) + return -1; + } + + return 0; +} /* Array of memzone pointers */ static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE]; diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index 8b2faec5b..7cb887409 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -18,6 +18,7 @@ #include #include #include +#include /* Forward declaration */ struct ecore_dev; @@ -284,10 +285,16 @@ typedef struct osal_list_t { /* PCI config space */ -#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) nothing -#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) nothing -#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) nothing -#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, pcie_id) 0 +int osal_pci_find_next_ext_capability(struct rte_pci_device *dev, + int cap); +#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) \ + rte_pci_read_config((dev)->pci_dev, dst, 1, address) +#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) \ + rte_pci_read_config((dev)->pci_dev, dst, 2, address) +#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) \ + rte_pci_read_config((dev)->pci_dev, dst, 4, address) +#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, cap) \ + osal_pci_find_next_ext_capability((dev)->pci_dev, cap) #define OSAL_PCI_FIND_CAPABILITY(dev, pcie_id) 0 #define OSAL_PCI_WRITE_CONFIG_WORD(dev, address, val) nothing #define OSAL_BAR_SIZE(dev, bar_id) 0 diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index b2077bc46..386348e68 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -27,6 +27,26 @@ #include "ecore_proto_if.h" #include "mcp_public.h" +#define PCICFG_VENDOR_ID_OFFSET 0x00 +#define PCICFG_DEVICE_ID_OFFSET 0x02 +#define PCI_CFG_SPACE_SIZE 256 +#define PCI_EXP_DEVCTL 0x0008 +#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff) +#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) +#define PCI_CFG_SPACE_EXP_SIZE 4096 + +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ +#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ +#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ +#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ +#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ +#define PCI_SRIOV_VF_DID 0x1a +#define PCI_SRIOV_SUP_PGSIZE 0x1c +#define PCI_SRIOV_CAP 0x04 +#define PCI_SRIOV_FUNC_LINK 0x12 +#define PCI_EXT_CAP_ID_SRIOV 0x10 + #define ECORE_MAJOR_VERSION 8 #define ECORE_MINOR_VERSION 40 #define ECORE_REVISION_VERSION 26 @@ -916,6 +936,9 @@ struct ecore_dev { /* @DPDK */ struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM]; u8 engine_for_debug; + + /* DPDK specific ecore field */ + struct rte_pci_device *pci_dev; }; enum ecore_hsi_def_type { diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index 70357ebb6..62039af6f 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -36,6 +36,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev) edev->regview = pci_dev->mem_resource[0].addr; edev->doorbells = pci_dev->mem_resource[2].addr; edev->db_size = pci_dev->mem_resource[2].len; + edev->pci_dev = pci_dev; } static int -- 2.17.1