From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 031D1A04FE; Tue, 9 Jun 2020 21:44:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D694528EE; Tue, 9 Jun 2020 21:44:38 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 4FCDA1E2B for ; Tue, 9 Jun 2020 21:44:37 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 059JaWm9015247; Tue, 9 Jun 2020 12:44:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=zNeX0x6RrkGAMx916+/sYGWKdGGSHe9QiY8lOPBrttw=; b=N+oNc2w+LY03POcQlBEMmF+Shji/GT0mHBdtwJ59pUfVnbEoO0pjOhUOlN60Sbe3cKrF xn9vQoXMaBUUg7fzxN5Ux6QXd0AiXxqlvFtHzRjcYTgC6gJ+kl/yjIk1NCu2k5QrCXSJ SCsRAWx7mCGe/b65hir4OFA/E6xAoQry3iB1lZYtTrXi/SoQBnLo9MSBNm9DpZHhG6sG FZuOwt5SABu0DEr2bivY8jlfyRnOTTKxisdNdUjBLxJnqNMvUZOg9+6kJ87pXbLZxcz8 bdttse5xjfUcIJKLtdLiWWjb0UxqjGxrl1YiRbzFoIz5bVE4hBGgbh9Vrymtu4kkS0hJ Jg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 31gannb089-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 09 Jun 2020 12:44:36 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Jun 2020 12:44:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Jun 2020 12:44:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Jun 2020 12:44:34 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id B2FF03F703F; Tue, 9 Jun 2020 12:44:34 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 059JiYaL024413; Tue, 9 Jun 2020 12:44:34 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 059JiY6K024411; Tue, 9 Jun 2020 12:44:34 -0700 From: Manish Chopra To: , , CC: , , , Date: Tue, 9 Jun 2020 12:42:06 -0700 Message-ID: <20200609194207.24328-6-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200609194207.24328-1-manishc@marvell.com> References: <20200609194207.24328-1-manishc@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-09_13:2020-06-09, 2020-06-09 signatures=0 Subject: [dpdk-dev] [PATCH 5/6] net/qede: add VF FLR support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds required bit to handle VF FLR indication from Management FW (MFW) of the device With that VFs were able to load in VM (VF attached as PCI passthrough to the guest VM) followed by FLR successfully. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- drivers/net/qede/base/bcm_osal.c | 5 +++++ drivers/net/qede/base/bcm_osal.h | 4 +++- drivers/net/qede/qede_sriov.c | 18 ++++++++++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index 1f6466a32..78524431c 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -33,6 +33,11 @@ int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn) return rc; } +void osal_vf_flr_update(struct ecore_hwfn *p_hwfn) +{ + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); +} + void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie) { struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie; diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index b55802952..cb3711210 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -352,7 +352,9 @@ u32 qede_find_first_zero_bit(unsigned long *, u32); /* SR-IOV channel */ int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn); -#define OSAL_VF_FLR_UPDATE(hwfn) nothing +void osal_vf_flr_update(struct ecore_hwfn *p_hwfn); +#define OSAL_VF_FLR_UPDATE(hwfn) \ + osal_vf_flr_update(hwfn) #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol) (0) #define OSAL_PF_VF_MSG(hwfn, vfid) \ diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c index 125e5058b..a486b0496 100644 --- a/drivers/net/qede/qede_sriov.c +++ b/drivers/net/qede/qede_sriov.c @@ -151,6 +151,7 @@ static void qed_handle_bulletin_post(struct ecore_hwfn *hwfn) void qed_iov_pf_task(void *arg) { struct ecore_hwfn *p_hwfn = arg; + int rc; if (qede_test_bit(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) { qede_clr_bit(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags); @@ -163,6 +164,23 @@ void qed_iov_pf_task(void *arg) &p_hwfn->iov_task_flags); qed_handle_bulletin_post(p_hwfn); } + + if (qede_test_bit(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags)) { + struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); + + qede_clr_bit(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags); + + if (!p_ptt) { + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); + return; + } + + rc = ecore_iov_vf_flr_cleanup(p_hwfn, p_ptt); + if (rc) + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); + + ecore_ptt_release(p_hwfn, p_ptt); + } } int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag) -- 2.17.1