* [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements
@ 2020-06-10 6:56 Somnath Kotur
2020-06-10 6:56 ` [dpdk-dev] [PATCH 01/36] net/bnxt: Makefile changes Somnath Kotur
` (35 more replies)
0 siblings, 36 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:56 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
This patchset consists of fixes for the host based flow table
management mechanism that was introduced in 20.05. Also has some
enhancements that add offload support for vxlan encap/decap and
on-chip exact match flows.
Kishore Padmanabha (30):
bnxt/tf_ulp: Created sub Makefile for tf_ulp and tf_core
net/bnxt: remove svif and vlan information from header bitmap
net/bnxt: add vfr flag to the mark manager
net/bnxt: support for mark action for LFID rules
net/bnxt: remove mem field from mapper class table
net/bnxt: support more resource functions in flow database
net/bnxt: rename the ulp action bitmap enumeration values
net/bnxt: add support for computed header field in result opcode
net/bnxt: updated compute field list and access macros
net/bnxt: extend default identifier list to be global resource list
net/bnxt: add resource sub type to class and action tables
net/bnxt: remove cache tbl id from the mapper class table
net/bnxt: move vfr flag from computed field list to class table
net/bnxt: add support for action bitmap opcode in result field
processing
net/bnxt: direction bit needs to be added to the action bitmap
net/bnxt: remove cache_tbl_id enums
net/bnxt: extend index table processing to process action templates
net/bnxt: use vport in the phy port act handler
net/bnxt: add enum to the critical resource
net/bnxt: rename regfile_wr_idx to regfile_idx
net/bnxt: remove unused enum in regfile index
net/bnxt: rename an enum in the regfile index
net/bnxt: rename the enums in the bnxt_ulp_resource_sub_type
net/bnxt: add support for vxlan encap and decap templates
net/bnxt: flow db api to get vf rep action record
net/bnxt: remove the implicit bitset update for vnic action
net/bnxt: divide the ulp template db file to smaller modules
net/bnxt: add support for internal exact match flows
net/bnxt: enable vfr flag processing with mark db opcode
net/bnxt: update ulp template database for new opcodes
Mike Baucom (3):
net/bnxt: unify the mapper opcodes into single enum
net/bnxt: change opcode for adding pad to setting zero for common
usage
net/bnxt: optimized key/mask/result fields to use set to zero opcode
Shuanglin Wang (1):
net/bnxt: add a devarg to set max flow count
Venkat Duvvuru (2):
net/bnxt: parse ipv6 vtc_flow field for more granularly
net/bnxt: rename fields in the device params structure
drivers/net/bnxt/Makefile | 29 +-
drivers/net/bnxt/bnxt.h | 3 +
drivers/net/bnxt/bnxt_ethdev.c | 62 +-
drivers/net/bnxt/bnxt_rxr.c | 37 +-
drivers/net/bnxt/meson.build | 4 +-
drivers/net/bnxt/tf_core/Makefile | 17 +
drivers/net/bnxt/tf_ulp/Makefile | 18 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 85 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 7 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 231 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 51 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 874 +++---
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 26 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 13 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 4 +
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 25 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 167 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 13 +-
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 3426 +++++++++++++++++++++--
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 341 ++-
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 545 ++++
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 2498 +++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 591 ++++
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h | 225 ++
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 549 ++++
drivers/net/bnxt/tf_ulp/ulp_template_field_db.h | 163 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 77 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 69 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 40 +-
30 files changed, 9212 insertions(+), 980 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/Makefile
create mode 100644 drivers/net/bnxt/tf_ulp/Makefile
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 01/36] net/bnxt: Makefile changes
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
@ 2020-06-10 6:56 ` Somnath Kotur
2020-06-10 6:56 ` [dpdk-dev] [PATCH 02/36] net/bnxt: remove svif and vlan information from header bitmap Somnath Kotur
` (34 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:56 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Created sub Makefile for tf_ulp and and tf_core
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/Makefile | 29 +++++------------------------
drivers/net/bnxt/tf_core/Makefile | 17 +++++++++++++++++
drivers/net/bnxt/tf_ulp/Makefile | 16 ++++++++++++++++
3 files changed, 38 insertions(+), 24 deletions(-)
create mode 100644 drivers/net/bnxt/tf_core/Makefile
create mode 100644 drivers/net/bnxt/tf_ulp/Makefile
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
index 2a39ed1..a375299 100644
--- a/drivers/net/bnxt/Makefile
+++ b/drivers/net/bnxt/Makefile
@@ -17,7 +17,7 @@ CFLAGS += -O3
CFLAGS += $(WERROR_FLAGS)
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs
-LDLIBS += -lrte_bus_pci
+LDLIBS += -lrte_bus_pci -pthread
EXPORT_MAP := rte_pmd_bnxt_version.map
@@ -44,34 +44,15 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_rxtx_vec_sse.c
endif
ifeq ($(CONFIG_RTE_LIBRTE_BNXT_PMD), y)
-CFLAGS += -I$(SRCDIR) -I$(SRCDIR)/tf_core -I$(SRCDIR)/tf_ulp
+CFLAGS += -I$(SRCDIR) -I$(SRCDIR)/tf_ulp -I$(SRCDIR)/tf_core
+include $(SRCDIR)/tf_ulp/Makefile
+include $(SRCDIR)/tf_core/Makefile
endif
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_core.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/bitalloc.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_msg.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/rand.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/stack.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_em.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_rm.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_tbl.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tfp.c
-
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_mark_mgr.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_flow_db.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_utils.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_mapper.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_matcher.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_rte_parser.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp_flow.c
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_port_db.c
-
#
# Export include files
#
SYMLINK-y-include +=
-SYMLINK-$(CONFIG_RTE_LIBRTE_BNXT_PMD)-include := rte_pmd_bnxt.h
+SYMLINK-$(CONFIG_RTE_LIBRTE_BNXT_PMD)-include += rte_pmd_bnxt.h
include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/net/bnxt/tf_core/Makefile b/drivers/net/bnxt/tf_core/Makefile
new file mode 100644
index 0000000..379da30
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2010-2014 Intel Corporation.
+# Copyright(c) 2014 6WIND S.A.
+# Copyright(c) Broadcom Limited.
+# All rights reserved.
+
+
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/bitalloc.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/rand.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/stack.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_core.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_rm.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tfp.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_msg.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_em.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_tbl.c
+
diff --git a/drivers/net/bnxt/tf_ulp/Makefile b/drivers/net/bnxt/tf_ulp/Makefile
new file mode 100644
index 0000000..d5c22b3
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2010-2014 Intel Corporation.
+# Copyright(c) 2014 6WIND S.A.
+# Copyright(c) Broadcom Limited.
+# All rights reserved.
+
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_rte_parser.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp_flow.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_matcher.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_utils.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_mapper.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_mark_mgr.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_flow_db.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_port_db.c
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 02/36] net/bnxt: remove svif and vlan information from header bitmap
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
2020-06-10 6:56 ` [dpdk-dev] [PATCH 01/36] net/bnxt: Makefile changes Somnath Kotur
@ 2020-06-10 6:56 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 03/36] net/bnxt: add vfr flag to the mark manager Somnath Kotur
` (33 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:56 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The svif and vlan information are removed from header bitmap
signature so that the matching algorithm does not use these
fields to perform matching. So flows with or without vlan
tag could use the same flow template.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 3 ++
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 16 ++++++++
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 2 +
drivers/net/bnxt/tf_ulp/ulp_matcher.c | 25 +------------
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 45 +++++++++++------------
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 1 +
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 18 ++++-----
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 49 +++++++++++--------------
drivers/net/bnxt/tf_ulp/ulp_template_field_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 34 +++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_utils.h | 18 +++++++++
11 files changed, 128 insertions(+), 85 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index dbec8ce..1d8d79f 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -99,6 +99,8 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
ULP_UTIL_CHF_IDX_WR(¶ms, BNXT_ULP_CHF_IDX_INCOMING_IF,
dev->data->port_id);
ULP_UTIL_CHF_IDX_WR(¶ms, BNXT_ULP_CHF_IDX_DIRECTION, params.dir);
+ ULP_UTIL_CHF_IDX_WR(¶ms, BNXT_ULP_CHF_IDX_SVIF,
+ BNXT_ULP_INVALID_SVIF_VAL);
/* Parse the rte flow pattern */
ret = bnxt_ulp_rte_parser_hdr_parse(pattern, ¶ms);
@@ -121,6 +123,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
mapper_cparms.app_priority = attr->priority;
mapper_cparms.hdr_bitmap = ¶ms.hdr_bitmap;
mapper_cparms.hdr_field = params.hdr_field;
+ mapper_cparms.comp_fld = params.comp_fld;
mapper_cparms.act = ¶ms.act_bitmap;
mapper_cparms.act_prop = ¶ms.act_prop;
mapper_cparms.class_tid = class_id;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 938b88e..1a0d577 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -743,6 +743,21 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
+ case BNXT_ULP_SPEC_OPC_SET_TO_COMP_HDR_FIELD:
+ if (!ulp_operand_read(operand, (uint8_t *)&idx,
+ sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ if (idx < BNXT_ULP_CHF_IDX_LAST)
+ val = ulp_blob_push_32(blob, &parms->comp_fld[idx],
+ bitlen);
+ if (!val) {
+ BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name);
+ return -EINVAL;
+ }
+ break;
case BNXT_ULP_SPEC_OPC_SET_TO_REGFILE:
if (!ulp_operand_read(operand, (uint8_t *)&idx,
sizeof(uint16_t))) {
@@ -1857,6 +1872,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
parms.act_bitmap = cparms->act;
parms.regfile = ®file;
parms.hdr_field = cparms->hdr_field;
+ parms.comp_fld = cparms->comp_fld;
parms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx);
parms.ulp_ctx = ulp_ctx;
parms.tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 162d869..e794795 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -67,6 +67,7 @@ struct bnxt_ulp_mapper_parms {
struct ulp_rte_act_prop *act_prop;
struct ulp_rte_act_bitmap *act_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ uint32_t *comp_fld;
struct ulp_regfile *regfile;
struct tf *tfp;
struct bnxt_ulp_context *ulp_ctx;
@@ -82,6 +83,7 @@ struct bnxt_ulp_mapper_create_parms {
uint32_t app_priority;
struct ulp_rte_hdr_bitmap *hdr_bitmap;
struct ulp_rte_hdr_field *hdr_field;
+ uint32_t *comp_fld;
struct ulp_rte_act_bitmap *act;
struct ulp_rte_act_prop *act_prop;
uint32_t class_tid;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.c b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
index e5f23ef..f665700 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.c
@@ -34,22 +34,6 @@ ulp_matcher_action_hash_calculate(uint64_t hi_sig)
return (uint32_t)hash;
}
-/* Utility function to mask the computed and internal proto headers. */
-static void
-ulp_matcher_hdr_fields_normalize(struct ulp_rte_hdr_bitmap *hdr1,
- struct ulp_rte_hdr_bitmap *hdr2)
-{
- /* copy the contents first */
- rte_memcpy(hdr2, hdr1, sizeof(struct ulp_rte_hdr_bitmap));
-
- /* reset the computed fields */
- ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_SVIF);
- ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OO_VLAN);
- ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_OI_VLAN);
- ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_IO_VLAN);
- ULP_BITMAP_RESET(hdr2->bits, BNXT_ULP_HDR_BIT_II_VLAN);
-}
-
/*
* Function to handle the matching of RTE Flows and validating
* the pattern masks against the flow templates.
@@ -58,16 +42,11 @@ int32_t
ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
uint32_t *class_id)
{
- struct ulp_rte_hdr_bitmap hdr_bitmap_masked;
struct bnxt_ulp_class_match_info *class_match;
uint32_t class_hid;
uint8_t vf_to_vf;
uint16_t tmpl_id;
- /* Remove the hdr bit maps that are internal or computed */
- ulp_matcher_hdr_fields_normalize(¶ms->hdr_bitmap,
- &hdr_bitmap_masked);
-
/* determine vf to vf flow */
if (params->dir == ULP_DIR_EGRESS &&
ULP_BITMAP_ISSET(params->act_bitmap.bits,
@@ -78,7 +57,7 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
}
/* calculate the hash of the given flow */
- class_hid = ulp_matcher_class_hash_calculate(hdr_bitmap_masked.bits,
+ class_hid = ulp_matcher_class_hash_calculate(params->hdr_bitmap.bits,
params->fld_bitmap.bits);
/* validate the calculate hash values */
@@ -89,7 +68,7 @@ ulp_matcher_pattern_match(struct ulp_rte_parser_params *params,
goto error;
class_match = &ulp_class_match_list[tmpl_id];
- if (ULP_BITMAP_CMP(&hdr_bitmap_masked, &class_match->hdr_sig)) {
+ if (ULP_BITMAP_CMP(¶ms->hdr_bitmap, &class_match->hdr_sig)) {
BNXT_TF_DBG(DEBUG, "Proto Header does not match\n");
goto error;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index ace5fad..4f7adfc 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -165,15 +165,13 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
uint32_t ifindex;
int32_t rc;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF)) {
+ if (ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_SVIF) !=
+ BNXT_ULP_INVALID_SVIF_VAL) {
BNXT_TF_DBG(ERR,
"SVIF already set,multiple source not support'd\n");
return BNXT_TF_RC_ERROR;
}
- /*update the hdr_bitmap with BNXT_ULP_HDR_PROTO_SVIF */
- ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF);
-
if (proto == RTE_FLOW_ITEM_TYPE_PORT_ID) {
dir = ULP_UTIL_CHF_IDX_RD(params,
BNXT_ULP_CHF_IDX_DIRECTION);
@@ -192,6 +190,8 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
memcpy(hdr_field->spec, &svif, sizeof(svif));
memcpy(hdr_field->mask, &mask, sizeof(mask));
hdr_field->size = sizeof(svif);
+ ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_SVIF,
+ rte_be_to_cpu_16(svif));
return BNXT_TF_RC_SUCCESS;
}
@@ -202,7 +202,8 @@ ulp_rte_parser_svif_process(struct ulp_rte_parser_params *params)
uint16_t port_id = 0;
uint16_t svif_mask = 0xFFFF;
- if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_SVIF))
+ if (ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_SVIF) !=
+ BNXT_ULP_INVALID_SVIF_VAL)
return BNXT_TF_RC_SUCCESS;
/* SVIF not set. So get the port id */
@@ -421,41 +422,39 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap of the vlans */
hdr_bit = ¶ms->hdr_bitmap;
if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
- !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN)) {
- /* Set the outer vlan bit and update the vlan tag num */
- ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN);
+ !outer_vtag_num) {
+ /* Update the vlan tag num */
outer_vtag_num++;
ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,
outer_vtag_num);
ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_PRESENT, 1);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
- ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&
- !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN)) {
- /* Set the outer vlan bit and update the vlan tag num */
- ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN);
+ ULP_UTIL_CHF_IDX_RD(params,
+ BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
+ outer_vtag_num == 1) {
+ /* update the vlan tag num */
outer_vtag_num++;
ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,
outer_vtag_num);
ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_TWO_VTAGS, 1);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
- ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&
- ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN) &&
+ ULP_UTIL_CHF_IDX_RD(params,
+ BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
- !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN)) {
- /* Set the inner vlan bit and update the vlan tag num */
- ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN);
+ !inner_vtag_num) {
+ /* update the vlan tag num */
inner_vtag_num++;
ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,
inner_vtag_num);
ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_PRESENT, 1);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
- ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OO_VLAN) &&
- ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_OI_VLAN) &&
+ ULP_UTIL_CHF_IDX_RD(params,
+ BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
- ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_IO_VLAN) &&
- !ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_II_VLAN)) {
- /* Set the inner vlan bit and update the vlan tag num */
- ULP_BITMAP_SET(hdr_bit->bits, BNXT_ULP_HDR_BIT_II_VLAN);
+ ULP_UTIL_CHF_IDX_RD(params,
+ BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
+ inner_vtag_num == 1) {
+ /* update the vlan tag num */
inner_vtag_num++;
ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,
inner_vtag_num);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index cbc8a43..868e6dc 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -19,6 +19,7 @@
#define BNXT_ULP_ENCAP_IPV4_SIZE 12
#define BNXT_ULP_ENCAP_IPV6_SIZE 8
#define BNXT_ULP_ENCAP_UDP_SIZE 4
+#define BNXT_ULP_INVALID_SVIF_VAL -1U
/* Function to handle the parsing of the RTE port id. */
int32_t
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index e89aefa..f06fbc0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -3,10 +3,6 @@
* All rights reserved.
*/
-/*
- * date: Mon Mar 9 02:37:53 2020
- * version: 0.0
- */
#include "ulp_template_db.h"
#include "ulp_template_field_db.h"
@@ -538,12 +534,12 @@ uint32_t bnxt_ulp_encap_vtag_map[] = {
};
uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
- [BNXT_ULP_CLASS_HID_0092] = 1
+ [BNXT_ULP_CLASS_HID_0013] = 1
};
struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
[1] = {
- .class_hid = BNXT_ULP_CLASS_HID_0092,
+ .class_hid = BNXT_ULP_CLASS_HID_0013,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
@@ -833,15 +829,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
- /* class template id: 0, wh_plus, table: profile_tcam_cache_0 */
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_COMP_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CHF_IDX_O_VTAG_NUM >> 8) & 0xff,
+ BNXT_ULP_CHF_IDX_O_VTAG_NUM & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 7,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index e6065d2..212068f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -3,10 +3,6 @@
* All rights reserved.
*/
-/*
- * date: Mon Mar 9 02:37:53 2020
- * version: 0.0
- */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -64,24 +60,19 @@ enum bnxt_ulp_action_bit {
};
enum bnxt_ulp_hdr_bit {
- BNXT_ULP_HDR_BIT_SVIF = 0x0000000000000001,
- BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000002,
- BNXT_ULP_HDR_BIT_OO_VLAN = 0x0000000000000004,
- BNXT_ULP_HDR_BIT_OI_VLAN = 0x0000000000000008,
- BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000010,
- BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000020,
- BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000040,
- BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000080,
- BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000100,
- BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000200,
- BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000400,
- BNXT_ULP_HDR_BIT_IO_VLAN = 0x0000000000000800,
- BNXT_ULP_HDR_BIT_II_VLAN = 0x0000000000001000,
- BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000002000,
- BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000004000,
- BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000008000,
- BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000010000,
- BNXT_ULP_HDR_BIT_LAST = 0x0000000000020000
+ BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001,
+ BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002,
+ BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004,
+ BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008,
+ BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010,
+ BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020,
+ BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040,
+ BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080,
+ BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100,
+ BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200,
+ BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400,
+ BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000
};
enum bnxt_ulp_act_type {
@@ -232,10 +223,11 @@ enum bnxt_ulp_search_before_alloc {
enum bnxt_ulp_spec_opc {
BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
- BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 2,
- BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE = 3,
- BNXT_ULP_SPEC_OPC_ADD_PAD = 4,
- BNXT_ULP_SPEC_OPC_LAST = 5
+ BNXT_ULP_SPEC_OPC_SET_TO_COMP_HDR_FIELD = 2,
+ BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
+ BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE = 4,
+ BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
+ BNXT_ULP_SPEC_OPC_LAST = 6
};
enum bnxt_ulp_encap_vtag_encoding {
@@ -445,12 +437,13 @@ enum bnxt_ulp_act_prop_idx {
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
BNXT_ULP_ACT_PROP_IDX_LAST = 268
};
+
enum bnxt_ulp_class_hid {
- BNXT_ULP_CLASS_HID_0092 = 0x0092
+ BNXT_ULP_CLASS_HID_0013 = 0x0013
};
enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_0029 = 0x0029
};
-#endif /* _ULP_TEMPLATE_DB_H_ */
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
index 587de8a..2655b83 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
@@ -60,4 +60,4 @@ enum bnxt_ulp_hf_bitmask0 {
BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000
};
-#endif /* _ULP_HDR_FIELD_ENUMS_H_ */
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 0150c1d..bd267b6 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -310,6 +310,40 @@ ulp_blob_push_64(struct ulp_blob *blob,
}
/*
+ * Add data to the binary blob at the current offset.
+ *
+ * blob [in] The blob that data is added to. The blob must
+ * be initialized prior to pushing data.
+ *
+ * data [in] 32-bit value to be added to the blob.
+ *
+ * datalen [in] The number of bits to be added ot the blob.
+ *
+ * The offset of the data is updated after each push of data.
+ * NULL returned on error, pointer pushed value otherwise.
+ */
+uint8_t *
+ulp_blob_push_32(struct ulp_blob *blob,
+ uint32_t *data,
+ uint32_t datalen)
+{
+ uint8_t *val = (uint8_t *)data;
+ uint32_t rc;
+ uint32_t size = ULP_BITS_2_BYTE(datalen);
+
+ if (!data || size > sizeof(uint32_t)) {
+ BNXT_TF_DBG(ERR, "invalid argument\n");
+ return 0;
+ }
+
+ rc = ulp_blob_push(blob, &val[sizeof(uint32_t) - size], datalen);
+ if (!rc)
+ return 0;
+
+ return &val[sizeof(uint32_t) - size];
+}
+
+/*
* Add encap data to the binary blob at the current offset.
*
* blob [in] The blob that data is added to. The blob must
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 5db3933..b8de4b4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -179,6 +179,24 @@ ulp_blob_push_64(struct ulp_blob *blob,
uint32_t datalen);
/*
+ * Add data to the binary blob at the current offset.
+ *
+ * blob [in] The blob that data is added to. The blob must
+ * be initialized prior to pushing data.
+ *
+ * data [in] 32-bit value to be added to the blob.
+ *
+ * datalen [in] The number of bits to be added ot the blob.
+ *
+ * The offset of the data is updated after each push of data.
+ * NULL returned on error, pointer pushed value otherwise.
+ */
+uint8_t *
+ulp_blob_push_32(struct ulp_blob *blob,
+ uint32_t *data,
+ uint32_t datalen);
+
+/*
* Add encap data to the binary blob at the current offset.
*
* blob [in] The blob that data is added to. The blob must
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 03/36] net/bnxt: add vfr flag to the mark manager
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
2020-06-10 6:56 ` [dpdk-dev] [PATCH 01/36] net/bnxt: Makefile changes Somnath Kotur
2020-06-10 6:56 ` [dpdk-dev] [PATCH 02/36] net/bnxt: remove svif and vlan information from header bitmap Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 04/36] net/bnxt: support for mark action for LFID rules Somnath Kotur
` (32 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Add support for the vfr flag to the mark manager
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/bnxt_rxr.c | 3 ++-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 7 +++++++
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 4 ++++
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index 91ff729..bd452b7 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -413,6 +413,7 @@ bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
uint32_t mark_id;
uint32_t flags2;
int rc;
+ uint32_t vfr_flag;
cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
@@ -466,7 +467,7 @@ bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
}
rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid,
- cfa_code, &mark_id);
+ cfa_code, &vfr_flag, &mark_id);
if (!rc) {
/* Got the mark, write it to the mbuf and return */
mbuf->hash.fdir.hi = mark_id;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 9e8b81e..0e13a46 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -18,6 +18,8 @@
BNXT_ULP_MARK_VALID)
#define ULP_MARK_DB_ENTRY_IS_INVALID(mark_info) (!((mark_info)->flags &\
BNXT_ULP_MARK_VALID))
+#define ULP_MARK_DB_ENTRY_IS_VFR_ID(mark_info) ((mark_info)->flags &\
+ BNXT_ULP_MARK_VFR_ID)
#define ULP_MARK_DB_ENTRY_IS_GLOBAL_HW_FID(mark_info) ((mark_info)->flags &\
BNXT_ULP_MARK_GLOBAL_HW_FID)
@@ -153,6 +155,8 @@ ulp_mark_db_deinit(struct bnxt_ulp_context *ctxt)
*
* fid [in] The flow id that is returned by HW in BD
*
+ * vfr_flag [out].it indicatesif mark is vfr_id or mark id
+ *
* mark [out] The mark that is associated with the FID
*
*/
@@ -160,6 +164,7 @@ int32_t
ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
bool is_gfid,
uint32_t fid,
+ uint32_t *vfr_flag,
uint32_t *mark)
{
struct bnxt_ulp_mark_tbl *mtbl;
@@ -184,6 +189,7 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
BNXT_TF_DBG(DEBUG, "Get GFID[0x%0x] = 0x%0x\n",
idx, mtbl->gfid_tbl[idx].mark_id);
+ *vfr_flag = ULP_MARK_DB_ENTRY_IS_VFR_ID(&mtbl->gfid_tbl[idx]);
*mark = mtbl->gfid_tbl[idx].mark_id;
} else {
if (idx >= mtbl->lfid_num_entries ||
@@ -193,6 +199,7 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
BNXT_TF_DBG(DEBUG, "Get LFID[0x%0x] = 0x%0x\n",
idx, mtbl->lfid_tbl[idx].mark_id);
+ *vfr_flag = ULP_MARK_DB_ENTRY_IS_VFR_ID(&mtbl->lfid_tbl[idx]);
*mark = mtbl->lfid_tbl[idx].mark_id;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
index fd0d840..9696730 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
@@ -9,6 +9,7 @@
#include "bnxt_ulp.h"
#define BNXT_ULP_MARK_VALID 0x1
+#define BNXT_ULP_MARK_VFR_ID 0x2
#define BNXT_ULP_MARK_GLOBAL_HW_FID 0x4
#define BNXT_ULP_MARK_LOCAL_HW_FID 0x8
@@ -67,6 +68,8 @@ ulp_mark_db_deinit(struct bnxt_ulp_context *ctxt);
*
* fid [in] The flow id that is returned by HW in BD
*
+ * vfr_flag [out].it indicatesif mark is vfr_id or mark id
+ *
* mark [out] The mark that is associated with the FID
*
*/
@@ -74,6 +77,7 @@ int32_t
ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
bool is_gfid,
uint32_t fid,
+ uint32_t *vfr_flag,
uint32_t *mark);
/*
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 04/36] net/bnxt: support for mark action for LFID rules
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (2 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 03/36] net/bnxt: add vfr flag to the mark manager Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 05/36] net/bnxt: remove mem field from mapper class table Somnath Kotur
` (31 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The ulp mapper changes to support mark actions for non
GFID entries that support only LFID rules.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 198 +++++++++++++++++++-----------
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 3 +-
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 3 +-
3 files changed, 132 insertions(+), 72 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 1a0d577..41800d5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -313,8 +313,8 @@ ulp_mapper_cache_res_type_get(struct ulp_flow_db_res_params *res,
static int32_t
ulp_mapper_cache_entry_free(struct bnxt_ulp_context *ulp,
- struct tf *tfp,
- struct ulp_flow_db_res_params *res)
+ struct tf *tfp,
+ struct ulp_flow_db_res_params *res)
{
struct bnxt_ulp_mapper_cache_entry *cache_entry;
struct tf_free_identifier_parms ident_parms;
@@ -945,7 +945,7 @@ ulp_mapper_action_info_process(struct bnxt_ulp_mapper_parms *parms,
bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
else
bit_size = tbl->result_bit_size;
- if (!ulp_blob_init(&blob, bit_size, parms->order)) {
+ if (!ulp_blob_init(&blob, bit_size, parms->device_params->byte_order)) {
BNXT_TF_DBG(ERR, "action blob init failed\n");
return -EINVAL;
}
@@ -968,7 +968,7 @@ ulp_mapper_action_info_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
/* set the swap index if 64 bit swap is enabled */
- if (parms->encap_byte_swap && encap_flds) {
+ if (parms->device_params->encap_byte_swap && encap_flds) {
if ((i + 1) == num_flds)
ulp_blob_encap_swap_idx_set(&blob);
/* if 64 bit swap is enabled perform the 64bit swap */
@@ -982,6 +982,98 @@ ulp_mapper_action_info_process(struct bnxt_ulp_mapper_parms *parms,
}
static int32_t
+ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_class_tbl_info *tbl,
+ uint64_t flow_id)
+{
+ struct ulp_flow_db_res_params fid_parms;
+ uint32_t vfr_flag, mark, gfid, mark_flag;
+ int32_t rc = 0;
+
+ vfr_flag = ULP_UTIL_CHF_IDX_RD(parms, BNXT_ULP_CHF_IDX_VFR_FLAG);
+ if (!(tbl->mark_enable &&
+ (ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
+ return rc; /* no need to perform gfid process */
+
+ /* Get the mark id details from action property */
+ memcpy(&mark, &parms->act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_MARK],
+ sizeof(mark));
+ mark = tfp_be_to_cpu_32(mark);
+
+ TF_GET_GFID_FROM_FLOW_ID(flow_id, gfid);
+ mark_flag = BNXT_ULP_MARK_GLOBAL_HW_FID;
+ mark_flag |= (vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
+ rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
+ gfid, mark);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to add mark to flow\n");
+ return rc;
+ }
+ fid_parms.direction = tbl->direction;
+ fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID;
+ fid_parms.critical_resource = 0;
+ fid_parms.resource_type = mark_flag;
+ fid_parms.resource_hndl = gfid;
+ rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+ parms->tbl_idx,
+ parms->fid,
+ &fid_parms);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc);
+ return rc;
+}
+
+static int32_t
+ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_class_tbl_info *tbl)
+{
+ struct ulp_flow_db_res_params fid_parms;
+ uint32_t vfr_flag, act_idx, mark, mark_flag;
+ uint64_t val64;
+ int32_t rc = 0;
+
+ vfr_flag = ULP_UTIL_CHF_IDX_RD(parms, BNXT_ULP_CHF_IDX_VFR_FLAG);
+ if (!(tbl->mark_enable &&
+ (ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
+ return rc; /* no need to perform mark action process */
+
+ /* Get the mark id details from action property */
+ memcpy(&mark, &parms->act_prop->act_details[BNXT_ULP_ACT_PROP_IDX_MARK],
+ sizeof(mark));
+ mark = tfp_be_to_cpu_32(mark);
+
+ if (!ulp_regfile_read(parms->regfile,
+ BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN,
+ &val64)) {
+ BNXT_TF_DBG(ERR, "read action ptr main failed\n");
+ return -EINVAL;
+ }
+ act_idx = tfp_be_to_cpu_64(val64);
+ mark_flag = BNXT_ULP_MARK_LOCAL_HW_FID;
+ mark_flag |= (vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
+ rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
+ act_idx, mark);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to add mark to flow\n");
+ return rc;
+ }
+ fid_parms.direction = tbl->direction;
+ fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID;
+ fid_parms.critical_resource = 0;
+ fid_parms.resource_type = mark_flag;
+ fid_parms.resource_hndl = act_idx;
+ rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+ parms->tbl_idx,
+ parms->fid,
+ &fid_parms);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc);
+ return rc;
+}
+
+static int32_t
ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_class_tbl_info *tbl)
{
@@ -1015,9 +1107,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- if (!ulp_blob_init(&key, tbl->key_bit_size, parms->order) ||
- !ulp_blob_init(&mask, tbl->key_bit_size, parms->order) ||
- !ulp_blob_init(&data, tbl->result_bit_size, parms->order)) {
+ if (!ulp_blob_init(&key, tbl->key_bit_size,
+ parms->device_params->byte_order) ||
+ !ulp_blob_init(&mask, tbl->key_bit_size,
+ parms->device_params->byte_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size,
+ parms->device_params->byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -1160,6 +1255,11 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
parms->cache_ptr->tcam_idx = aparms.idx;
}
+ /* Mark action */
+ rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
+ if (rc)
+ goto error;
+
} else {
BNXT_TF_DBG(ERR, "Not supporting search before alloc now\n");
rc = -EINVAL;
@@ -1220,7 +1320,6 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
uint32_t i, num_kflds, num_dflds;
uint16_t tmplen;
struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx);
- struct ulp_rte_act_prop *a_prop = parms->act_prop;
struct ulp_flow_db_res_params fid_parms = { 0 };
struct tf_insert_em_entry_parms iparms = { 0 };
struct tf_delete_em_entry_parms free_parms = { 0 };
@@ -1234,8 +1333,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* Initialize the key/result blobs */
- if (!ulp_blob_init(&key, tbl->blob_key_bit_size, parms->order) ||
- !ulp_blob_init(&data, tbl->result_bit_size, parms->order)) {
+ if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
+ parms->device_params->byte_order) ||
+ !ulp_blob_init(&data, tbl->result_bit_size,
+ parms->device_params->byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@@ -1305,56 +1406,16 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
- if (tbl->mark_enable &&
- ULP_BITMAP_ISSET(parms->act_bitmap->bits,
- BNXT_ULP_ACTION_BIT_MARK)) {
- uint32_t val, mark, gfid, flag;
- /* TBD: Need to determine if GFID is enabled globally */
- if (sizeof(val) != BNXT_ULP_ACT_PROP_SZ_MARK) {
- BNXT_TF_DBG(ERR, "Mark size (%d) != expected (%zu)\n",
- BNXT_ULP_ACT_PROP_SZ_MARK, sizeof(val));
- rc = -EINVAL;
- goto error;
- }
-
- memcpy(&val,
- &a_prop->act_details[BNXT_ULP_ACT_PROP_IDX_MARK],
- sizeof(val));
-
- mark = tfp_be_to_cpu_32(val);
-
- TF_GET_GFID_FROM_FLOW_ID(iparms.flow_id, gfid);
- flag = BNXT_ULP_MARK_GLOBAL_HW_FID;
- rc = ulp_mark_db_mark_add(parms->ulp_ctx,
- flag,
- gfid,
- mark);
- if (rc) {
- BNXT_TF_DBG(ERR, "Failed to add mark to flow\n");
- goto error;
- }
-
- /*
- * Link the mark resource to the flow in the flow db
- * The mark is never the critical resource, so it is 0.
- */
- memset(&fid_parms, 0, sizeof(fid_parms));
- fid_parms.direction = tbl->direction;
- fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID;
- fid_parms.resource_type = flag;
- fid_parms.resource_hndl = gfid;
- fid_parms.critical_resource = 0;
-
- rc = ulp_flow_db_resource_add(parms->ulp_ctx,
- parms->tbl_idx,
- parms->fid,
- &fid_parms);
- if (rc) {
- BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n",
- rc);
- /* Need to free the identifier, so goto error */
- goto error;
- }
+ /* Mark action process */
+ if (parms->device_params->global_fid_enable &&
+ tbl->table_type == TF_MEM_EXTERNAL)
+ rc = ulp_mapper_mark_gfid_process(parms, tbl, iparms.flow_id);
+ else if (!parms->device_params->global_fid_enable &&
+ tbl->table_type == TF_MEM_INTERNAL)
+ rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to add mark to flow\n");
+ goto error;
}
/* Link the EM resource to the flow in the flow db */
@@ -1409,7 +1470,8 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, &tbl_scope_id);
- if (!ulp_blob_init(&data, tbl->result_bit_size, parms->order)) {
+ if (!ulp_blob_init(&data, tbl->result_bit_size,
+ parms->device_params->byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial index table blob\n");
return -EINVAL;
}
@@ -1538,7 +1600,8 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to get key fields\n");
return -EINVAL;
}
- if (!ulp_blob_init(&key, tbl->key_bit_size, parms->order)) {
+ if (!ulp_blob_init(&key, tbl->key_bit_size,
+ parms->device_params->byte_order)) {
BNXT_TF_DBG(ERR, "Failed to alloc blob\n");
return -EINVAL;
}
@@ -1858,7 +1921,6 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_mapper_create_parms *cparms,
uint32_t *flowid)
{
- struct bnxt_ulp_device_params *device_params;
struct bnxt_ulp_mapper_parms parms;
struct ulp_regfile regfile;
int32_t rc, trc;
@@ -1916,15 +1978,13 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
return -EINVAL;
}
- /* Get the byte order for the further processing from device params */
- device_params = bnxt_ulp_device_params_get(parms.dev_id);
- if (!device_params) {
+ /* Get the device params, it will be used in later processing */
+ parms.device_params = bnxt_ulp_device_params_get(parms.dev_id);
+ if (!parms.device_params) {
BNXT_TF_DBG(ERR, "No class tables for %d:%d\n",
parms.dev_id, parms.class_tid);
return -EINVAL;
}
- parms.order = device_params->byte_order;
- parms.encap_byte_swap = device_params->encap_byte_swap;
/* initialize the registry file for further processing */
if (!ulp_regfile_init(parms.regfile)) {
@@ -2033,7 +2093,7 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx)
/* All regfile entries are stored as 64bit big-endian values. */
regval = tfp_cpu_to_be_64((uint64_t)iparms.id);
rc = ulp_mapper_def_regfile_write(data, iparms.dir,
- reg_idx, regval);
+ reg_idx, regval);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to write to default "
"regfile.\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index e794795..0754e39 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -57,7 +57,6 @@ struct bnxt_ulp_mapper_data {
/* Internal Structure for passing the arguments around */
struct bnxt_ulp_mapper_parms {
uint32_t dev_id;
- enum bnxt_ulp_byte_order order;
uint32_t act_tid;
struct bnxt_ulp_mapper_act_tbl_info *atbls;
uint32_t num_atbls;
@@ -71,12 +70,12 @@ struct bnxt_ulp_mapper_parms {
struct ulp_regfile *regfile;
struct tf *tfp;
struct bnxt_ulp_context *ulp_ctx;
- uint8_t encap_byte_swap;
uint32_t fid;
enum bnxt_ulp_flow_db_tables tbl_idx;
struct bnxt_ulp_mapper_data *mapper_data;
enum bnxt_ulp_cache_table_opc tcam_tbl_opc;
struct bnxt_ulp_mapper_cache_entry *cache_ptr;
+ struct bnxt_ulp_device_params *device_params;
};
struct bnxt_ulp_mapper_create_parms {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 212068f..fcd80d9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -111,7 +111,8 @@ enum bnxt_ulp_chf_idx {
BNXT_ULP_CHF_IDX_I_L3 = 11,
BNXT_ULP_CHF_IDX_O_L4 = 12,
BNXT_ULP_CHF_IDX_I_L4 = 13,
- BNXT_ULP_CHF_IDX_LAST = 14
+ BNXT_ULP_CHF_IDX_VFR_FLAG = 14,
+ BNXT_ULP_CHF_IDX_LAST = 15
};
enum bnxt_ulp_def_regfile_index {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 05/36] net/bnxt: remove mem field from mapper class table
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (3 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 04/36] net/bnxt: support for mark action for LFID rules Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 06/36] net/bnxt: support more resource functions in flow database Somnath Kotur
` (30 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Remove the unused mem field in the ulp mapper class table structure
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 41800d5..9531bed 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1394,7 +1394,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
*/
iparms.dup_check = 0;
iparms.dir = tbl->direction;
- iparms.mem = tbl->mem;
+ iparms.mem = tbl->table_type;
iparms.key = ulp_blob_data_get(&key, &tmplen);
iparms.key_sz_in_bits = tbl->key_bit_size;
iparms.em_record = ulp_blob_data_get(&data, &tmplen);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 0e0d02f..a85ccf2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -159,7 +159,6 @@ struct bnxt_ulp_mapper_class_tbl_info {
enum bnxt_ulp_resource_func resource_func;
uint32_t table_type;
uint8_t direction;
- uint8_t mem;
uint32_t priority;
uint8_t srch_b4_alloc;
uint32_t critical_resource;
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 06/36] net/bnxt: support more resource functions in flow database
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (4 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 05/36] net/bnxt: remove mem field from mapper class table Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 07/36] net/bnxt: rename the ulp action bitmap enumeration values Somnath Kotur
` (29 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added support to include more resource functions in the flow
database. The number of bits increased from 3 to 8 for storing
the resource function.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 51 +++++++++++++++++++++++--------
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 24 +++++++++++----
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 13 +++-----
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 3 --
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 18 ++++++-----
5 files changed, 71 insertions(+), 38 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 35a7f86..30a809a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -16,6 +16,9 @@
#define ULP_FLOW_DB_RES_FUNC_BITS 28
#define ULP_FLOW_DB_RES_FUNC_MASK 0x70000000
#define ULP_FLOW_DB_RES_NXT_MASK 0x0FFFFFFF
+#define ULP_FLOW_DB_RES_FUNC_UPPER 5
+#define ULP_FLOW_DB_RES_FUNC_NEED_LOWER 0x80
+#define ULP_FLOW_DB_RES_FUNC_LOWER_MASK 0x1F
/* Macro to copy the nxt_resource_idx */
#define ULP_FLOW_DB_RES_NXT_SET(dst, src) {(dst) |= ((src) &\
@@ -77,20 +80,32 @@ ulp_flow_db_active_flow_is_set(struct bnxt_ulp_flow_tbl *flow_tbl,
* returns none
*/
static void
-ulp_flow_db_res_params_to_info(struct ulp_fdb_resource_info *resource_info,
- struct ulp_flow_db_res_params *params)
+ulp_flow_db_res_params_to_info(struct ulp_fdb_resource_info *resource_info,
+ struct ulp_flow_db_res_params *params)
{
+ uint32_t resource_func;
+
resource_info->nxt_resource_idx |= ((params->direction <<
ULP_FLOW_DB_RES_DIR_BIT) &
ULP_FLOW_DB_RES_DIR_MASK);
- resource_info->nxt_resource_idx |= ((params->resource_func <<
+ resource_func = (params->resource_func >> ULP_FLOW_DB_RES_FUNC_UPPER);
+ resource_info->nxt_resource_idx |= ((resource_func <<
ULP_FLOW_DB_RES_FUNC_BITS) &
ULP_FLOW_DB_RES_FUNC_MASK);
+ if (params->resource_func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) {
+ /* Break the resource func into two parts */
+ resource_func = (params->resource_func &
+ ULP_FLOW_DB_RES_FUNC_LOWER_MASK);
+ resource_info->resource_func_lower = resource_func;
+ }
+
+ /* Store the handle as 64bit only for EM table entries */
if (params->resource_func != BNXT_ULP_RESOURCE_FUNC_EM_TABLE) {
resource_info->resource_hndl = (uint32_t)params->resource_hndl;
resource_info->resource_type = params->resource_type;
-
+ resource_info->resource_sub_type = params->resource_sub_type;
+ resource_info->reserved = params->reserved;
} else {
resource_info->resource_em_handle = params->resource_hndl;
}
@@ -106,22 +121,34 @@ ulp_flow_db_res_params_to_info(struct ulp_fdb_resource_info *resource_info,
* returns none
*/
static void
-ulp_flow_db_res_info_to_params(struct ulp_fdb_resource_info *resource_info,
- struct ulp_flow_db_res_params *params)
+ulp_flow_db_res_info_to_params(struct ulp_fdb_resource_info *resource_info,
+ struct ulp_flow_db_res_params *params)
{
+ uint8_t resource_func_upper;
+
memset(params, 0, sizeof(struct ulp_flow_db_res_params));
params->direction = ((resource_info->nxt_resource_idx &
ULP_FLOW_DB_RES_DIR_MASK) >>
ULP_FLOW_DB_RES_DIR_BIT);
- params->resource_func = ((resource_info->nxt_resource_idx &
- ULP_FLOW_DB_RES_FUNC_MASK) >>
- ULP_FLOW_DB_RES_FUNC_BITS);
+ resource_func_upper = (((resource_info->nxt_resource_idx &
+ ULP_FLOW_DB_RES_FUNC_MASK) >>
+ ULP_FLOW_DB_RES_FUNC_BITS) <<
+ ULP_FLOW_DB_RES_FUNC_UPPER);
+
+ /* The reource func is split into upper and lower */
+ if (resource_func_upper & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
+ params->resource_func = (resource_func_upper |
+ resource_info->resource_func_lower);
+ else
+ params->resource_func = resource_func_upper;
- if (params->resource_func != BNXT_ULP_RESOURCE_FUNC_EM_TABLE) {
+ if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE) {
+ params->resource_hndl = resource_info->resource_em_handle;
+ } else if (params->resource_func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) {
params->resource_hndl = resource_info->resource_hndl;
params->resource_type = resource_info->resource_type;
- } else {
- params->resource_hndl = resource_info->resource_em_handle;
+ params->resource_sub_type = resource_info->resource_sub_type;
+ params->reserved = resource_info->reserved;
}
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index ebca849..9037dc5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -12,14 +12,24 @@
#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS 128
#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES 5
-/* Structure for the flow database resource information. */
+/*
+ * Structure for the flow database resource information
+ * The below structure is based on the below paritions
+ * nxt_resource_idx = dir[31],resource_func_upper[30:28],nxt_resource_idx[27:0]
+ * If resource_func is EM_TBL then use resource_em_handle.
+ * Else the other part of the union is used and
+ * resource_func is resource_func_upper[30:28] << 5 | resource_func_lower
+ */
struct ulp_fdb_resource_info {
/* Points to next resource in the chained list. */
- uint32_t nxt_resource_idx;
+ uint32_t nxt_resource_idx;
union {
- uint64_t resource_em_handle;
+ uint64_t resource_em_handle;
struct {
- uint32_t resource_type;
+ uint8_t resource_func_lower;
+ uint8_t resource_type;
+ uint8_t resource_sub_type;
+ uint8_t reserved;
uint32_t resource_hndl;
};
};
@@ -59,9 +69,11 @@ struct bnxt_ulp_flow_db {
struct ulp_flow_db_res_params {
enum tf_dir direction;
enum bnxt_ulp_resource_func resource_func;
+ uint8_t resource_type;
+ uint8_t resource_sub_type;
+ uint8_t reserved;
+ uint8_t critical_resource;
uint64_t resource_hndl;
- uint32_t resource_type;
- uint32_t critical_resource;
};
/*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 9531bed..437b055 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -292,9 +292,8 @@ ulp_mapper_cache_res_type_set(struct ulp_flow_db_res_params *res,
uint16_t tbl_type,
uint16_t tbl_id)
{
- res->resource_type =
- ((uint32_t)tbl_id << ULP_MAPPER_CACHE_RES_TBL_ID_SHFT) |
- ((uint32_t)tbl_type << ULP_MAPPER_CACHE_RES_TBL_TYPE_SHFT);
+ res->resource_type = tbl_type;
+ res->resource_sub_type = tbl_id;
}
/* Extracts the tbl_type and tbl_id from the 32bit resource type. */
@@ -303,12 +302,8 @@ ulp_mapper_cache_res_type_get(struct ulp_flow_db_res_params *res,
uint16_t *tbl_type,
uint16_t *tbl_id)
{
- *tbl_type = (uint16_t)((res->resource_type >>
- ULP_MAPPER_CACHE_RES_TBL_TYPE_SHFT) &
- ULP_MAPPER_CACHE_RES_TBL_MASK);
- *tbl_id = (uint16_t)((res->resource_type >>
- ULP_MAPPER_CACHE_RES_TBL_ID_SHFT) &
- ULP_MAPPER_CACHE_RES_TBL_MASK);
+ *tbl_type = res->resource_type;
+ *tbl_id = res->resource_sub_type;
}
static int32_t
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 0754e39..3be04e8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -17,9 +17,6 @@
#define ULP_SZ_BITS2BYTES(x) (((x) + 7) / 8)
#define ULP_IDENTS_INVALID ((uint16_t)0xffff)
-#define ULP_MAPPER_CACHE_RES_TBL_ID_SHFT 16
-#define ULP_MAPPER_CACHE_RES_TBL_TYPE_SHFT 0
-#define ULP_MAPPER_CACHE_RES_TBL_MASK ((uint32_t)0x0000ffff)
/*
* The cache table opcode is used to convey informat from the cache handler
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index fcd80d9..4721177 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -196,14 +196,16 @@ enum bnxt_ulp_regfile_index {
};
enum bnxt_ulp_resource_func {
- BNXT_ULP_RESOURCE_FUNC_INVALID = 0,
- BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 1,
- BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 2,
- BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 3,
- BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 4,
- BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 5,
- BNXT_ULP_RESOURCE_FUNC_HW_FID = 6,
- BNXT_ULP_RESOURCE_FUNC_LAST = 7
+ BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
+ BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
+ BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
+ BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
+ BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
+ BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
+ BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
+ BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
+ BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
+ BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
};
enum bnxt_ulp_result_opc {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 07/36] net/bnxt: rename the ulp action bitmap enumeration values
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (5 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 06/36] net/bnxt: support more resource functions in flow database Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 08/36] net/bnxt: add support for computed header field in result opcode Somnath Kotur
` (28 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The ulp action bitmap enumeration values that
contain open flow string are renamed
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 4721177..f86cc42 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -38,15 +38,15 @@ enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040,
BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080,
BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100,
- BNXT_ULP_ACTION_BIT_OF_POP_MPLS = 0x0000000000000200,
- BNXT_ULP_ACTION_BIT_OF_PUSH_MPLS = 0x0000000000000400,
+ BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200,
+ BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400,
BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800,
BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000,
BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000,
- BNXT_ULP_ACTION_BIT_OF_POP_VLAN = 0x0000000000004000,
- BNXT_ULP_ACTION_BIT_OF_PUSH_VLAN = 0x0000000000008000,
- BNXT_ULP_ACTION_BIT_OF_SET_VLAN_PCP = 0x0000000000010000,
- BNXT_ULP_ACTION_BIT_OF_SET_VLAN_VID = 0x0000000000020000,
+ BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000,
+ BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000,
BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000,
BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000,
BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000,
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 08/36] net/bnxt: add support for computed header field in result opcode
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (6 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 07/36] net/bnxt: rename the ulp action bitmap enumeration values Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 09/36] net/bnxt: updated compute field list and access macros Somnath Kotur
` (27 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added support for computed header fields in the result field
processing. The computed header fields are fields that are extracted
from header fields or derived from data that is not part of the flow
command but shall be used in setting up of the flow rule.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 16 ++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 3 ++-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 437b055..1ede967 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -662,6 +662,22 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
+ case BNXT_ULP_RESULT_OPC_SET_TO_COMP_HDR_FIELD:
+ if (!ulp_operand_read(fld->result_operand,
+ (uint8_t *)&idx,
+ sizeof(uint16_t))) {
+ BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
+ return -EINVAL;
+ }
+ idx = tfp_be_to_cpu_16(idx);
+ if (idx < BNXT_ULP_CHF_IDX_LAST)
+ val = ulp_blob_push_32(blob, &parms->comp_fld[idx],
+ fld->field_bit_size);
+ if (!val) {
+ BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name);
+ return -EINVAL;
+ }
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index f86cc42..82df8de 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -214,7 +214,8 @@ enum bnxt_ulp_result_opc {
BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE = 4,
- BNXT_ULP_RESULT_OPC_LAST = 5
+ BNXT_ULP_RESULT_OPC_SET_TO_COMP_HDR_FIELD = 5,
+ BNXT_ULP_RESULT_OPC_LAST = 6
};
enum bnxt_ulp_search_before_alloc {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 09/36] net/bnxt: updated compute field list and access macros
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (7 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 08/36] net/bnxt: add support for computed header field in result opcode Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 10/36] net/bnxt: extend default identifier list to be global resource list Somnath Kotur
` (26 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The compute field is extended to support action fields and not
just header fields, hence CHF is changed to CF. The access macro
for compute field is renamed to address this.
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 12 ++--
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 88 +++++++++++++--------------
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 6 +-
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 52 ++++++++++------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_utils.h | 4 +-
7 files changed, 92 insertions(+), 78 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 1d8d79f..6eb2d61 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -96,10 +96,10 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.dir = ULP_DIR_EGRESS;
/* copy the device port id and direction for further processing */
- ULP_UTIL_CHF_IDX_WR(¶ms, BNXT_ULP_CHF_IDX_INCOMING_IF,
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_INCOMING_IF,
dev->data->port_id);
- ULP_UTIL_CHF_IDX_WR(¶ms, BNXT_ULP_CHF_IDX_DIRECTION, params.dir);
- ULP_UTIL_CHF_IDX_WR(¶ms, BNXT_ULP_CHF_IDX_SVIF,
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_DIRECTION, params.dir);
+ ULP_COMP_FLD_IDX_WR(¶ms, BNXT_ULP_CF_IDX_SVIF_FLAG,
BNXT_ULP_INVALID_SVIF_VAL);
/* Parse the rte flow pattern */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 1ede967..3b8ec43 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -662,7 +662,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_COMP_HDR_FIELD:
+ case BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx,
sizeof(uint16_t))) {
@@ -670,7 +670,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx < BNXT_ULP_CHF_IDX_LAST)
+ if (idx < BNXT_ULP_CF_IDX_LAST)
val = ulp_blob_push_32(blob, &parms->comp_fld[idx],
fld->field_bit_size);
if (!val) {
@@ -754,14 +754,14 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_SPEC_OPC_SET_TO_COMP_HDR_FIELD:
+ case BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD:
if (!ulp_operand_read(operand, (uint8_t *)&idx,
sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (idx < BNXT_ULP_CHF_IDX_LAST)
+ if (idx < BNXT_ULP_CF_IDX_LAST)
val = ulp_blob_push_32(blob, &parms->comp_fld[idx],
bitlen);
if (!val) {
@@ -1001,7 +1001,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
uint32_t vfr_flag, mark, gfid, mark_flag;
int32_t rc = 0;
- vfr_flag = ULP_UTIL_CHF_IDX_RD(parms, BNXT_ULP_CHF_IDX_VFR_FLAG);
+ vfr_flag = ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_VFR_FLAG);
if (!(tbl->mark_enable &&
(ULP_BITMAP_ISSET(parms->act_bitmap->bits,
BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
@@ -1044,7 +1044,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
uint64_t val64;
int32_t rc = 0;
- vfr_flag = ULP_UTIL_CHF_IDX_RD(parms, BNXT_ULP_CHF_IDX_VFR_FLAG);
+ vfr_flag = ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_VFR_FLAG);
if (!(tbl->mark_enable &&
(ULP_BITMAP_ISSET(parms->act_bitmap->bits,
BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 4f7adfc..d264fd5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -165,7 +165,7 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
uint32_t ifindex;
int32_t rc;
- if (ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_SVIF) !=
+ if (ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_SVIF_FLAG) !=
BNXT_ULP_INVALID_SVIF_VAL) {
BNXT_TF_DBG(ERR,
"SVIF already set,multiple source not support'd\n");
@@ -173,8 +173,8 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
}
if (proto == RTE_FLOW_ITEM_TYPE_PORT_ID) {
- dir = ULP_UTIL_CHF_IDX_RD(params,
- BNXT_ULP_CHF_IDX_DIRECTION);
+ dir = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_DIRECTION);
/* perform the conversion from dpdk port to bnxt svif */
rc = ulp_port_db_dev_port_to_ulp_index(params->ulp_ctx, port_id,
&ifindex);
@@ -190,7 +190,7 @@ ulp_rte_parser_svif_set(struct ulp_rte_parser_params *params,
memcpy(hdr_field->spec, &svif, sizeof(svif));
memcpy(hdr_field->mask, &mask, sizeof(mask));
hdr_field->size = sizeof(svif);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_SVIF,
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_SVIF_FLAG,
rte_be_to_cpu_16(svif));
return BNXT_TF_RC_SUCCESS;
}
@@ -202,12 +202,12 @@ ulp_rte_parser_svif_process(struct ulp_rte_parser_params *params)
uint16_t port_id = 0;
uint16_t svif_mask = 0xFFFF;
- if (ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_SVIF) !=
+ if (ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_SVIF_FLAG) !=
BNXT_ULP_INVALID_SVIF_VAL)
return BNXT_TF_RC_SUCCESS;
/* SVIF not set. So get the port id */
- port_id = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);
+ port_id = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_INCOMING_IF);
/* Update the SVIF details */
return ulp_rte_parser_svif_set(params, RTE_FLOW_ITEM_TYPE_PORT_ID,
@@ -238,7 +238,7 @@ ulp_rte_pf_hdr_handler(const struct rte_flow_item *item,
uint16_t svif_mask = 0xFFFF;
/* Get the port id */
- port_id = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);
+ port_id = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_INCOMING_IF);
/* Update the SVIF details */
return ulp_rte_parser_svif_set(params,
@@ -414,10 +414,10 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
params->vlan_idx += BNXT_ULP_PROTO_HDR_S_VLAN_NUM;
/* Get the outer tag and inner tag counts */
- outer_vtag_num = ULP_UTIL_CHF_IDX_RD(params,
- BNXT_ULP_CHF_IDX_O_VTAG_NUM);
- inner_vtag_num = ULP_UTIL_CHF_IDX_RD(params,
- BNXT_ULP_CHF_IDX_I_VTAG_NUM);
+ outer_vtag_num = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM);
+ inner_vtag_num = ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_I_VTAG_NUM);
/* Update the hdr_bitmap of the vlans */
hdr_bit = ¶ms->hdr_bitmap;
@@ -425,40 +425,40 @@ ulp_rte_vlan_hdr_handler(const struct rte_flow_item *item,
!outer_vtag_num) {
/* Update the vlan tag num */
outer_vtag_num++;
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM,
outer_vtag_num);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_PRESENT, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_PRESENT, 1);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
- ULP_UTIL_CHF_IDX_RD(params,
- BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
+ ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT) &&
outer_vtag_num == 1) {
/* update the vlan tag num */
outer_vtag_num++;
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_VTAG_NUM,
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_VTAG_NUM,
outer_vtag_num);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_TWO_VTAGS, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_TWO_VTAGS, 1);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
- ULP_UTIL_CHF_IDX_RD(params,
- BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
+ ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
!inner_vtag_num) {
/* update the vlan tag num */
inner_vtag_num++;
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM,
inner_vtag_num);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_PRESENT, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_PRESENT, 1);
} else if (ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_O_ETH) &&
- ULP_UTIL_CHF_IDX_RD(params,
- BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
+ ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT) &&
ULP_BITMAP_ISSET(hdr_bit->bits, BNXT_ULP_HDR_BIT_I_ETH) &&
- ULP_UTIL_CHF_IDX_RD(params,
- BNXT_ULP_CHF_IDX_O_VTAG_PRESENT) &&
+ ULP_COMP_FLD_IDX_RD(params,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT) &&
inner_vtag_num == 1) {
/* update the vlan tag num */
inner_vtag_num++;
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_VTAG_NUM,
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_VTAG_NUM,
inner_vtag_num);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_TWO_VTAGS, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_TWO_VTAGS, 1);
} else {
BNXT_TF_DBG(ERR, "Error Parsing:Vlan hdr found withtout eth\n");
return BNXT_TF_RC_ERROR;
@@ -479,7 +479,7 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
uint32_t size;
uint32_t inner_l3, outer_l3;
- inner_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L3);
+ inner_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L3);
if (inner_l3) {
BNXT_TF_DBG(ERR, "Parse Error:Third L3 header not supported\n");
return BNXT_TF_RC_ERROR;
@@ -567,17 +567,17 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
params->field_idx += BNXT_ULP_PROTO_HDR_IPV4_NUM;
/* Set the ipv4 header bitmap and computed l3 header bitmaps */
- outer_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L3);
+ outer_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L3);
if (outer_l3 ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV4);
inner_l3++;
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L3, inner_l3);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, inner_l3);
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4);
outer_l3++;
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L3, outer_l3);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, outer_l3);
}
return BNXT_TF_RC_SUCCESS;
}
@@ -595,7 +595,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
uint32_t size;
uint32_t inner_l3, outer_l3;
- inner_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L3);
+ inner_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L3);
if (inner_l3) {
BNXT_TF_DBG(ERR, "Parse Error: 3'rd L3 header not supported\n");
return BNXT_TF_RC_ERROR;
@@ -655,15 +655,15 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
params->field_idx += BNXT_ULP_PROTO_HDR_IPV6_NUM;
/* Set the ipv6 header bitmap and computed l3 header bitmaps */
- outer_l3 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L3);
+ outer_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L3);
if (outer_l3 ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV4) ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6)) {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_IPV6);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L3, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3, 1);
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_IPV6);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L3, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3, 1);
}
return BNXT_TF_RC_SUCCESS;
}
@@ -681,7 +681,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
uint32_t size;
uint32_t inner_l4, outer_l4;
- inner_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L4);
+ inner_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L4);
if (inner_l4) {
BNXT_TF_DBG(ERR, "Parse Err:Third L4 header not supported\n");
return BNXT_TF_RC_ERROR;
@@ -728,15 +728,15 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
params->field_idx += BNXT_ULP_PROTO_HDR_UDP_NUM;
/* Set the udp header bitmap and computed l4 header bitmaps */
- outer_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L4);
+ outer_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L4);
if (outer_l4 ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
}
return BNXT_TF_RC_SUCCESS;
}
@@ -754,7 +754,7 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
uint32_t size;
uint32_t inner_l4, outer_l4;
- inner_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_I_L4);
+ inner_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L4);
if (inner_l4) {
BNXT_TF_DBG(ERR, "Parse Error:Third L4 header not supported\n");
return BNXT_TF_RC_ERROR;
@@ -838,15 +838,15 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
params->field_idx += BNXT_ULP_PROTO_HDR_TCP_NUM;
/* Set the udp header bitmap and computed l4 header bitmaps */
- outer_l4 = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_O_L4);
+ outer_l4 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_O_L4);
if (outer_l4 ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP) ||
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_I_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);
- ULP_UTIL_CHF_IDX_WR(params, BNXT_ULP_CHF_IDX_O_L4, 1);
+ ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
}
return BNXT_TF_RC_SUCCESS;
}
@@ -1211,7 +1211,7 @@ ulp_rte_pf_act_handler(const struct rte_flow_action *action_item __rte_unused,
ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_VNIC);
/* copy the PF of the current device into VNIC Property */
- svif = ULP_UTIL_CHF_IDX_RD(params, BNXT_ULP_CHF_IDX_INCOMING_IF);
+ svif = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_INCOMING_IF);
svif = bnxt_get_vnic_id(svif);
svif = rte_cpu_to_be_32(svif);
memcpy(¶ms->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VNIC],
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index f06fbc0..444373a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -834,10 +834,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_COMP_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD,
.spec_operand = {
- (BNXT_ULP_CHF_IDX_O_VTAG_NUM >> 8) & 0xff,
- BNXT_ULP_CHF_IDX_O_VTAG_NUM & 0xff,
+ (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 82df8de..d087404 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -96,23 +96,37 @@ enum bnxt_ulp_cache_tbl_id {
BNXT_ULP_CACHE_TBL_ID_LAST = 4
};
-enum bnxt_ulp_chf_idx {
- BNXT_ULP_CHF_IDX_MPLS_TAG_NUM = 0,
- BNXT_ULP_CHF_IDX_O_VTAG_NUM = 1,
- BNXT_ULP_CHF_IDX_O_VTAG_PRESENT = 2,
- BNXT_ULP_CHF_IDX_O_TWO_VTAGS = 3,
- BNXT_ULP_CHF_IDX_I_VTAG_NUM = 4,
- BNXT_ULP_CHF_IDX_I_VTAG_PRESENT = 5,
- BNXT_ULP_CHF_IDX_I_TWO_VTAGS = 6,
- BNXT_ULP_CHF_IDX_INCOMING_IF = 7,
- BNXT_ULP_CHF_IDX_DIRECTION = 8,
- BNXT_ULP_CHF_IDX_SVIF = 9,
- BNXT_ULP_CHF_IDX_O_L3 = 10,
- BNXT_ULP_CHF_IDX_I_L3 = 11,
- BNXT_ULP_CHF_IDX_O_L4 = 12,
- BNXT_ULP_CHF_IDX_I_L4 = 13,
- BNXT_ULP_CHF_IDX_VFR_FLAG = 14,
- BNXT_ULP_CHF_IDX_LAST = 15
+enum bnxt_ulp_cf_idx {
+ BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2,
+ BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
+ BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
+ BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5,
+ BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6,
+ BNXT_ULP_CF_IDX_INCOMING_IF = 7,
+ BNXT_ULP_CF_IDX_DIRECTION = 8,
+ BNXT_ULP_CF_IDX_SVIF_FLAG = 9,
+ BNXT_ULP_CF_IDX_O_L3 = 10,
+ BNXT_ULP_CF_IDX_I_L3 = 11,
+ BNXT_ULP_CF_IDX_O_L4 = 12,
+ BNXT_ULP_CF_IDX_I_L4 = 13,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 14,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
+ BNXT_ULP_CF_IDX_VFR_FLAG = 28,
+ BNXT_ULP_CF_IDX_LAST = 29
};
enum bnxt_ulp_def_regfile_index {
@@ -214,7 +228,7 @@ enum bnxt_ulp_result_opc {
BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE = 4,
- BNXT_ULP_RESULT_OPC_SET_TO_COMP_HDR_FIELD = 5,
+ BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 5,
BNXT_ULP_RESULT_OPC_LAST = 6
};
@@ -227,7 +241,7 @@ enum bnxt_ulp_search_before_alloc {
enum bnxt_ulp_spec_opc {
BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
- BNXT_ULP_SPEC_OPC_SET_TO_COMP_HDR_FIELD = 2,
+ BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE = 4,
BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index a85ccf2..22a2173 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -60,7 +60,7 @@ struct ulp_rte_parser_params {
struct ulp_rte_hdr_bitmap hdr_bitmap;
struct ulp_rte_field_bitmap fld_bitmap;
struct ulp_rte_hdr_field hdr_field[BNXT_ULP_PROTO_HDR_MAX];
- uint32_t comp_fld[BNXT_ULP_CHF_IDX_LAST];
+ uint32_t comp_fld[BNXT_ULP_CF_IDX_LAST];
uint32_t field_idx;
uint32_t vlan_idx;
struct ulp_rte_act_bitmap act_bitmap;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index b8de4b4..2f64bcb 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -51,10 +51,10 @@
#define ULP_BITS_2_BYTE_NR(bits_x) ((bits_x) / 8)
/* Macros to read the computed fields */
-#define ULP_UTIL_CHF_IDX_RD(params, idx) \
+#define ULP_COMP_FLD_IDX_RD(params, idx) \
rte_be_to_cpu_32((params)->comp_fld[(idx)])
-#define ULP_UTIL_CHF_IDX_WR(params, idx, val) \
+#define ULP_COMP_FLD_IDX_WR(params, idx, val) \
((params)->comp_fld[(idx)] = rte_cpu_to_be_32((val)))
/*
* Making the blob statically sized to 128 bytes for now.
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 10/36] net/bnxt: extend default identifier list to be global resource list
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (8 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 09/36] net/bnxt: updated compute field list and access macros Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 11/36] net/bnxt: add resource sub type to class and action tables Somnath Kotur
` (25 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The default identifier list in ulp mapper is extended to support
other truflow resource types and not just identifiers.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 231 +++++++++++++++++---------
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 11 +-
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 45 ++---
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 18 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 13 +-
5 files changed, 196 insertions(+), 122 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 3b8ec43..158b430 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -17,55 +17,111 @@
#include "ulp_flow_db.h"
#include "ulp_mapper.h"
-static struct bnxt_ulp_def_ident_info *
-ulp_mapper_def_ident_info_list_get(uint32_t *num_entries)
+static struct bnxt_ulp_glb_resource_info *
+ulp_mapper_glb_resource_info_list_get(uint32_t *num_entries)
{
if (!num_entries)
return NULL;
- *num_entries = BNXT_ULP_DEF_IDENT_INFO_TBL_MAX_SZ;
- return ulp_def_ident_tbl;
+ *num_entries = BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ;
+ return ulp_glb_resource_tbl;
}
/*
- * Read a default identifier from the mapper regfile.
+ * Read the global resource from the mapper global resource list
*
* The regval is always returned in big-endian.
*
* returns 0 on success
*/
static int32_t
-ulp_mapper_def_regfile_read(struct bnxt_ulp_mapper_data *mapper_data,
- enum tf_dir dir,
- uint16_t idx,
- uint64_t *regval)
+ulp_mapper_glb_resource_read(struct bnxt_ulp_mapper_data *mapper_data,
+ enum tf_dir dir,
+ uint16_t idx,
+ uint64_t *regval)
{
if (!mapper_data || !regval ||
- dir >= TF_DIR_MAX || idx >= BNXT_ULP_DEF_REGFILE_INDEX_LAST)
+ dir >= TF_DIR_MAX || idx >= BNXT_ULP_GLB_REGFILE_INDEX_LAST)
return -EINVAL;
- *regval = mapper_data->dflt_ids[dir][idx].ident;
+
+ *regval = mapper_data->glb_res_tbl[dir][idx].resource_hndl;
return 0;
}
/*
- * Write a default identifier to the mapper regfile
+ * Write a global resource to the mapper global resource list
*
* The regval value must be in big-endian.
*
* return 0 on success.
*/
static int32_t
-ulp_mapper_def_regfile_write(struct bnxt_ulp_mapper_data *mapper_data,
- enum tf_dir dir,
- uint16_t idx,
- uint64_t regval)
+ulp_mapper_glb_resource_write(struct bnxt_ulp_mapper_data *data,
+ struct bnxt_ulp_glb_resource_info *res,
+ uint64_t regval)
{
- if (!mapper_data || dir >= TF_DIR_MAX ||
- idx >= BNXT_ULP_DEF_REGFILE_INDEX_LAST)
+ struct bnxt_ulp_mapper_glb_resource_entry *ent;
+
+ /* validate the arguments */
+ if (!data || res->direction >= TF_DIR_MAX ||
+ res->glb_regfile_index >= BNXT_ULP_GLB_REGFILE_INDEX_LAST)
return -EINVAL;
- mapper_data->dflt_ids[dir][idx].ident = regval;
+
+ /* write to the mapper data */
+ ent = &data->glb_res_tbl[res->direction][res->glb_regfile_index];
+ ent->resource_func = res->resource_func;
+ ent->resource_type = res->resource_type;
+ ent->resource_hndl = regval;
return 0;
}
+/*
+ * Internal function to allocate identity resource and store it in mapper data.
+ *
+ * returns 0 on success
+ */
+static int32_t
+ulp_mapper_resource_ident_allocate(struct tf *tfp,
+ struct bnxt_ulp_mapper_data *mapper_data,
+ struct bnxt_ulp_glb_resource_info *glb_res)
+{
+ struct tf_alloc_identifier_parms iparms = { 0 };
+ struct tf_free_identifier_parms fparms;
+ uint64_t regval;
+ int32_t rc = 0;
+
+ iparms.ident_type = glb_res->resource_type;
+ iparms.dir = glb_res->direction;
+
+ /* Allocate the Identifier using tf api */
+ rc = tf_alloc_identifier(tfp, &iparms);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to alloc identifier [%s][%d]\n",
+ (iparms.dir == TF_DIR_RX) ? "RX" : "TX",
+ iparms.ident_type);
+ return rc;
+ }
+
+ /* entries are stored as big-endian format */
+ regval = tfp_cpu_to_be_64((uint64_t)iparms.id);
+ /* write to the mapper global resource */
+ rc = ulp_mapper_glb_resource_write(mapper_data, glb_res, regval);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to write to global resource id\n");
+ /* Free the identifer when update failed */
+ fparms.dir = iparms.dir;
+ fparms.ident_type = iparms.ident_type;
+ fparms.id = iparms.id;
+ tf_free_identifier(tfp, &fparms);
+ return rc;
+ }
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ BNXT_TF_DBG(DEBUG, "Allocated Glb Res[%s][%d][%d] = 0x%04x\n",
+ (iparms.dir == TF_DIR_RX) ? "RX" : "TX",
+ glb_res->glb_regfile_index, iparms.ident_type, iparms.id);
+#endif
+ return rc;
+}
+
/* Retrieve the cache initialization parameters for the tbl_idx */
static struct bnxt_ulp_cache_tbl_params *
ulp_mapper_cache_tbl_params_get(uint32_t tbl_idx)
@@ -323,7 +379,6 @@ ulp_mapper_cache_entry_free(struct bnxt_ulp_context *ulp,
* formulate the args for tf calls.
*/
ulp_mapper_cache_res_type_get(res, &table_type, &table_id);
-
cache_entry = ulp_mapper_cache_entry_get(ulp, table_id,
(uint16_t)res->resource_hndl);
if (!cache_entry || !cache_entry->ref_count) {
@@ -641,7 +696,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE:
+ case BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx,
sizeof(uint16_t))) {
@@ -649,9 +704,9 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (ulp_mapper_def_regfile_read(parms->mapper_data,
- dir,
- idx, ®val)) {
+ if (ulp_mapper_glb_resource_read(parms->mapper_data,
+ dir,
+ idx, ®val)) {
BNXT_TF_DBG(ERR, "%s regfile[%d] read failed.\n",
name, idx);
return -EINVAL;
@@ -789,16 +844,16 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE:
+ case BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE:
if (!ulp_operand_read(operand, (uint8_t *)&idx,
sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
return -EINVAL;
}
idx = tfp_be_to_cpu_16(idx);
- if (ulp_mapper_def_regfile_read(parms->mapper_data,
- dir,
- idx, &val64)) {
+ if (ulp_mapper_glb_resource_read(parms->mapper_data,
+ dir,
+ idx, &val64)) {
BNXT_TF_DBG(ERR, "%s regfile[%d] read failed.\n",
name, idx);
return -EINVAL;
@@ -1736,6 +1791,37 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
+static int32_t
+ulp_mapper_glb_resource_info_init(struct tf *tfp,
+ struct bnxt_ulp_mapper_data *mapper_data)
+{
+ struct bnxt_ulp_glb_resource_info *glb_res;
+ uint32_t num_glb_res_ids, idx;
+ int32_t rc = 0;
+
+ glb_res = ulp_mapper_glb_resource_info_list_get(&num_glb_res_ids);
+ if (!glb_res || !num_glb_res_ids) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+
+ /* Iterate the global resources and process each one */
+ for (idx = 0; idx < num_glb_res_ids; idx++) {
+ switch (glb_res[idx].resource_func) {
+ case BNXT_ULP_RESOURCE_FUNC_IDENTIFIER:
+ rc = ulp_mapper_resource_ident_allocate(tfp,
+ mapper_data,
+ &glb_res[idx]);
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Global resource %x not supported\n",
+ glb_res[idx].resource_func);
+ break;
+ }
+ }
+ return rc;
+}
+
/*
* Function to process the action template. Iterate through the list
* action info templates and process it.
@@ -1911,6 +1997,32 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
+static void
+ulp_mapper_glb_resource_info_deinit(struct bnxt_ulp_context *ulp_ctx,
+ struct bnxt_ulp_mapper_data *mapper_data)
+{
+ struct bnxt_ulp_mapper_glb_resource_entry *ent;
+ struct ulp_flow_db_res_params res;
+ uint32_t dir, idx;
+
+ /* Iterate the global resources and process each one */
+ for (dir = TF_DIR_RX; dir < TF_DIR_MAX; dir++) {
+ for (idx = 0; idx < BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ;
+ idx++) {
+ ent = &mapper_data->glb_res_tbl[dir][idx];
+ if (ent->resource_func ==
+ BNXT_ULP_RESOURCE_FUNC_INVALID)
+ continue;
+ memset(&res, 0, sizeof(struct ulp_flow_db_res_params));
+ res.resource_func = ent->resource_func;
+ res.direction = dir;
+ res.resource_type = ent->resource_type;
+ res.resource_hndl = ent->resource_hndl;
+ ulp_mapper_resource_free(ulp_ctx, &res);
+ }
+ }
+}
+
int32_t
ulp_mapper_flow_destroy(struct bnxt_ulp_context *ulp_ctx, uint32_t fid)
{
@@ -2057,11 +2169,8 @@ int32_t
ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx)
{
struct bnxt_ulp_cache_tbl_params *tbl;
- struct tf_alloc_identifier_parms iparms;
struct bnxt_ulp_mapper_data *data;
- struct bnxt_ulp_def_ident_info *dflt_ids;
- uint32_t i, num_dflt_ids, reg_idx;
- uint64_t regval;
+ uint32_t i;
struct tf *tfp;
int32_t rc, csize;
@@ -2086,30 +2195,11 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx)
return -ENOMEM;
}
- /* Allocate the default ids. */
- dflt_ids = ulp_mapper_def_ident_info_list_get(&num_dflt_ids);
- for (i = 0; i < num_dflt_ids; i++) {
- iparms.ident_type = dflt_ids[i].ident_type;
- iparms.dir = dflt_ids[i].direction;
-
- rc = tf_alloc_identifier(tfp, &iparms);
- if (rc) {
- BNXT_TF_DBG(ERR, "Failed to alloc dflt "
- "identifier [%s][%d]\n",
- (iparms.dir == TF_DIR_RX) ? "RX" : "TX",
- iparms.ident_type);
- goto error;
- }
- reg_idx = dflt_ids[i].def_regfile_index;
- /* All regfile entries are stored as 64bit big-endian values. */
- regval = tfp_cpu_to_be_64((uint64_t)iparms.id);
- rc = ulp_mapper_def_regfile_write(data, iparms.dir,
- reg_idx, regval);
- if (rc) {
- BNXT_TF_DBG(ERR, "Failed to write to default "
- "regfile.\n");
- goto error;
- }
+ /* Allocate the global resource ids */
+ rc = ulp_mapper_glb_resource_info_init(tfp, data);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to initialize global resource ids\n");
+ goto error;
}
/* Allocate the ulp cache tables. */
@@ -2144,12 +2234,8 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx)
void
ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx)
{
- struct tf_free_identifier_parms free_parms;
- struct bnxt_ulp_def_ident_info *dflt_ids;
struct bnxt_ulp_mapper_data *data;
- uint32_t i, num_dflt_ids, reg_idx;
- enum tf_dir dir;
- uint64_t regval;
+ uint32_t i;
struct tf *tfp;
if (!ulp_ctx) {
@@ -2174,27 +2260,8 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx)
goto free_mapper_data;
}
- /* Free the default prof func ids per direction. */
- dflt_ids = ulp_mapper_def_ident_info_list_get(&num_dflt_ids);
- for (i = 0; i < num_dflt_ids; i++) {
- reg_idx = dflt_ids[i].def_regfile_index;
- dir = dflt_ids[i].direction;
- free_parms.ident_type = dflt_ids[i].ident_type;
- free_parms.dir = dir;
- if (ulp_mapper_def_regfile_read(data, dir, reg_idx, ®val)) {
- BNXT_TF_DBG(ERR, "Failed to read def regfile to free "
- "identifier.\n");
- continue;
- }
- /*
- * All regfile entries are stored as 64bit big-endian. Need
- * to convert the value to cpu before calling tf.
- */
- regval = tfp_be_to_cpu_64(regval);
- free_parms.id = (uint16_t)regval;
- /* Ignore errors and free the remaining identifiers. */
- tf_free_identifier(tfp, &free_parms);
- }
+ /* Free the global resource info table entries */
+ ulp_mapper_glb_resource_info_deinit(ulp_ctx, data);
free_mapper_data:
/* Free the ulp cache tables */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 3be04e8..0c9bb86 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -39,14 +39,15 @@ struct bnxt_ulp_mapper_cache_entry {
uint8_t ident_types[BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM];
};
-struct bnxt_ulp_mapper_def_id_entry {
- enum tf_identifier_type ident_type;
- uint64_t ident;
+struct bnxt_ulp_mapper_glb_resource_entry {
+ enum bnxt_ulp_resource_func resource_func;
+ uint32_t resource_type; /* TF_ enum type */
+ uint64_t resource_hndl;
};
struct bnxt_ulp_mapper_data {
- struct bnxt_ulp_mapper_def_id_entry
- dflt_ids[TF_DIR_MAX][BNXT_ULP_DEF_IDENT_INFO_TBL_MAX_SZ];
+ struct bnxt_ulp_mapper_glb_resource_entry
+ glb_res_tbl[TF_DIR_MAX][BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ];
struct bnxt_ulp_mapper_cache_entry
*cache_tbl[BNXT_ULP_CACHE_TBL_MAX_SZ];
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 444373a..c6b1b9b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -308,20 +308,10 @@ struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
}
};
-struct bnxt_ulp_def_ident_info ulp_def_ident_tbl[] = {
- [0] = {
- .ident_type = TF_IDENT_TYPE_PROF_FUNC,
- .def_regfile_index =
- BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID,
- .direction = TF_DIR_RX
- }
-};
-
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
.global_fid_enable = BNXT_ULP_SYM_YES,
- .byte_order = (enum bnxt_ulp_byte_order)
- BNXT_ULP_SYM_LITTLE_ENDIAN,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
.lfid_entries = 16384,
.lfid_entry_size = 4,
@@ -332,6 +322,21 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
}
};
+struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ [0] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ [1] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ }
+};
+
struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
[RTE_FLOW_ITEM_TYPE_END] = {
.hdr_type = BNXT_ULP_HDR_TYPE_END,
@@ -846,10 +851,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE,
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
- (BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID & 0xff,
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1208,10 +1213,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE,
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
- (BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID & 0xff,
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1385,10 +1390,10 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 7,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
.result_operand = {
- (BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID & 0xff,
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index d087404..1bec4b6 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -26,7 +26,7 @@
#define BNXT_ULP_ACT_HID_SHFTL 23
#define BNXT_ULP_ACT_HID_MASK 255
#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
-#define BNXT_ULP_DEF_IDENT_INFO_TBL_MAX_SZ 1
+#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
@@ -129,11 +129,6 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_LAST = 29
};
-enum bnxt_ulp_def_regfile_index {
- BNXT_ULP_DEF_REGFILE_INDEX_DEF_PROF_FUNC_ID = 0,
- BNXT_ULP_DEF_REGFILE_INDEX_LAST = 1
-};
-
enum bnxt_ulp_device_id {
BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
BNXT_ULP_DEVICE_ID_THOR = 1,
@@ -148,6 +143,11 @@ enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_LAST = 2
};
+enum bnxt_ulp_glb_regfile_index {
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
+ BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
+};
+
enum bnxt_ulp_hdr_type {
BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
@@ -165,7 +165,7 @@ enum bnxt_ulp_mask_opc {
BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
- BNXT_ULP_MASK_OPC_SET_TO_DEF_REGFILE = 3,
+ BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3,
BNXT_ULP_MASK_OPC_ADD_PAD = 4,
BNXT_ULP_MASK_OPC_LAST = 5
};
@@ -227,7 +227,7 @@ enum bnxt_ulp_result_opc {
BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
- BNXT_ULP_RESULT_OPC_SET_TO_DEF_REGFILE = 4,
+ BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 4,
BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 5,
BNXT_ULP_RESULT_OPC_LAST = 6
};
@@ -243,7 +243,7 @@ enum bnxt_ulp_spec_opc {
BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
- BNXT_ULP_SPEC_OPC_SET_TO_DEF_REGFILE = 4,
+ BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4,
BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
BNXT_ULP_SPEC_OPC_LAST = 6
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 22a2173..3cbed24 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -224,10 +224,11 @@ struct bnxt_ulp_mapper_ident_info {
enum bnxt_ulp_regfile_index regfile_wr_idx;
};
-struct bnxt_ulp_def_ident_info {
- enum tf_dir direction;
- enum tf_identifier_type ident_type;
- enum bnxt_ulp_def_regfile_index def_regfile_index;
+struct bnxt_ulp_glb_resource_info {
+ enum bnxt_ulp_resource_func resource_func;
+ uint32_t resource_type; /* TF_ enum type */
+ enum bnxt_ulp_glb_regfile_index glb_regfile_index;
+ enum tf_dir direction;
};
struct bnxt_ulp_cache_tbl_params {
@@ -298,10 +299,10 @@ extern struct bnxt_ulp_mapper_ident_info ulp_ident_list[];
extern uint32_t ulp_act_prop_map_table[];
/*
- * The ulp_def_ident_tbl provides the list of default identifiers that need to
+ * The ulp_glb_resource_tbl provides the list of global resources that need to
* be initialized and where to store them.
*/
-extern struct bnxt_ulp_def_ident_info ulp_def_ident_tbl[];
+extern struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[];
/*
* The ulp_cache_tbl_parms table provides the sizes of the cache tables the
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 11/36] net/bnxt: add resource sub type to class and action tables
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (9 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 10/36] net/bnxt: extend default identifier list to be global resource list Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 12/36] net/bnxt: remove cache tbl id from the mapper class table Somnath Kotur
` (24 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added support for resource sub type to class and action tables
renamed table id to resource type.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 38 +++++++++++++--------------
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 18 ++++++++-----
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 36 ++++++++++++++++---------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 6 +++--
4 files changed, 58 insertions(+), 40 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 158b430..35b5d72 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -889,7 +889,7 @@ ulp_mapper_action_alloc_and_set(struct bnxt_ulp_mapper_parms *parms,
/* Set the allocation parameters for the table*/
alloc_parms.dir = atbls->direction;
- alloc_parms.type = atbls->table_type;
+ alloc_parms.type = atbls->resource_type;
alloc_parms.search_enable = atbls->srch_b4_alloc;
alloc_parms.result = ulp_blob_data_get(blob,
&alloc_parms.result_sz_in_bytes);
@@ -910,7 +910,7 @@ ulp_mapper_action_alloc_and_set(struct bnxt_ulp_mapper_parms *parms,
/* Need to calculate the idx for the result record */
uint64_t tmpidx = alloc_parms.idx;
- if (atbls->table_type == TF_TBL_TYPE_EXT)
+ if (atbls->resource_type == TF_TBL_TYPE_EXT)
tmpidx = TF_ACT_REC_OFFSET_2_PTR(alloc_parms.idx);
else
tmpidx = alloc_parms.idx;
@@ -935,7 +935,7 @@ ulp_mapper_action_alloc_and_set(struct bnxt_ulp_mapper_parms *parms,
uint16_t length;
set_parm.dir = atbls->direction;
- set_parm.type = atbls->table_type;
+ set_parm.type = atbls->resource_type;
set_parm.idx = alloc_parms.idx;
set_parm.data = ulp_blob_data_get(blob, &length);
set_parm.data_sz_in_bytes = length / 8;
@@ -958,7 +958,7 @@ ulp_mapper_action_alloc_and_set(struct bnxt_ulp_mapper_parms *parms,
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.direction = atbls->direction;
fid_parms.resource_func = atbls->resource_func;
- fid_parms.resource_type = atbls->table_type;
+ fid_parms.resource_type = atbls->resource_type;
fid_parms.resource_hndl = alloc_parms.idx;
fid_parms.critical_resource = 0;
@@ -1209,7 +1209,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
aparms.dir = tbl->direction;
- aparms.tcam_tbl_type = tbl->table_type;
+ aparms.tcam_tbl_type = tbl->resource_type;
aparms.search_enable = tbl->srch_b4_alloc;
aparms.key_sz_in_bits = tbl->key_bit_size;
aparms.key = ulp_blob_data_get(&key, &tmplen);
@@ -1339,7 +1339,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (parms->tcam_tbl_opc == BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL) {
fid_parms.direction = tbl->direction;
fid_parms.resource_func = tbl->resource_func;
- fid_parms.resource_type = tbl->table_type;
+ fid_parms.resource_type = tbl->resource_type;
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_hndl = aparms.idx;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
@@ -1366,12 +1366,12 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
error:
parms->tcam_tbl_opc = BNXT_ULP_MAPPER_TCAM_TBL_OPC_NORMAL;
free_parms.dir = tbl->direction;
- free_parms.tcam_tbl_type = tbl->table_type;
+ free_parms.tcam_tbl_type = tbl->resource_type;
free_parms.idx = aparms.idx;
trc = tf_free_tcam_entry(tfp, &free_parms);
if (trc)
BNXT_TF_DBG(ERR, "Failed to free tcam[%d][%d][%d] on failure\n",
- tbl->table_type, tbl->direction, aparms.idx);
+ tbl->resource_type, tbl->direction, aparms.idx);
return rc;
}
@@ -1460,7 +1460,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
*/
iparms.dup_check = 0;
iparms.dir = tbl->direction;
- iparms.mem = tbl->table_type;
+ iparms.mem = tbl->resource_type;
iparms.key = ulp_blob_data_get(&key, &tmplen);
iparms.key_sz_in_bits = tbl->key_bit_size;
iparms.em_record = ulp_blob_data_get(&data, &tmplen);
@@ -1474,10 +1474,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Mark action process */
if (parms->device_params->global_fid_enable &&
- tbl->table_type == TF_MEM_EXTERNAL)
+ tbl->resource_type == TF_MEM_EXTERNAL)
rc = ulp_mapper_mark_gfid_process(parms, tbl, iparms.flow_id);
else if (!parms->device_params->global_fid_enable &&
- tbl->table_type == TF_MEM_INTERNAL)
+ tbl->resource_type == TF_MEM_INTERNAL)
rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to add mark to flow\n");
@@ -1488,7 +1488,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.direction = tbl->direction;
fid_parms.resource_func = tbl->resource_func;
- fid_parms.resource_type = tbl->table_type;
+ fid_parms.resource_type = tbl->resource_type;
fid_parms.critical_resource = tbl->critical_resource;
fid_parms.resource_hndl = iparms.flow_handle;
@@ -1561,7 +1561,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
aparms.dir = tbl->direction;
- aparms.type = tbl->table_type;
+ aparms.type = tbl->resource_type;
aparms.search_enable = tbl->srch_b4_alloc;
aparms.result = ulp_blob_data_get(&data, &tmplen);
aparms.result_sz_in_bytes = ULP_SZ_BITS2BYTES(tbl->result_bit_size);
@@ -1571,7 +1571,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
BNXT_TF_DBG(ERR, "Alloc table[%d][%s] failed rc=%d\n",
- tbl->table_type,
+ tbl->resource_type,
(tbl->direction == TF_DIR_RX) ? "RX" : "TX",
rc);
return rc;
@@ -1588,7 +1588,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
if (!tbl->srch_b4_alloc) {
sparms.dir = tbl->direction;
- sparms.type = tbl->table_type;
+ sparms.type = tbl->resource_type;
sparms.data = ulp_blob_data_get(&data, &tmplen);
sparms.data_sz_in_bytes =
ULP_SZ_BITS2BYTES(tbl->result_bit_size);
@@ -1598,7 +1598,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
rc = tf_set_tbl_entry(tfp, &sparms);
if (rc) {
BNXT_TF_DBG(ERR, "Set table[%d][%s][%d] failed rc=%d\n",
- tbl->table_type,
+ tbl->resource_type,
(tbl->direction == TF_DIR_RX) ? "RX" : "TX",
sparms.idx,
rc);
@@ -1611,7 +1611,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
memset(&fid_parms, 0, sizeof(fid_parms));
fid_parms.direction = tbl->direction;
fid_parms.resource_func = tbl->resource_func;
- fid_parms.resource_type = tbl->table_type;
+ fid_parms.resource_type = tbl->resource_type;
fid_parms.resource_hndl = aparms.idx;
fid_parms.critical_resource = 0;
@@ -1632,7 +1632,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
* write to the entry or link the flow
*/
free_parms.dir = tbl->direction;
- free_parms.type = tbl->table_type;
+ free_parms.type = tbl->resource_type;
free_parms.idx = aparms.idx;
free_parms.tbl_scope_id = tbl_scope_id;
@@ -1760,7 +1760,7 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms,
* need to set it appropriately via setter.
*/
ulp_mapper_cache_res_type_set(&fid_parms,
- tbl->table_type,
+ tbl->resource_type,
tbl->cache_tbl_id);
fid_parms.resource_hndl = (uint64_t)*ckey;
fid_parms.critical_resource = tbl->critical_resource;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index c6b1b9b..9b793a2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -590,7 +590,8 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .table_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_NOT_USED,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -610,7 +611,8 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .table_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -630,7 +632,8 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .table_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_NOT_USED,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -650,7 +653,8 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .table_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -670,7 +674,8 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
- .table_type = TF_MEM_EXTERNAL,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_NOT_USED,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -1613,7 +1618,8 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
struct bnxt_ulp_mapper_act_tbl_info ulp_act_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .table_type = TF_TBL_TYPE_EXT,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_IT_NORMAL,
.direction = TF_DIR_RX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
.result_start_idx = 0,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 1bec4b6..aaf9024 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -209,19 +209,6 @@ enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_LAST = 16
};
-enum bnxt_ulp_resource_func {
- BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
- BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
- BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
- BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
- BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
- BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
- BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
- BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
- BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
- BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
-};
-
enum bnxt_ulp_result_opc {
BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
@@ -287,6 +274,29 @@ enum bnxt_ulp_match_type_bitmask {
BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
};
+enum bnxt_ulp_resource_func {
+ BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
+ BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
+ BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
+ BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
+ BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
+ BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
+ BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
+ BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
+ BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
+ BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
+};
+
+enum bnxt_ulp_resource_sub_type {
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_IT_NORMAL = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_IT_VFR_ACT_IDX = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_IT_INT_CNT_IDX = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_IT_EXT_CNT_IDX = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE = 1
+};
+
enum bnxt_ulp_sym {
BNXT_ULP_SYM_BIG_ENDIAN = 0,
BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 3cbed24..ce449d0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -157,7 +157,8 @@ struct bnxt_ulp_mapper_tbl_list_info {
struct bnxt_ulp_mapper_class_tbl_info {
enum bnxt_ulp_resource_func resource_func;
- uint32_t table_type;
+ uint32_t resource_type; /* TF_ enum type */
+ enum bnxt_ulp_resource_sub_type resource_sub_type;
uint8_t direction;
uint32_t priority;
uint8_t srch_b4_alloc;
@@ -187,7 +188,8 @@ struct bnxt_ulp_mapper_class_tbl_info {
struct bnxt_ulp_mapper_act_tbl_info {
enum bnxt_ulp_resource_func resource_func;
- enum tf_tbl_type table_type;
+ uint32_t resource_type; /* TF_ enum type */
+ enum bnxt_ulp_resource_sub_type resource_sub_type;
uint8_t direction;
uint8_t srch_b4_alloc;
uint32_t result_start_idx;
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 12/36] net/bnxt: remove cache tbl id from the mapper class table
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (10 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 11/36] net/bnxt: add resource sub type to class and action tables Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 13/36] net/bnxt: move vfr flag from computed field list to " Somnath Kotur
` (23 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The cache table id is not needed anymore since the value can
be calculated from resource sub type and direction.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 21 +++++++++++++++------
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 5 -----
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 --
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 35b5d72..5db0da7 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -324,13 +324,14 @@ ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
static struct bnxt_ulp_mapper_cache_entry *
ulp_mapper_cache_entry_get(struct bnxt_ulp_context *ulp,
- enum bnxt_ulp_cache_tbl_id id,
+ uint32_t id,
uint16_t key)
{
struct bnxt_ulp_mapper_data *mapper_data;
mapper_data = bnxt_ulp_cntxt_ptr2_mapper_data_get(ulp);
- if (!mapper_data || !mapper_data->cache_tbl[id]) {
+ if (!mapper_data || id >= BNXT_ULP_CACHE_TBL_MAX_SZ ||
+ !mapper_data->cache_tbl[id]) {
BNXT_TF_DBG(ERR, "Unable to acquire the cache tbl (%d)\n", id);
return NULL;
}
@@ -1691,8 +1692,15 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms,
*/
cache_key = ulp_blob_data_get(&key, &tmplen);
ckey = (uint16_t *)cache_key;
+
+ /*
+ * The id computed based on resource sub type and direction where
+ * dir is the bit0 and rest of the bits come from resource
+ * sub type.
+ */
cache_entry = ulp_mapper_cache_entry_get(parms->ulp_ctx,
- tbl->cache_tbl_id,
+ (tbl->resource_sub_type << 1 |
+ (tbl->direction & 0x1)),
*ckey);
/*
@@ -1756,12 +1764,13 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_func = tbl->resource_func;
/*
- * Cache resource type is composed of both table_type and cache_tbl_id
- * need to set it appropriately via setter.
+ * Cache resource type is composed of table_type, resource
+ * sub type and direction, it needs to set appropriately via setter.
*/
ulp_mapper_cache_res_type_set(&fid_parms,
tbl->resource_type,
- tbl->cache_tbl_id);
+ (tbl->resource_sub_type << 1 |
+ (tbl->direction & 0x1)));
fid_parms.resource_hndl = (uint64_t)*ckey;
fid_parms.critical_resource = tbl->critical_resource;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 9b793a2..140f96a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -606,7 +606,6 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.critical_resource = 0,
- .cache_tbl_id = BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_INGRESS,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -627,7 +626,6 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.critical_resource = 0,
- .cache_tbl_id = 0,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -648,7 +646,6 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.critical_resource = 0,
- .cache_tbl_id = BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_INGRESS,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -669,7 +666,6 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.critical_resource = 0,
- .cache_tbl_id = 0,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -690,7 +686,6 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_YES,
.critical_resource = 1,
- .cache_tbl_id = 0,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index ce449d0..eebe035 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -182,8 +182,6 @@ struct bnxt_ulp_mapper_class_tbl_info {
uint8_t mark_enable;
enum bnxt_ulp_regfile_index regfile_wr_idx;
-
- enum bnxt_ulp_cache_tbl_id cache_tbl_id;
};
struct bnxt_ulp_mapper_act_tbl_info {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 13/36] net/bnxt: move vfr flag from computed field list to class table
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (11 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 12/36] net/bnxt: remove cache tbl id from the mapper class table Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 14/36] net/bnxt: add support for action bitmap opcode in result field processing Somnath Kotur
` (22 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The vf representor flag is moved from computed field list to class
table so it can be set in the template details.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 14 ++++++--------
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 5 +++++
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 9 +++++++--
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 +
4 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 5db0da7..40c515d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1054,13 +1054,12 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
uint64_t flow_id)
{
struct ulp_flow_db_res_params fid_parms;
- uint32_t vfr_flag, mark, gfid, mark_flag;
+ uint32_t mark, gfid, mark_flag;
int32_t rc = 0;
- vfr_flag = ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_VFR_FLAG);
if (!(tbl->mark_enable &&
(ULP_BITMAP_ISSET(parms->act_bitmap->bits,
- BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
+ BNXT_ULP_ACTION_BIT_MARK) || tbl->vfr_flag)))
return rc; /* no need to perform gfid process */
/* Get the mark id details from action property */
@@ -1070,7 +1069,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
TF_GET_GFID_FROM_FLOW_ID(flow_id, gfid);
mark_flag = BNXT_ULP_MARK_GLOBAL_HW_FID;
- mark_flag |= (vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
+ mark_flag |= (tbl->vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
gfid, mark);
if (rc) {
@@ -1096,14 +1095,13 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_class_tbl_info *tbl)
{
struct ulp_flow_db_res_params fid_parms;
- uint32_t vfr_flag, act_idx, mark, mark_flag;
+ uint32_t act_idx, mark, mark_flag;
uint64_t val64;
int32_t rc = 0;
- vfr_flag = ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_VFR_FLAG);
if (!(tbl->mark_enable &&
(ULP_BITMAP_ISSET(parms->act_bitmap->bits,
- BNXT_ULP_ACTION_BIT_MARK) || vfr_flag)))
+ BNXT_ULP_ACTION_BIT_MARK) || tbl->vfr_flag)))
return rc; /* no need to perform mark action process */
/* Get the mark id details from action property */
@@ -1119,7 +1117,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
}
act_idx = tfp_be_to_cpu_64(val64);
mark_flag = BNXT_ULP_MARK_LOCAL_HW_FID;
- mark_flag |= (vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
+ mark_flag |= (tbl->vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
act_idx, mark);
if (rc) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 140f96a..013bc13 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -605,6 +605,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_start_idx = 0,
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = 0,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -625,6 +626,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_start_idx = 1,
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = 0,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -645,6 +647,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_start_idx = 1,
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = 0,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -665,6 +668,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_start_idx = 2,
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = 0,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -685,6 +689,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.ident_start_idx = 2,
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = 1,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index aaf9024..8554a03 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -125,8 +125,7 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
- BNXT_ULP_CF_IDX_VFR_FLAG = 28,
- BNXT_ULP_CF_IDX_LAST = 29
+ BNXT_ULP_CF_IDX_LAST = 28
};
enum bnxt_ulp_device_id {
@@ -254,6 +253,12 @@ enum bnxt_ulp_encap_vtag_encoding {
BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3
};
+enum bnxt_ulp_vfr_flag {
+ BNXT_ULP_VFR_FLAG_NO = 0,
+ BNXT_ULP_VFR_FLAG_YES = 1,
+ BNXT_ULP_VFR_FLAG_LAST = 2
+};
+
enum bnxt_ulp_fdb_resource_flags {
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index eebe035..b51cca2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -182,6 +182,7 @@ struct bnxt_ulp_mapper_class_tbl_info {
uint8_t mark_enable;
enum bnxt_ulp_regfile_index regfile_wr_idx;
+ enum bnxt_ulp_vfr_flag vfr_flag;
};
struct bnxt_ulp_mapper_act_tbl_info {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 14/36] net/bnxt: add support for action bitmap opcode in result field processing
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (12 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 13/36] net/bnxt: move vfr flag from computed field list to " Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 15/36] net/bnxt: direction bit needs to be added to the action bitmap Somnath Kotur
` (21 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
This enables using the action bitmap to update the action result
fields in the flow creation instead of using computed header fields.
An example would be the usage of the vlan pop action bitmap that is
used to updated action result field as part of this commit.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 20 ++++++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 14 +++++++++++---
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 11 ++++++-----
3 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 40c515d..a0b77c0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -611,6 +611,8 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
uint8_t *val = NULL;
uint64_t regval;
uint32_t val_size = 0, field_size = 0;
+ uint64_t act_bit;
+ uint8_t act_val;
switch (fld->result_opcode) {
case BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT:
@@ -644,6 +646,24 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
+ case BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT:
+ if (!ulp_operand_read(fld->result_operand,
+ (uint8_t *)&act_bit, sizeof(uint64_t))) {
+ BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
+ return -EINVAL;
+ }
+ act_bit = tfp_be_to_cpu_64(act_bit);
+ act_val = ULP_BITMAP_ISSET(parms->act_bitmap->bits, act_bit);
+ if (fld->field_bit_size > ULP_BYTE_2_BITS(sizeof(act_val))) {
+ BNXT_TF_DBG(ERR, "%s field size is incorrect\n", name);
+ return -EINVAL;
+ }
+ if (!ulp_blob_push(blob, &act_val, fld->field_bit_size)) {
+ BNXT_TF_DBG(ERR, "%s push field failed\n", name);
+ return -EINVAL;
+ }
+ val = &act_val;
+ break;
case BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx, sizeof(uint16_t))) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 013bc13..cb5e325 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -1774,9 +1774,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT,
+ .result_operand = {
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 8554a03..6935072 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -211,11 +211,12 @@ enum bnxt_ulp_regfile_index {
enum bnxt_ulp_result_opc {
BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
- BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 2,
- BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
- BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 4,
- BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 5,
- BNXT_ULP_RESULT_OPC_LAST = 6
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
+ BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
+ BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
+ BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
+ BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
+ BNXT_ULP_RESULT_OPC_LAST = 7
};
enum bnxt_ulp_search_before_alloc {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 15/36] net/bnxt: direction bit needs to be added to the action bitmap
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (13 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 14/36] net/bnxt: add support for action bitmap opcode in result field processing Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 16/36] net/bnxt: remove cache_tbl_id enums Somnath Kotur
` (20 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
This is a fix to add the direction bit to the action bitmap during
flow parsing, so that egress flows can be matched to the
template signature.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index d264fd5..842466d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -124,6 +124,10 @@ bnxt_ulp_rte_parser_act_parse(const struct rte_flow_action actions[],
const struct rte_flow_action *action_item = actions;
struct bnxt_ulp_rte_act_info *hdr_info;
+ if (params->dir == ULP_DIR_EGRESS)
+ ULP_BITMAP_SET(params->act_bitmap.bits,
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR);
+
/* Parse all the items in the pattern */
while (action_item && action_item->type != RTE_FLOW_ACTION_TYPE_END) {
/* get the header information from the flow_hdr_info table */
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 16/36] net/bnxt: remove cache_tbl_id enums
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (14 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 15/36] net/bnxt: direction bit needs to be added to the action bitmap Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 17/36] net/bnxt: extend index table processing to process action templates Somnath Kotur
` (19 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The bnxt_ulp_cache_tbl_id enums are not required any longer
since the index is now calculated using resource sub type
and direction.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ccxsw Build <ccxsw.build@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 16 ++++++++--------
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 8 --------
2 files changed, 8 insertions(+), 16 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index cb5e325..395d33b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -294,17 +294,17 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
};
struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
- [BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_INGRESS] = {
- .num_entries = 16384
+ [BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE << 1 | TF_DIR_RX] = {
+ .num_entries = 16384
},
- [BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_EGRESS] = {
- .num_entries = 16384
+ [BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE << 1 | TF_DIR_TX] = {
+ .num_entries = 16384
},
- [BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_INGRESS] = {
- .num_entries = 16384
+ [BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE << 1 | TF_DIR_RX] = {
+ .num_entries = 16384
},
- [BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_EGRESS] = {
- .num_entries = 16384
+ [BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE << 1 | TF_DIR_TX] = {
+ .num_entries = 16384
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 6935072..a850e22 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -88,14 +88,6 @@ enum bnxt_ulp_byte_order {
BNXT_ULP_BYTE_ORDER_LAST = 2
};
-enum bnxt_ulp_cache_tbl_id {
- BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_INGRESS = 0,
- BNXT_ULP_CACHE_TBL_ID_L2_CNTXT_TCAM_EGRESS = 1,
- BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_INGRESS = 2,
- BNXT_ULP_CACHE_TBL_ID_PROFILE_TCAM_EGRESS = 3,
- BNXT_ULP_CACHE_TBL_ID_LAST = 4
-};
-
enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 17/36] net/bnxt: extend index table processing to process action templates
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (15 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 16/36] net/bnxt: remove cache_tbl_id enums Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 18/36] net/bnxt: use vport in the phy port act handler Somnath Kotur
` (18 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The index table processing is extended to address encapsulation fields
so that action template index table can be processed by a common index
processing function that can process both class and action index
tables.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 305 ++++++++------------------
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 5 +-
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 9 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 21 +-
4 files changed, 109 insertions(+), 231 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index a0b77c0..7f7335a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -159,7 +159,7 @@ ulp_mapper_act_prop_size_get(uint32_t idx)
*
* Returns An array of action tables to implement the flow, or NULL on error.
*/
-static struct bnxt_ulp_mapper_act_tbl_info *
+static struct bnxt_ulp_mapper_tbl_info *
ulp_mapper_action_tbl_list_get(uint32_t dev_id,
uint32_t tid,
uint32_t *num_tbls)
@@ -196,7 +196,7 @@ ulp_mapper_action_tbl_list_get(uint32_t dev_id,
* returns An array of classifier tables to implement the flow, or NULL on
* error
*/
-static struct bnxt_ulp_mapper_class_tbl_info *
+static struct bnxt_ulp_mapper_tbl_info *
ulp_mapper_class_tbl_list_get(uint32_t dev_id,
uint32_t tid,
uint32_t *num_tbls)
@@ -228,7 +228,7 @@ ulp_mapper_class_tbl_list_get(uint32_t dev_id,
* Returns array of Key fields, or NULL on error.
*/
static struct bnxt_ulp_mapper_class_key_field_info *
-ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
+ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_tbl_info *tbl,
uint32_t *num_flds)
{
uint32_t idx;
@@ -255,7 +255,7 @@ ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
* Returns array of data fields, or NULL on error.
*/
static struct bnxt_ulp_mapper_result_field_info *
-ulp_mapper_result_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
+ulp_mapper_result_fields_get(struct bnxt_ulp_mapper_tbl_info *tbl,
uint32_t *num_flds)
{
uint32_t idx;
@@ -280,7 +280,7 @@ ulp_mapper_result_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
* Returns array of data fields, or NULL on error.
*/
static struct bnxt_ulp_mapper_result_field_info *
-ulp_mapper_act_result_fields_get(struct bnxt_ulp_mapper_act_tbl_info *tbl,
+ulp_mapper_act_result_fields_get(struct bnxt_ulp_mapper_tbl_info *tbl,
uint32_t *num_rslt_flds,
uint32_t *num_encap_flds)
{
@@ -307,7 +307,7 @@ ulp_mapper_act_result_fields_get(struct bnxt_ulp_mapper_act_tbl_info *tbl,
* returns array of ident fields, or NULL on error
*/
static struct bnxt_ulp_mapper_ident_info *
-ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
+ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_tbl_info *tbl,
uint32_t *num_flds)
{
uint32_t idx;
@@ -522,7 +522,7 @@ ulp_mapper_mark_free(struct bnxt_ulp_context *ulp,
*/
static int32_t
ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_class_tbl_info *tbl,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
struct bnxt_ulp_mapper_ident_info *ident,
uint16_t *val)
{
@@ -892,185 +892,9 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return 0;
}
-/* Function to alloc action record and set the table. */
-static int32_t
-ulp_mapper_action_alloc_and_set(struct bnxt_ulp_mapper_parms *parms,
- struct ulp_blob *blob)
-{
- struct ulp_flow_db_res_params fid_parms;
- struct tf_alloc_tbl_entry_parms alloc_parms = { 0 };
- struct tf_free_tbl_entry_parms free_parms = { 0 };
- struct bnxt_ulp_mapper_act_tbl_info *atbls = parms->atbls;
- int32_t rc = 0;
- int32_t trc;
- uint64_t idx;
- uint32_t tbl_scope_id;
-
- bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, &tbl_scope_id);
-
- /* Set the allocation parameters for the table*/
- alloc_parms.dir = atbls->direction;
- alloc_parms.type = atbls->resource_type;
- alloc_parms.search_enable = atbls->srch_b4_alloc;
- alloc_parms.result = ulp_blob_data_get(blob,
- &alloc_parms.result_sz_in_bytes);
- alloc_parms.tbl_scope_id = tbl_scope_id;
- if (!alloc_parms.result) {
- BNXT_TF_DBG(ERR, "blob is not populated\n");
- return -EINVAL;
- }
-
- rc = tf_alloc_tbl_entry(parms->tfp, &alloc_parms);
- if (rc) {
- BNXT_TF_DBG(ERR, "table type= [%d] dir = [%s] alloc failed\n",
- alloc_parms.type,
- (alloc_parms.dir == TF_DIR_RX) ? "RX" : "TX");
- return rc;
- }
-
- /* Need to calculate the idx for the result record */
- uint64_t tmpidx = alloc_parms.idx;
-
- if (atbls->resource_type == TF_TBL_TYPE_EXT)
- tmpidx = TF_ACT_REC_OFFSET_2_PTR(alloc_parms.idx);
- else
- tmpidx = alloc_parms.idx;
-
- idx = tfp_cpu_to_be_64(tmpidx);
-
- /* Store the allocated index for future use in the regfile */
- rc = ulp_regfile_write(parms->regfile, atbls->regfile_wr_idx, idx);
- if (!rc) {
- BNXT_TF_DBG(ERR, "regfile[%d] write failed\n",
- atbls->regfile_wr_idx);
- rc = -EINVAL;
- goto error;
- }
-
- /*
- * The set_tbl_entry API if search is not enabled or searched entry
- * is not found.
- */
- if (!atbls->srch_b4_alloc || !alloc_parms.hit) {
- struct tf_set_tbl_entry_parms set_parm = { 0 };
- uint16_t length;
-
- set_parm.dir = atbls->direction;
- set_parm.type = atbls->resource_type;
- set_parm.idx = alloc_parms.idx;
- set_parm.data = ulp_blob_data_get(blob, &length);
- set_parm.data_sz_in_bytes = length / 8;
-
- if (set_parm.type == TF_TBL_TYPE_EXT)
- set_parm.tbl_scope_id = tbl_scope_id;
-
- /* set the table entry */
- rc = tf_set_tbl_entry(parms->tfp, &set_parm);
- if (rc) {
- BNXT_TF_DBG(ERR, "table[%d][%s][%d] set failed\n",
- set_parm.type,
- (set_parm.dir == TF_DIR_RX) ? "RX" : "TX",
- set_parm.idx);
- goto error;
- }
- }
-
- /* Link the resource to the flow in the flow db */
- memset(&fid_parms, 0, sizeof(fid_parms));
- fid_parms.direction = atbls->direction;
- fid_parms.resource_func = atbls->resource_func;
- fid_parms.resource_type = atbls->resource_type;
- fid_parms.resource_hndl = alloc_parms.idx;
- fid_parms.critical_resource = 0;
-
- rc = ulp_flow_db_resource_add(parms->ulp_ctx,
- parms->tbl_idx,
- parms->fid,
- &fid_parms);
- if (rc) {
- BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n",
- rc);
- rc = -EINVAL;
- goto error;
- }
-
- return 0;
-error:
-
- free_parms.dir = alloc_parms.dir;
- free_parms.type = alloc_parms.type;
- free_parms.idx = alloc_parms.idx;
-
- trc = tf_free_tbl_entry(parms->tfp, &free_parms);
- if (trc)
- BNXT_TF_DBG(ERR, "Failed to free table entry on failure\n");
-
- return rc;
-}
-
-/*
- * Function to process the action Info. Iterate through the list
- * action info templates and process it.
- */
-static int32_t
-ulp_mapper_action_info_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_act_tbl_info *tbl)
-{
- struct ulp_blob blob;
- struct bnxt_ulp_mapper_result_field_info *flds, *fld;
- uint32_t num_flds = 0;
- uint32_t encap_flds = 0;
- uint32_t i;
- int32_t rc;
- uint16_t bit_size;
-
- if (!tbl || !parms->act_prop || !parms->act_bitmap || !parms->regfile)
- return -EINVAL;
-
- /* use the max size if encap is enabled */
- if (tbl->encap_num_fields)
- bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
- else
- bit_size = tbl->result_bit_size;
- if (!ulp_blob_init(&blob, bit_size, parms->device_params->byte_order)) {
- BNXT_TF_DBG(ERR, "action blob init failed\n");
- return -EINVAL;
- }
-
- flds = ulp_mapper_act_result_fields_get(tbl, &num_flds, &encap_flds);
- if (!flds || !num_flds) {
- BNXT_TF_DBG(ERR, "Template undefined for action\n");
- return -EINVAL;
- }
-
- for (i = 0; i < (num_flds + encap_flds); i++) {
- fld = &flds[i];
- rc = ulp_mapper_result_field_process(parms,
- tbl->direction,
- fld,
- &blob,
- "Action");
- if (rc) {
- BNXT_TF_DBG(ERR, "Action field failed\n");
- return rc;
- }
- /* set the swap index if 64 bit swap is enabled */
- if (parms->device_params->encap_byte_swap && encap_flds) {
- if ((i + 1) == num_flds)
- ulp_blob_encap_swap_idx_set(&blob);
- /* if 64 bit swap is enabled perform the 64bit swap */
- if ((i + 1) == (num_flds + encap_flds))
- ulp_blob_perform_encap_swap(&blob);
- }
- }
-
- rc = ulp_mapper_action_alloc_and_set(parms, &blob);
- return rc;
-}
-
static int32_t
ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_class_tbl_info *tbl,
+ struct bnxt_ulp_mapper_tbl_info *tbl,
uint64_t flow_id)
{
struct ulp_flow_db_res_params fid_parms;
@@ -1112,7 +936,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
static int32_t
ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_class_tbl_info *tbl)
+ struct bnxt_ulp_mapper_tbl_info *tbl)
{
struct ulp_flow_db_res_params fid_parms;
uint32_t act_idx, mark, mark_flag;
@@ -1160,7 +984,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
static int32_t
ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_class_tbl_info *tbl)
+ struct bnxt_ulp_mapper_tbl_info *tbl)
{
struct bnxt_ulp_mapper_class_key_field_info *kflds;
struct ulp_blob key, mask, data;
@@ -1397,7 +1221,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
static int32_t
ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_class_tbl_info *tbl)
+ struct bnxt_ulp_mapper_tbl_info *tbl)
{
struct bnxt_ulp_mapper_class_key_field_info *kflds;
struct bnxt_ulp_mapper_result_field_info *dflds;
@@ -1538,7 +1362,8 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
static int32_t
ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_class_tbl_info *tbl)
+ struct bnxt_ulp_mapper_tbl_info *tbl,
+ bool is_class_tbl)
{
struct bnxt_ulp_mapper_result_field_info *flds;
struct ulp_flow_db_res_params fid_parms;
@@ -1552,22 +1377,49 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct tf_free_tbl_entry_parms free_parms = { 0 };
uint32_t tbl_scope_id;
struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx);
+ uint16_t bit_size;
+ uint32_t encap_flds = 0;
+
+ /* Get the scope id first */
+ rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, &tbl_scope_id);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to get table scope rc=%d\n", rc);
+ return rc;
+ }
- bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx, &tbl_scope_id);
+ /* use the max size if encap is enabled */
+ if (tbl->encap_num_fields)
+ bit_size = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
+ else
+ bit_size = tbl->result_bit_size;
- if (!ulp_blob_init(&data, tbl->result_bit_size,
+ /* Initialize the blob data */
+ if (!ulp_blob_init(&data, bit_size,
parms->device_params->byte_order)) {
BNXT_TF_DBG(ERR, "Failed initial index table blob\n");
return -EINVAL;
}
- flds = ulp_mapper_result_fields_get(tbl, &num_flds);
+ /* Get the result fields list */
+ if (is_class_tbl)
+ flds = ulp_mapper_result_fields_get(tbl, &num_flds);
+ else
+ flds = ulp_mapper_act_result_fields_get(tbl, &num_flds,
+ &encap_flds);
+
if (!flds || !num_flds) {
- BNXT_TF_DBG(ERR, "Template undefined for action\n");
+ BNXT_TF_DBG(ERR, "template undefined for the index table\n");
return -EINVAL;
}
- for (i = 0; i < num_flds; i++) {
+ /* process the result fields, loop through them */
+ for (i = 0; i < (num_flds + encap_flds); i++) {
+ /* set the swap index if encap swap bit is enabled */
+ if (parms->device_params->encap_byte_swap && encap_flds &&
+ ((i + 1) == num_flds))
+ ulp_blob_encap_swap_idx_set(&data);
+
+ /* Process the result fields */
rc = ulp_mapper_result_field_process(parms,
tbl->direction,
&flds[i],
@@ -1577,27 +1429,50 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "data field failed\n");
return rc;
}
+
+ /* if encap bit swap is enabled perform the bit swap */
+ if (parms->device_params->encap_byte_swap && encap_flds) {
+ if ((i + 1) == (num_flds + encap_flds))
+ ulp_blob_perform_encap_swap(&data);
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ if ((i + 1) == (num_flds + encap_flds)) {
+ BNXT_TF_DBG(INFO, "Dump fter encap swap\n");
+ ulp_mapper_blob_dump(&data);
+ }
+#endif
+ }
}
+ /* Perform the tf table allocation by filling the alloc params */
aparms.dir = tbl->direction;
aparms.type = tbl->resource_type;
aparms.search_enable = tbl->srch_b4_alloc;
aparms.result = ulp_blob_data_get(&data, &tmplen);
- aparms.result_sz_in_bytes = ULP_SZ_BITS2BYTES(tbl->result_bit_size);
+ aparms.result_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
aparms.tbl_scope_id = tbl_scope_id;
/* All failures after the alloc succeeds require a free */
rc = tf_alloc_tbl_entry(tfp, &aparms);
if (rc) {
BNXT_TF_DBG(ERR, "Alloc table[%d][%s] failed rc=%d\n",
- tbl->resource_type,
- (tbl->direction == TF_DIR_RX) ? "RX" : "TX",
+ aparms.type,
+ (aparms.dir == TF_DIR_RX) ? "RX" : "TX",
rc);
return rc;
}
+ /*
+ * calculate the idx for the result record, for external EM the offset
+ * needs to be shifted accordingly. If external non-inline table types
+ * are used then need to revisit this logic.
+ */
+ if (aparms.type == TF_TBL_TYPE_EXT)
+ idx = TF_ACT_REC_OFFSET_2_PTR(aparms.idx);
+ else
+ idx = aparms.idx;
+
/* Always storing values in Regfile in BE */
- idx = tfp_cpu_to_be_64(aparms.idx);
+ idx = tfp_cpu_to_be_64(idx);
rc = ulp_regfile_write(parms->regfile, tbl->regfile_wr_idx, idx);
if (!rc) {
BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n",
@@ -1605,23 +1480,22 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
goto error;
}
- if (!tbl->srch_b4_alloc) {
+ /* Perform the tf table set by filling the set params */
+ if (!tbl->srch_b4_alloc || !aparms.hit) {
sparms.dir = tbl->direction;
sparms.type = tbl->resource_type;
sparms.data = ulp_blob_data_get(&data, &tmplen);
- sparms.data_sz_in_bytes =
- ULP_SZ_BITS2BYTES(tbl->result_bit_size);
+ sparms.data_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
sparms.idx = aparms.idx;
sparms.tbl_scope_id = tbl_scope_id;
rc = tf_set_tbl_entry(tfp, &sparms);
if (rc) {
BNXT_TF_DBG(ERR, "Set table[%d][%s][%d] failed rc=%d\n",
- tbl->resource_type,
- (tbl->direction == TF_DIR_RX) ? "RX" : "TX",
+ sparms.type,
+ (sparms.dir == TF_DIR_RX) ? "RX" : "TX",
sparms.idx,
rc);
-
goto error;
}
}
@@ -1664,7 +1538,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
static int32_t
ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms,
- struct bnxt_ulp_mapper_class_tbl_info *tbl)
+ struct bnxt_ulp_mapper_tbl_info *tbl)
{
struct bnxt_ulp_mapper_class_key_field_info *kflds;
struct bnxt_ulp_mapper_cache_entry *cache_entry;
@@ -1858,6 +1732,7 @@ ulp_mapper_action_tbls_process(struct bnxt_ulp_mapper_parms *parms)
{
uint32_t i;
int32_t rc = 0;
+ struct bnxt_ulp_mapper_tbl_info *tbl;
if (!parms->atbls || !parms->num_atbls) {
BNXT_TF_DBG(ERR, "No action tables for template[%d][%d].\n",
@@ -1866,9 +1741,21 @@ ulp_mapper_action_tbls_process(struct bnxt_ulp_mapper_parms *parms)
}
for (i = 0; i < parms->num_atbls; i++) {
- rc = ulp_mapper_action_info_process(parms, &parms->atbls[i]);
- if (rc)
- return rc;
+ tbl = &parms->atbls[i];
+ switch (tbl->resource_func) {
+ case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
+ rc = ulp_mapper_index_tbl_process(parms, tbl, false);
+ break;
+ default:
+ BNXT_TF_DBG(ERR, "Unexpected action resource %d\n",
+ tbl->resource_func);
+ return -EINVAL;
+ }
+ }
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Resource type %d failed\n",
+ tbl->resource_func);
+ return rc;
}
return rc;
@@ -1891,7 +1778,7 @@ ulp_mapper_class_tbls_process(struct bnxt_ulp_mapper_parms *parms)
}
for (i = 0; i < parms->num_ctbls; i++) {
- struct bnxt_ulp_mapper_class_tbl_info *tbl = &parms->ctbls[i];
+ struct bnxt_ulp_mapper_tbl_info *tbl = &parms->ctbls[i];
switch (tbl->resource_func) {
case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE:
@@ -1901,7 +1788,7 @@ ulp_mapper_class_tbls_process(struct bnxt_ulp_mapper_parms *parms)
rc = ulp_mapper_em_tbl_process(parms, tbl);
break;
case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
- rc = ulp_mapper_index_tbl_process(parms, tbl);
+ rc = ulp_mapper_index_tbl_process(parms, tbl, true);
break;
case BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE:
rc = ulp_mapper_cache_tbl_process(parms, tbl);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 0c9bb86..67410c9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -15,7 +15,6 @@
#include "bnxt_ulp.h"
#include "ulp_utils.h"
-#define ULP_SZ_BITS2BYTES(x) (((x) + 7) / 8)
#define ULP_IDENTS_INVALID ((uint16_t)0xffff)
/*
@@ -56,10 +55,10 @@ struct bnxt_ulp_mapper_data {
struct bnxt_ulp_mapper_parms {
uint32_t dev_id;
uint32_t act_tid;
- struct bnxt_ulp_mapper_act_tbl_info *atbls;
+ struct bnxt_ulp_mapper_tbl_info *atbls; /* action table */
uint32_t num_atbls;
uint32_t class_tid;
- struct bnxt_ulp_mapper_class_tbl_info *ctbls;
+ struct bnxt_ulp_mapper_tbl_info *ctbls; /* class table */
uint32_t num_ctbls;
struct ulp_rte_act_prop *act_prop;
struct ulp_rte_act_bitmap *act_bitmap;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 395d33b..bac3bce 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -587,7 +587,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
}
};
-struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
+struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
@@ -602,6 +602,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.result_start_idx = 0,
.result_bit_size = 10,
.result_num_fields = 1,
+ .encap_num_fields = 0,
.ident_start_idx = 0,
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
@@ -623,6 +624,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.result_start_idx = 1,
.result_bit_size = 64,
.result_num_fields = 13,
+ .encap_num_fields = 0,
.ident_start_idx = 1,
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
@@ -644,6 +646,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.result_start_idx = 14,
.result_bit_size = 10,
.result_num_fields = 1,
+ .encap_num_fields = 0,
.ident_start_idx = 1,
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
@@ -665,6 +668,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.result_start_idx = 15,
.result_bit_size = 38,
.result_num_fields = 8,
+ .encap_num_fields = 0,
.ident_start_idx = 2,
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
@@ -686,6 +690,7 @@ struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[] = {
.result_start_idx = 23,
.result_bit_size = 64,
.result_num_fields = 9,
+ .encap_num_fields = 0,
.ident_start_idx = 2,
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_YES,
@@ -1615,7 +1620,7 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
}
};
-struct bnxt_ulp_mapper_act_tbl_info ulp_act_tbl_list[] = {
+struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index b51cca2..df3519d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -155,7 +155,7 @@ struct bnxt_ulp_mapper_tbl_list_info {
uint32_t num_tbls;
};
-struct bnxt_ulp_mapper_class_tbl_info {
+struct bnxt_ulp_mapper_tbl_info {
enum bnxt_ulp_resource_func resource_func;
uint32_t resource_type; /* TF_ enum type */
enum bnxt_ulp_resource_sub_type resource_sub_type;
@@ -175,6 +175,7 @@ struct bnxt_ulp_mapper_class_tbl_info {
uint32_t result_start_idx;
uint16_t result_bit_size;
uint16_t result_num_fields;
+ uint16_t encap_num_fields;
/* Information for accessing the ulp_ident_list */
uint32_t ident_start_idx;
@@ -185,20 +186,6 @@ struct bnxt_ulp_mapper_class_tbl_info {
enum bnxt_ulp_vfr_flag vfr_flag;
};
-struct bnxt_ulp_mapper_act_tbl_info {
- enum bnxt_ulp_resource_func resource_func;
- uint32_t resource_type; /* TF_ enum type */
- enum bnxt_ulp_resource_sub_type resource_sub_type;
- uint8_t direction;
- uint8_t srch_b4_alloc;
- uint32_t result_start_idx;
- uint16_t result_bit_size;
- uint16_t encap_num_fields;
- uint16_t result_num_fields;
-
- enum bnxt_ulp_regfile_index regfile_wr_idx;
-};
-
struct bnxt_ulp_mapper_class_key_field_info {
uint8_t description[64];
enum bnxt_ulp_mask_opc mask_opcode;
@@ -263,8 +250,8 @@ extern struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[];
* table entry to include the start index and number of instructions in the
* field lists.
*/
-extern struct bnxt_ulp_mapper_class_tbl_info ulp_class_tbl_list[];
-extern struct bnxt_ulp_mapper_act_tbl_info ulp_act_tbl_list[];
+extern struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[];
+extern struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[];
/*
* The ulp_class_result_field_list provides the instructions for creating result
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 18/36] net/bnxt: use vport in the phy port act handler
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (16 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 17/36] net/bnxt: extend index table processing to process action templates Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 19/36] net/bnxt: add enum to the critical resource Somnath Kotur
` (17 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The phy port action handler should get vport details and not
vnic id. The fix is to calculate the vport of the given
port.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 842466d..3dd941f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -1284,7 +1284,7 @@ ulp_rte_phy_port_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *prm)
{
const struct rte_flow_action_phy_port *phy_port;
- uint32_t pid;
+ uint32_t vport;
phy_port = action_item->conf;
if (phy_port) {
@@ -1293,10 +1293,12 @@ ulp_rte_phy_port_act_handler(const struct rte_flow_action *action_item,
"Parse Err:Port Original not supported\n");
return BNXT_TF_RC_PARSE_ERR;
}
- pid = bnxt_get_vnic_id(phy_port->index);
- pid = rte_cpu_to_be_32(pid);
+ /* Get the vport of the physical port */
+ /* TBD: shall be changed later to portdb call */
+ vport = 1 << phy_port->index;
+ vport = rte_cpu_to_be_32(vport);
memcpy(&prm->act_prop.act_details[BNXT_ULP_ACT_PROP_IDX_VPORT],
- &pid, BNXT_ULP_ACT_PROP_SZ_VPORT);
+ &vport, BNXT_ULP_ACT_PROP_SZ_VPORT);
}
/* Update the hdr_bitmap with count */
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 19/36] net/bnxt: add enum to the critical resource
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (17 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 18/36] net/bnxt: use vport in the phy port act handler Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 20/36] net/bnxt: rename regfile_wr_idx to regfile_idx Somnath Kotur
` (16 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The critical resource field in the template table is assigned
enumeration values instead of hard coded values.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 14 +++++++-------
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 10 +++++-----
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 6 ++++++
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +-
4 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 7f7335a..41c4f2f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -568,7 +568,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_func = ident->resource_func;
fid_parms.resource_type = ident->ident_type;
fid_parms.resource_hndl = iparms.id;
- fid_parms.critical_resource = 0;
+ fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
parms->tbl_idx,
@@ -922,7 +922,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
}
fid_parms.direction = tbl->direction;
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID;
- fid_parms.critical_resource = 0;
+ fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = gfid;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
@@ -970,7 +970,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
}
fid_parms.direction = tbl->direction;
fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID;
- fid_parms.critical_resource = 0;
+ fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
fid_parms.resource_type = mark_flag;
fid_parms.resource_hndl = act_idx;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
@@ -1506,7 +1506,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
fid_parms.resource_func = tbl->resource_func;
fid_parms.resource_type = tbl->resource_type;
fid_parms.resource_hndl = aparms.idx;
- fid_parms.critical_resource = 0;
+ fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_add(parms->ulp_ctx,
parms->tbl_idx,
@@ -1870,7 +1870,7 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
* Set the critical resource on the first resource del, then iterate
* while status is good
*/
- res_parms.critical_resource = 1;
+ res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES;
rc = ulp_flow_db_resource_del(ulp_ctx, tbl_type, fid, &res_parms);
if (rc) {
@@ -1896,8 +1896,8 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
tbl_type, fid, res_parms.resource_func,
res_parms.resource_hndl, trc);
- /* All subsequent call require the critical_resource be zero */
- res_parms.critical_resource = 0;
+ /* All subsequent call require the non-critical_resource */
+ res_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
rc = ulp_flow_db_resource_del(ulp_ctx,
tbl_type,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index bac3bce..a9e1681 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -607,7 +607,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
- .critical_resource = 0,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -629,7 +629,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
- .critical_resource = 0,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -651,7 +651,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 1,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
- .critical_resource = 0,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -673,7 +673,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
- .critical_resource = 0,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
@@ -695,7 +695,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.ident_nums = 0,
.mark_enable = BNXT_ULP_MARK_ENABLE_YES,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
- .critical_resource = 1,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index a850e22..44ef839 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -120,6 +120,12 @@ enum bnxt_ulp_cf_idx {
BNXT_ULP_CF_IDX_LAST = 28
};
+enum bnxt_ulp_critical_resource {
+ BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
+ BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
+ BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
+};
+
enum bnxt_ulp_device_id {
BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
BNXT_ULP_DEVICE_ID_THOR = 1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index df3519d..aaa91c3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -162,7 +162,7 @@ struct bnxt_ulp_mapper_tbl_info {
uint8_t direction;
uint32_t priority;
uint8_t srch_b4_alloc;
- uint32_t critical_resource;
+ enum bnxt_ulp_critical_resource critical_resource;
/* Information for accessing the ulp_key_field_list */
uint32_t key_start_idx;
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 20/36] net/bnxt: rename regfile_wr_idx to regfile_idx
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (18 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 19/36] net/bnxt: add enum to the critical resource Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 21/36] net/bnxt: remove unused enum in regfile index Somnath Kotur
` (15 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The regfile index shall be used for both write and read operations.
Hence the field is renamed.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 8 ++++----
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 16 ++++++++--------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 4 ++--
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 41c4f2f..b0ef966 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -540,7 +540,7 @@ ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
- idx = ident->regfile_wr_idx;
+ idx = ident->regfile_idx;
iparms.ident_type = ident->ident_type;
iparms.dir = tbl->direction;
@@ -1473,10 +1473,10 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Always storing values in Regfile in BE */
idx = tfp_cpu_to_be_64(idx);
- rc = ulp_regfile_write(parms->regfile, tbl->regfile_wr_idx, idx);
+ rc = ulp_regfile_write(parms->regfile, tbl->regfile_idx, idx);
if (!rc) {
BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n",
- tbl->regfile_wr_idx);
+ tbl->regfile_idx);
goto error;
}
@@ -1633,7 +1633,7 @@ ulp_mapper_cache_tbl_process(struct bnxt_ulp_mapper_parms *parms,
for (i = 0; i < num_idents; i++) {
regval = (uint64_t)cache_entry->idents[i];
if (!ulp_regfile_write(parms->regfile,
- idents[i].regfile_wr_idx,
+ idents[i].regfile_idx,
tfp_cpu_to_be_64(regval))) {
BNXT_TF_DBG(ERR,
"Failed to write to regfile\n");
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index a9e1681..0e3c061 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -608,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -630,7 +630,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
@@ -652,7 +652,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
@@ -674,7 +674,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.mark_enable = BNXT_ULP_MARK_ENABLE_NO,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
@@ -696,7 +696,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.mark_enable = BNXT_ULP_MARK_ENABLE_YES,
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
}
};
@@ -1598,14 +1598,14 @@ struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.ident_type = TF_IDENT_TYPE_L2_CTXT,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
.ident_type = TF_IDENT_TYPE_EM_PROF,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
.ident_bit_size = 10,
.ident_bit_pos = 0
}
@@ -1631,7 +1631,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0,
- .regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index aaa91c3..9b1bdbb 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -182,7 +182,7 @@ struct bnxt_ulp_mapper_tbl_info {
uint16_t ident_nums;
uint8_t mark_enable;
- enum bnxt_ulp_regfile_index regfile_wr_idx;
+ enum bnxt_ulp_regfile_index regfile_idx;
enum bnxt_ulp_vfr_flag vfr_flag;
};
@@ -209,7 +209,7 @@ struct bnxt_ulp_mapper_ident_info {
uint16_t ident_type;
uint16_t ident_bit_size;
uint16_t ident_bit_pos;
- enum bnxt_ulp_regfile_index regfile_wr_idx;
+ enum bnxt_ulp_regfile_index regfile_idx;
};
struct bnxt_ulp_glb_resource_info {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 21/36] net/bnxt: remove unused enum in regfile index
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (19 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 20/36] net/bnxt: rename regfile_wr_idx to regfile_idx Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 22/36] net/bnxt: rename an enum in the " Somnath Kotur
` (14 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Removed the unsed enum BNXT_ULP_REGFILE_INDEX_CACHE_ENTRY_PTR
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 44ef839..3e5e27b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -7,7 +7,7 @@
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 16
+#define BNXT_ULP_REGFILE_MAX_SZ 15
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
@@ -201,9 +201,8 @@ enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
- BNXT_ULP_REGFILE_INDEX_CACHE_ENTRY_PTR = 14,
- BNXT_ULP_REGFILE_INDEX_NOT_USED = 15,
- BNXT_ULP_REGFILE_INDEX_LAST = 16
+ BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
+ BNXT_ULP_REGFILE_INDEX_LAST = 15
};
enum bnxt_ulp_result_opc {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 22/36] net/bnxt: rename an enum in the regfile index
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (20 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 21/36] net/bnxt: remove unused enum in regfile index Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 23/36] net/bnxt: rename the enums in the bnxt_ulp_resource_sub_type Somnath Kotur
` (13 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN is renamed to
BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR since it is the main
action pointer.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 6 +++---
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index b0ef966..300dca3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -954,7 +954,7 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
mark = tfp_be_to_cpu_32(mark);
if (!ulp_regfile_read(parms->regfile,
- BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
&val64)) {
BNXT_TF_DBG(ERR, "read action ptr main failed\n");
return -EINVAL;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 0e3c061..a1273b6 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -1537,8 +1537,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 33,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
- .result_operand = {(BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN & 0xff,
+ .result_operand = {(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1631,7 +1631,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0,
- .regfile_idx = BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 3e5e27b..bcd813d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -196,7 +196,7 @@ enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
- BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 9,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 23/36] net/bnxt: rename the enums in the bnxt_ulp_resource_sub_type
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (21 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 22/36] net/bnxt: rename an enum in the " Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 24/36] net/bnxt: add a devarg to set max flow count Somnath Kotur
` (12 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The enums in the bnxt_ulp_resource_sub_type are renamed to reflect
the table types explicitly.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 30 ++++++++++++++++++++----------
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 14 +++++++-------
2 files changed, 27 insertions(+), 17 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index a1273b6..6c547da 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -294,16 +294,20 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
};
struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
- [BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE << 1 | TF_DIR_RX] = {
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_RX] = {
.num_entries = 16384
},
- [BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE << 1 | TF_DIR_TX] = {
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_TX] = {
.num_entries = 16384
},
- [BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE << 1 | TF_DIR_RX] = {
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_RX] = {
.num_entries = 16384
},
- [BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE << 1 | TF_DIR_TX] = {
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_TX] = {
.num_entries = 16384
}
};
@@ -591,7 +595,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
- .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_NOT_USED,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -613,7 +618,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
- .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -635,7 +641,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_NOT_USED,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -657,7 +664,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -679,7 +687,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
.resource_type = TF_MEM_EXTERNAL,
- .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_NOT_USED,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -1624,7 +1633,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
- .resource_sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_IT_NORMAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
.result_start_idx = 0,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index bcd813d..0b6a2d3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -291,13 +291,13 @@ enum bnxt_ulp_resource_func {
};
enum bnxt_ulp_resource_sub_type {
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0,
- BNXT_ULP_RESOURCE_SUB_TYPE_IT_NORMAL = 0,
- BNXT_ULP_RESOURCE_SUB_TYPE_IT_VFR_ACT_IDX = 1,
- BNXT_ULP_RESOURCE_SUB_TYPE_IT_INT_CNT_IDX = 2,
- BNXT_ULP_RESOURCE_SUB_TYPE_IT_EXT_CNT_IDX = 3,
- BNXT_ULP_RESOURCE_SUB_TYPE_TT_L2_CNTXT_TCAM_CACHE = 0,
- BNXT_ULP_RESOURCE_SUB_TYPE_TT_PROFILE_TCAM_CACHE = 1
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
};
enum bnxt_ulp_sym {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 24/36] net/bnxt: add a devarg to set max flow count
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (22 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 23/36] net/bnxt: rename the enums in the bnxt_ulp_resource_sub_type Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 25/36] net/bnxt: add support for vxlan encap and decap templates Somnath Kotur
` (11 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Shuanglin Wang <shuanglin.wang@broadcom.com>
User could set max flow count by passing a devarg
"-w 0000:0d:00.0,max_num_kflows=64" to a DPDK application;
The value must be not less than 32K and be power-of-2;
the default value is 32K.
Signed-off-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 1 +
drivers/net/bnxt/bnxt_ethdev.c | 62 ++++++++++++++++++++++++++++++++++++--
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 35 +++++++++++++++++++++
3 files changed, 96 insertions(+), 2 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 2c3aef6..79e9b28 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -725,6 +725,7 @@ struct bnxt {
struct bnxt_ulp_context *ulp_ctx;
struct bnxt_flow_stat_info *flow_stat;
uint8_t flow_xstat;
+ uint16_t max_num_kflows;
};
#define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index e8b4c05..7022f6d 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -129,9 +129,11 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
#define BNXT_DEVARG_TRUFLOW "host-based-truflow"
#define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
+#define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
static const char *const bnxt_dev_args[] = {
BNXT_DEVARG_TRUFLOW,
BNXT_DEVARG_FLOW_XSTAT,
+ BNXT_DEVARG_MAX_NUM_KFLOWS,
NULL
};
@@ -147,6 +149,19 @@ static const char *const bnxt_dev_args[] = {
*/
#define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
+/*
+ * max_num_kflows must be >= 32
+ * and must be a power-of-2 supported value
+ * return: 1 -> invalid
+ * 0 -> valid
+ */
+static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
+{
+ if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
+ return 1;
+ return 0;
+}
+
static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
@@ -5390,6 +5405,42 @@ bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
return 0;
}
+static int
+bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
+ const char *value, void *opaque_arg)
+{
+ struct bnxt *bp = opaque_arg;
+ unsigned long max_num_kflows;
+ char *end = NULL;
+
+ if (!value || !opaque_arg) {
+ PMD_DRV_LOG(ERR,
+ "Invalid parameter passed to max_num_kflows devarg.\n");
+ return -EINVAL;
+ }
+
+ max_num_kflows = strtoul(value, &end, 10);
+ if (end == NULL || *end != '\0' ||
+ (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
+ PMD_DRV_LOG(ERR,
+ "Invalid parameter passed to max_num_kflows devarg.\n");
+ return -EINVAL;
+ }
+
+ if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
+ PMD_DRV_LOG(ERR,
+ "Invalid value passed to max_num_kflows devarg.\n");
+ return -EINVAL;
+ }
+
+ bp->max_num_kflows = max_num_kflows;
+ if (bp->max_num_kflows)
+ PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
+ max_num_kflows);
+
+ return 0;
+}
+
static void
bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
{
@@ -5404,18 +5455,25 @@ bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
/*
* Handler for "truflow" devarg.
- * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
+ * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
*/
rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
bnxt_parse_devarg_truflow, bp);
/*
* Handler for "flow_xstat" devarg.
- * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
+ * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
*/
rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
bnxt_parse_devarg_flow_xstat, bp);
+ /*
+ * Handler for "max_num_kflows" devarg.
+ * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
+ */
+ rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
+ bnxt_parse_devarg_max_num_kflows, bp);
+
rte_kvargs_free(kvlist);
}
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 872c1ab..00e21fa 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -276,6 +276,38 @@ ulp_ctx_init(struct bnxt *bp,
return rc;
}
+/* The function to initialize ulp dparms with devargs */
+static int32_t
+ulp_dparms_init(struct bnxt *bp,
+ struct bnxt_ulp_context *ulp_ctx)
+{
+ struct bnxt_ulp_device_params *dparms;
+ uint32_t dev_id;
+
+ if (!bp->max_num_kflows)
+ return -EINVAL;
+
+ if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) {
+ BNXT_TF_DBG(DEBUG, "Failed to get device id\n");
+ return -EINVAL;
+ }
+
+ dparms = bnxt_ulp_device_params_get(dev_id);
+ if (!dparms) {
+ BNXT_TF_DBG(DEBUG, "Failed to get device parms\n");
+ return -EINVAL;
+ }
+
+ /* num_flows = max_num_kflows * 1024 */
+ dparms->num_flows = bp->max_num_kflows * 1024;
+ /* GFID = 2 * num_flows */
+ dparms->gfid_entries = dparms->num_flows * 2;
+ BNXT_TF_DBG(DEBUG, "Set the number of flows = %"PRIu64"\n",
+ dparms->num_flows);
+
+ return 0;
+}
+
static int32_t
ulp_ctx_attach(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_session_state *session)
@@ -497,6 +529,9 @@ bnxt_ulp_init(struct bnxt *bp)
goto jump_to_error;
}
+ /* Initialize ulp dparms with values devargs passed */
+ rc = ulp_dparms_init(bp, bp->ulp_ctx);
+
/* create the port database */
rc = ulp_port_db_init(bp->ulp_ctx);
if (rc) {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 25/36] net/bnxt: add support for vxlan encap and decap templates
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (23 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 24/36] net/bnxt: add a devarg to set max flow count Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 26/36] net/bnxt: flow db api to get vf rep action record Somnath Kotur
` (10 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Two templates are added to ulp template db, an ingress rule
for vxlan decap and an egress rule for vxlan encap.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db.c | 3310 +++++++++++++++++++++--
drivers/net/bnxt/tf_ulp/ulp_template_db.h | 157 +-
drivers/net/bnxt/tf_ulp/ulp_template_field_db.h | 161 ++
3 files changed, 3365 insertions(+), 263 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index 6c547da..e9cf78c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -537,18 +537,20 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
};
uint32_t bnxt_ulp_encap_vtag_map[] = {
- [0] = BNXT_ULP_ENCAP_VTAG_ENCODING_NOP,
- [1] = BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI,
- [2] = BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI
+ [0] = BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP,
+ [1] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
+ [2] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI
};
uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
- [BNXT_ULP_CLASS_HID_0013] = 1
+ [BNXT_ULP_CLASS_HID_0080] = 1,
+ [BNXT_ULP_CLASS_HID_0000] = 2,
+ [BNXT_ULP_CLASS_HID_0087] = 3
};
struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
[1] = {
- .class_hid = BNXT_ULP_CLASS_HID_0013,
+ .class_hid = BNXT_ULP_CLASS_HID_0080,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
@@ -563,22 +565,79 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 0,
.act_vnic = 0,
.wc_pri = 0
+ },
+ [2] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0000,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .field_sig = { .bits =
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 1,
+ .act_vnic = 0,
+ .wc_pri = 0
+ },
+ [3] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0087,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 2,
+ .act_vnic = 0,
+ .wc_pri = 0
}
};
uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
- [BNXT_ULP_ACT_HID_0029] = 1
+ [BNXT_ULP_ACT_HID_00a1] = 1,
+ [BNXT_ULP_ACT_HID_0040] = 2,
+ [BNXT_ULP_ACT_HID_0029] = 3
};
struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
[1] = {
+ .act_hid = BNXT_ULP_ACT_HID_00a1,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 0
+ },
+ [2] = {
+ .act_hid = BNXT_ULP_ACT_HID_0040,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VPORT |
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 1
+ },
+ [3] = {
.act_hid = BNXT_ULP_ACT_HID_0029,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_VNIC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 0
+ .act_tid = 2
}
};
@@ -588,6 +647,18 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
.start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 5
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 10
}
};
@@ -706,6 +777,236 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.vfr_flag = BNXT_ULP_VFR_FLAG_NO,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 71,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 32,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 73,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 33,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 86,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 46,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 89,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 47,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 131,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 55,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 142,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 64,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 144,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 157,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 78,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 160,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 79,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 202,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 87,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
}
};
@@ -716,7 +1017,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -727,7 +1029,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -761,12 +1064,14 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 8,
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
- .mask_operand = {(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ .mask_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -831,7 +1136,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -858,12 +1164,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD,
- .spec_operand = {
- (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
- BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 7,
@@ -883,7 +1186,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
- .spec_operand = {(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -891,20 +1195,24 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -912,8 +1220,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -921,8 +1231,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -930,8 +1242,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -939,8 +1253,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -948,8 +1264,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
@@ -957,7 +1275,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -967,8 +1286,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -976,8 +1297,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -985,8 +1308,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -994,8 +1319,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
@@ -1003,8 +1330,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
@@ -1012,7 +1341,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1022,8 +1352,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1031,8 +1363,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
@@ -1040,8 +1374,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
@@ -1049,7 +1385,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1059,17 +1396,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1077,8 +1418,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
@@ -1086,7 +1429,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1096,8 +1440,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1105,8 +1451,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1114,8 +1462,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1123,8 +1473,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1132,8 +1484,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
@@ -1141,18 +1495,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1160,8 +1517,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1169,8 +1528,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1178,8 +1539,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
@@ -1187,8 +1550,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
@@ -1196,7 +1561,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1206,8 +1572,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -1215,8 +1583,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 9,
@@ -1224,8 +1594,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 7,
@@ -1245,8 +1618,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
@@ -1254,8 +1629,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
@@ -1263,7 +1640,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_PKT_TYPE_L2,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1300,7 +1678,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {(BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1311,7 +1690,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {(BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1322,7 +1702,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
- .spec_operand = {BNXT_ULP_SYM_IP_PROTO_UDP,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1332,7 +1713,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {(BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1343,7 +1725,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {(BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1372,7 +1755,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
- .spec_operand = {(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1383,71 +1767,2402 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
- .spec_operand = {(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
- }
-};
-
-struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
- {
- .field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
- .result_operand = {(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
- .result_operand = {(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 7,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
- .result_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 6,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
+ [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 1
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 2
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 0,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_TX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 26,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 12,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 64,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 3,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1459,19 +4174,36 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 16,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 2,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1482,23 +4214,20 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
-
{
- .field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
- .result_operand = {(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 4,
+ .field_bit_size = 14,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 8,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1510,31 +4239,33 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 10,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {(0x00f9 >> 8) & 0xff,
- 0x00f9 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 5,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
- .result_operand = {(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -1544,17 +4275,45 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 33,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
- .result_operand = {(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -1564,21 +4323,48 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 5,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 9,
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {(0x00c5 >> 8) & 0xff,
- 0x00c5 & 0xff,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 11,
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1586,7 +4372,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 2,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -1596,56 +4382,108 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
.field_bit_size = 1,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
- }
-};
-
-struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
+ },
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_L2_CTXT,
- .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
- .ident_bit_size = 10,
- .ident_bit_pos = 0
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .ident_type = TF_IDENT_TYPE_EM_PROF,
- .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
- .ident_bit_size = 10,
- .ident_bit_pos = 0
- }
-};
-
-struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
- [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
- BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
- .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 1,
- .start_tbl_idx = 0
- }
-};
-
-struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_EXT,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
- .direction = TF_DIR_RX,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .result_start_idx = 0,
- .result_bit_size = 128,
- .result_num_fields = 26,
- .encap_num_fields = 0,
- .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
- }
-};
-
-struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
{
.field_bit_size = 14,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
@@ -1769,14 +4607,16 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
{
.field_bit_size = 4,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
- .result_operand = {BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
- .result_operand = {(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
@@ -1789,17 +4629,9 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT,
- .result_operand = {
- ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
- ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
- ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
- ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
- ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
- ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
- ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
- (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index 0b6a2d3..0f47b8f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -12,14 +12,14 @@
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 2
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
-#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7919
-#define BNXT_ULP_CLASS_HID_SHFTR 0
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
+#define BNXT_ULP_CLASS_HID_SHFTR 16
#define BNXT_ULP_CLASS_HID_SHFTL 23
#define BNXT_ULP_CLASS_HID_MASK 255
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 2
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
#define BNXT_ULP_ACT_HID_SHFTR 0
@@ -232,25 +232,6 @@ enum bnxt_ulp_spec_opc {
BNXT_ULP_SPEC_OPC_LAST = 6
};
-enum bnxt_ulp_encap_vtag_encoding {
- BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_ECAP_PRI = 4,
- BNXT_ULP_ENCAP_VTAG_ENCODING_DTAG_REMAP_DIFFSERV = 5,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_ECAP_PRI = 6,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_DIFFSERV = 7,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_0 = 8,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_1 = 9,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_2 = 10,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_3 = 11,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_4 = 12,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_5 = 13,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_6 = 14,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NO_TAG_REMAP_PRI_7 = 15,
- BNXT_ULP_ENCAP_VTAG_ENCODING_NOP = 0,
- BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_ECAP_PRI = 1,
- BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_IVLAN_PRI = 2,
- BNXT_ULP_ENCAP_VTAG_ENCODING_STAG_REMAP_DIFFSERV = 3
-};
-
enum bnxt_ulp_vfr_flag {
BNXT_ULP_VFR_FLAG_NO = 0,
BNXT_ULP_VFR_FLAG_YES = 1,
@@ -301,6 +282,9 @@ enum bnxt_ulp_resource_sub_type {
};
enum bnxt_ulp_sym {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_AGG_ERROR_NO = 0,
+ BNXT_ULP_SYM_AGG_ERROR_YES = 1,
BNXT_ULP_SYM_BIG_ENDIAN = 0,
BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
@@ -332,42 +316,160 @@ enum bnxt_ulp_sym {
BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
BNXT_ULP_SYM_ECV_VALID_NO = 0,
BNXT_ULP_SYM_ECV_VALID_YES = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
+ BNXT_ULP_SYM_HREC_NEXT_NO = 0,
+ BNXT_ULP_SYM_HREC_NEXT_YES = 1,
+ BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
+ BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
+ BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
+ BNXT_ULP_SYM_IP_PROTO_TCP = 6,
BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+ BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+ BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+ BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+ BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
+ BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
BNXT_ULP_SYM_NO = 0,
+ BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
BNXT_ULP_SYM_POP_VLAN_NO = 0,
BNXT_ULP_SYM_POP_VLAN_YES = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
+ BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
+ BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
+ BNXT_ULP_SYM_RESERVED_IGNORE = 0,
BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
@@ -377,6 +479,9 @@ enum bnxt_ulp_sym {
BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_YES = 1
};
@@ -470,10 +575,14 @@ enum bnxt_ulp_act_prop_idx {
};
enum bnxt_ulp_class_hid {
- BNXT_ULP_CLASS_HID_0013 = 0x0013
+ BNXT_ULP_CLASS_HID_0080 = 0x0080,
+ BNXT_ULP_CLASS_HID_0000 = 0x0000,
+ BNXT_ULP_CLASS_HID_0087 = 0x0087
};
enum bnxt_ulp_act_hid {
+ BNXT_ULP_ACT_HID_00a1 = 0x00a1,
+ BNXT_ULP_ACT_HID_0040 = 0x0040,
BNXT_ULP_ACT_HID_0029 = 0x0029
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
index 2655b83..f69082d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
@@ -33,6 +33,87 @@ enum bnxt_ulp_hf0 {
BNXT_ULP_HF0_IDX_O_UDP_CSUM = 23
};
+enum bnxt_ulp_hf1 {
+ BNXT_ULP_HF1_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF1_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF1_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF1_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF1_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF1_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF1_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF1_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF1_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF1_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF1_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF1_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF1_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF1_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF1_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF1_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF1_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF1_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf2 {
+ BNXT_ULP_HF2_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF2_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF2_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF2_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF2_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF2_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF2_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF2_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF2_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF2_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF2_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF2_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF2_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF2_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF2_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF2_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF2_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF2_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF2_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF2_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF2_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF2_IDX_O_UDP_CSUM = 23,
+ BNXT_ULP_HF2_IDX_T_VXLAN_FLAGS = 24,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD0 = 25,
+ BNXT_ULP_HF2_IDX_T_VXLAN_VNI = 26,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD1 = 27,
+ BNXT_ULP_HF2_IDX_I_ETH_DMAC = 28,
+ BNXT_ULP_HF2_IDX_I_ETH_SMAC = 29,
+ BNXT_ULP_HF2_IDX_I_ETH_TYPE = 30,
+ BNXT_ULP_HF2_IDX_IO_VLAN_CFI_PRI = 31,
+ BNXT_ULP_HF2_IDX_IO_VLAN_VID = 32,
+ BNXT_ULP_HF2_IDX_IO_VLAN_TYPE = 33,
+ BNXT_ULP_HF2_IDX_II_VLAN_CFI_PRI = 34,
+ BNXT_ULP_HF2_IDX_II_VLAN_VID = 35,
+ BNXT_ULP_HF2_IDX_II_VLAN_TYPE = 36,
+ BNXT_ULP_HF2_IDX_I_IPV4_VER = 37,
+ BNXT_ULP_HF2_IDX_I_IPV4_TOS = 38,
+ BNXT_ULP_HF2_IDX_I_IPV4_LEN = 39,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_ID = 40,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_OFF = 41,
+ BNXT_ULP_HF2_IDX_I_IPV4_TTL = 42,
+ BNXT_ULP_HF2_IDX_I_IPV4_NEXT_PID = 43,
+ BNXT_ULP_HF2_IDX_I_IPV4_CSUM = 44,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR = 45,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR = 46,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT = 47,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT = 48,
+ BNXT_ULP_HF2_IDX_I_UDP_LENGTH = 49,
+ BNXT_ULP_HF2_IDX_I_UDP_CSUM = 50
+};
+
enum bnxt_ulp_hf_bitmask0 {
BNXT_ULP_HF0_BITMASK_SVIF_INDEX = 0x8000000000000000,
BNXT_ULP_HF0_BITMASK_O_ETH_DMAC = 0x4000000000000000,
@@ -59,5 +140,85 @@ enum bnxt_ulp_hf_bitmask0 {
BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000
};
+enum bnxt_ulp_hf_bitmask1 {
+ BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask2 {
+ BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_DMAC = 0x0000000800000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_SMAC = 0x0000000400000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_TYPE = 0x0000000200000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_VID = 0x0000000080000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_VID = 0x0000000010000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_VER = 0x0000000004000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TOS = 0x0000000002000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_LEN = 0x0000000001000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TTL = 0x0000000000200000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_NEXT_PID = 0x0000000000100000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_CSUM = 0x0000000000002000
+};
#endif
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 26/36] net/bnxt: flow db api to get vf rep action record
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (24 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 25/36] net/bnxt: add support for vxlan encap and decap templates Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 27/36] net/bnxt: parse ipv6 vtc_flow field for more granularly Somnath Kotur
` (9 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added flow db api to get the vf representor action
record for a given flow.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 200 +++++++++++++++++++++++++++++++---
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 25 +++++
2 files changed, 212 insertions(+), 13 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 30a809a..fc4c4da 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -53,7 +53,7 @@ ulp_flow_db_active_flow_set(struct bnxt_ulp_flow_tbl *flow_tbl,
/*
* Helper function to allocate the flow table and initialize
- * is set.No validation being done in this function.
+ * is set.No validation being done in this function.
*
* flow_tbl [in] Ptr to flow table
* idx [in] The index to bit to be set or reset.
@@ -71,6 +71,19 @@ ulp_flow_db_active_flow_is_set(struct bnxt_ulp_flow_tbl *flow_tbl,
idx);
}
+static uint8_t
+ulp_flow_db_resource_func_get(struct ulp_fdb_resource_info *res_info)
+{
+ uint8_t func;
+
+ func = (((res_info->nxt_resource_idx & ULP_FLOW_DB_RES_FUNC_MASK) >>
+ ULP_FLOW_DB_RES_FUNC_BITS) << ULP_FLOW_DB_RES_FUNC_UPPER);
+ /* The reource func is split into upper and lower */
+ if (func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
+ return (func | res_info->resource_func_lower);
+ return func;
+}
+
/*
* Helper function to copy the resource params to resource info
* No validation being done in this function.
@@ -124,23 +137,13 @@ static void
ulp_flow_db_res_info_to_params(struct ulp_fdb_resource_info *resource_info,
struct ulp_flow_db_res_params *params)
{
- uint8_t resource_func_upper;
-
memset(params, 0, sizeof(struct ulp_flow_db_res_params));
params->direction = ((resource_info->nxt_resource_idx &
ULP_FLOW_DB_RES_DIR_MASK) >>
ULP_FLOW_DB_RES_DIR_BIT);
- resource_func_upper = (((resource_info->nxt_resource_idx &
- ULP_FLOW_DB_RES_FUNC_MASK) >>
- ULP_FLOW_DB_RES_FUNC_BITS) <<
- ULP_FLOW_DB_RES_FUNC_UPPER);
- /* The reource func is split into upper and lower */
- if (resource_func_upper & ULP_FLOW_DB_RES_FUNC_NEED_LOWER)
- params->resource_func = (resource_func_upper |
- resource_info->resource_func_lower);
- else
- params->resource_func = resource_func_upper;
+ /* use the helper function to get the resource func */
+ params->resource_func = ulp_flow_db_resource_func_get(resource_info);
if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE) {
params->resource_hndl = resource_info->resource_em_handle;
@@ -852,3 +855,174 @@ ulp_flow_db_validate_flow_func(struct bnxt_ulp_context *ulp_ctx,
return false;
}
+
+/*
+ * Internal api to traverse the resource list within a flow
+ * and match a resource based on resource func and resource
+ * sub type. This api should be used only for resources that
+ * are unique and do not have multiple instances of resource
+ * func and sub type combination since it will return only
+ * the first match.
+ */
+static int32_t
+ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
+ enum bnxt_ulp_flow_db_tables tbl_idx,
+ uint32_t flow_id,
+ uint32_t resource_func,
+ uint32_t res_subtype,
+ uint64_t *res_hndl)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ struct ulp_fdb_resource_info *fid_res;
+ uint32_t res_id;
+
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctx);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Flow database not found\n");
+ return -EINVAL;
+ }
+
+ flow_tbl = &flow_db->flow_tbl[tbl_idx];
+
+ /* check for limits of fid */
+ if (flow_id >= flow_tbl->num_flows || !flow_id) {
+ BNXT_TF_DBG(ERR, "Invalid flow index\n");
+ return -EINVAL;
+ }
+
+ /* check if the flow is active or not */
+ if (!ulp_flow_db_active_flow_is_set(flow_tbl, flow_id)) {
+ BNXT_TF_DBG(ERR, "flow does not exist\n");
+ return -EINVAL;
+ }
+ /* Iterate the resource to get the resource handle */
+ res_id = flow_id;
+ while (res_id) {
+ fid_res = &flow_tbl->flow_resources[res_id];
+ if (ulp_flow_db_resource_func_get(fid_res) == resource_func) {
+ if (resource_func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) {
+ if (res_subtype == fid_res->resource_sub_type) {
+ *res_hndl = fid_res->resource_hndl;
+ return 0;
+ }
+
+ } else if (resource_func ==
+ BNXT_ULP_RESOURCE_FUNC_EM_TABLE){
+ *res_hndl = fid_res->resource_em_handle;
+ return 0;
+ }
+ }
+ res_id = 0;
+ ULP_FLOW_DB_RES_NXT_SET(res_id, fid_res->nxt_resource_idx);
+ }
+ return -ENOENT;
+}
+
+/*
+ * Api to get the cfa action pointer from a flow.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * flow_id [in] flow id
+ * cfa_action [out] The resource handle stored in the flow database
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t flow_id,
+ uint32_t *cfa_action)
+{
+ uint8_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX;
+ uint64_t hndl;
+ int32_t rc;
+
+ rc = ulp_flow_db_resource_hndl_get(ulp_ctx,
+ BNXT_ULP_DEFAULT_FLOW_TABLE,
+ flow_id,
+ BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ sub_type, &hndl);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "CFA Action ptr not found for flow id %u\n",
+ flow_id);
+ return -ENOENT;
+ }
+ *cfa_action = hndl;
+ return 0;
+}
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+static void ulp_flow_db_res_dump(struct ulp_fdb_resource_info *r,
+ uint32_t *nxt_res)
+{
+ uint8_t res_func = ulp_flow_db_resource_func_get(r);
+
+ BNXT_TF_DBG(DEBUG, "Resource func = %x, nxt_resource_idx = %x\n",
+ res_func, (ULP_FLOW_DB_RES_NXT_MASK & r->nxt_resource_idx));
+ if (res_func == BNXT_ULP_RESOURCE_FUNC_EM_TABLE)
+ BNXT_TF_DBG(DEBUG, "EM Handle = 0x%016" PRIX64 "\n",
+ r->resource_em_handle);
+ else
+ BNXT_TF_DBG(DEBUG, "Handle = 0x%08x\n", r->resource_hndl);
+
+ *nxt_res = 0;
+ ULP_FLOW_DB_RES_NXT_SET(*nxt_res,
+ r->nxt_resource_idx);
+}
+
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt)
+{
+ struct bnxt_ulp_flow_db *flow_db;
+ struct bnxt_ulp_flow_tbl *flow_tbl;
+ struct ulp_fdb_resource_info *r;
+ uint32_t nxt_res = 0;
+ enum bnxt_ulp_flow_db_tables tbl_idx;
+ uint32_t fid;
+
+ if (!ulp_ctxt || !ulp_ctxt->cfg_data) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+ flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+ if (!flow_db) {
+ BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+ return -EINVAL;
+ }
+
+ for (tbl_idx = 0; tbl_idx < BNXT_ULP_FLOW_TABLE_MAX; tbl_idx++) {
+ flow_tbl = &flow_db->flow_tbl[tbl_idx];
+ BNXT_TF_DBG(DEBUG, "Dump Tbl index = %u, flows = %u:%u\n",
+ tbl_idx, flow_tbl->num_flows,
+ flow_tbl->num_resources);
+ BNXT_TF_DBG(DEBUG, "Head_index = %u, Tail_index = %u\n",
+ flow_tbl->head_index, flow_tbl->tail_index);
+ for (fid = 0; fid < flow_tbl->num_flows; fid++) {
+ if (ulp_flow_db_active_flow_is_set(flow_tbl, fid)) {
+ BNXT_TF_DBG(DEBUG, "fid = %u\n", fid);
+ /* iterate the resource */
+ nxt_res = fid;
+ do {
+ r = &flow_tbl->flow_resources[nxt_res];
+ ulp_flow_db_res_dump(r, &nxt_res);
+ } while (nxt_res);
+ }
+ }
+ BNXT_TF_DBG(DEBUG, "Done.\n");
+ }
+ return 0;
+}
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 9037dc5..357a589 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -222,4 +222,29 @@ ulp_flow_db_validate_flow_func(struct bnxt_ulp_context *ulp_ctx,
uint32_t flow_id,
uint32_t func_id);
+/*
+ * Api to get the cfa action pointer from a flow.
+ *
+ * ulp_ctxt [in] Ptr to ulp context
+ * flow_id [in] flow id
+ * cfa_action [out] The resource handle stored in the flow database
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
+ uint32_t flow_id,
+ uint32_t *cfa_action);
+
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+/*
+ * Dump the flow database entry details
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+int32_t ulp_flow_db_debug_dump(struct bnxt_ulp_context *ulp_ctxt);
+#endif
+
#endif /* _ULP_FLOW_DB_H_ */
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 27/36] net/bnxt: parse ipv6 vtc_flow field for more granularly
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (25 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 26/36] net/bnxt: flow db api to get vf rep action record Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 28/36] net/bnxt: remove the implicit bitset update for vnic action Somnath Kotur
` (8 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
ipv6 vtc_flow contains three fields
1. Version
2. Priority / Traffic Class
3. Flow Label
Currently, these are not parsed separately and also not set separately
in the field bitmap by the flow parser. However, the template treats
them separately. As a result, the flow matching doesn't succeed because
the bitmaps of parser and the template doesn't match.
This patch fixes this problem by parsing the above mentioned fields
individually to align with the template.
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 37 ++++++++++++++++++++++++---
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 10 ++++++++
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +-
3 files changed, 44 insertions(+), 5 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 3dd941f..ec576a9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -598,6 +598,7 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
uint32_t idx = params->field_idx;
uint32_t size;
uint32_t inner_l3, outer_l3;
+ uint32_t vtcf, vtcf_mask;
inner_l3 = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_I_L3);
if (inner_l3) {
@@ -606,14 +607,27 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
}
/*
- * Copy the rte_flow_item for ipv4 into hdr_field using ipv4
+ * Copy the rte_flow_item for ipv6 into hdr_field using ipv6
* header fields
*/
if (ipv6_spec) {
size = sizeof(ipv6_spec->hdr.vtc_flow);
+
+ vtcf = BNXT_ULP_GET_IPV6_VER(ipv6_spec->hdr.vtc_flow);
field = ulp_rte_parser_fld_copy(¶ms->hdr_field[idx],
- &ipv6_spec->hdr.vtc_flow,
+ &vtcf,
+ size);
+
+ vtcf = BNXT_ULP_GET_IPV6_TC(ipv6_spec->hdr.vtc_flow);
+ field = ulp_rte_parser_fld_copy(field,
+ &vtcf,
+ size);
+
+ vtcf = BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_spec->hdr.vtc_flow);
+ field = ulp_rte_parser_fld_copy(field,
+ &vtcf,
size);
+
size = sizeof(ipv6_spec->hdr.payload_len);
field = ulp_rte_parser_fld_copy(field,
&ipv6_spec->hdr.payload_len,
@@ -636,9 +650,24 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
size);
}
if (ipv6_mask) {
+ size = sizeof(ipv6_mask->hdr.vtc_flow);
+
+ vtcf_mask = BNXT_ULP_GET_IPV6_VER(ipv6_mask->hdr.vtc_flow);
+ ulp_rte_prsr_mask_copy(params, &idx,
+ &vtcf_mask,
+ size);
+
+ vtcf_mask = BNXT_ULP_GET_IPV6_TC(ipv6_mask->hdr.vtc_flow);
ulp_rte_prsr_mask_copy(params, &idx,
- &ipv6_mask->hdr.vtc_flow,
- sizeof(ipv6_mask->hdr.vtc_flow));
+ &vtcf_mask,
+ size);
+
+ vtcf_mask =
+ BNXT_ULP_GET_IPV6_FLOWLABEL(ipv6_mask->hdr.vtc_flow);
+ ulp_rte_prsr_mask_copy(params, &idx,
+ &vtcf_mask,
+ size);
+
ulp_rte_prsr_mask_copy(params, &idx,
&ipv6_mask->hdr.payload_len,
sizeof(ipv6_mask->hdr.payload_len));
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 868e6dc..c90bff4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -21,6 +21,16 @@
#define BNXT_ULP_ENCAP_UDP_SIZE 4
#define BNXT_ULP_INVALID_SVIF_VAL -1U
+#define BNXT_ULP_GET_IPV6_VER(vtcf) \
+ (((vtcf) & BNXT_ULP_PARSER_IPV6_VER_MASK) >> 28)
+#define BNXT_ULP_GET_IPV6_TC(vtcf) \
+ (((vtcf) & BNXT_ULP_PARSER_IPV6_TC) >> 20)
+#define BNXT_ULP_GET_IPV6_FLOWLABEL(vtcf) \
+ ((vtcf) & BNXT_ULP_PARSER_IPV6_FLOW_LABEL)
+#define BNXT_ULP_PARSER_IPV6_VER_MASK 0xf0000000
+#define BNXT_ULP_PARSER_IPV6_TC 0x0ff00000
+#define BNXT_ULP_PARSER_IPV6_FLOW_LABEL 0x000fffff
+
/* Function to handle the parsing of the RTE port id. */
int32_t
ulp_rte_parser_svif_process(struct ulp_rte_parser_params *params);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 9b1bdbb..36bf5a4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -23,7 +23,7 @@
#define BNXT_ULP_PROTO_HDR_S_VLAN_NUM 3
#define BNXT_ULP_PROTO_HDR_VLAN_NUM 6
#define BNXT_ULP_PROTO_HDR_IPV4_NUM 10
-#define BNXT_ULP_PROTO_HDR_IPV6_NUM 6
+#define BNXT_ULP_PROTO_HDR_IPV6_NUM 8
#define BNXT_ULP_PROTO_HDR_UDP_NUM 4
#define BNXT_ULP_PROTO_HDR_TCP_NUM 9
#define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 28/36] net/bnxt: remove the implicit bitset update for vnic action
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (26 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 27/36] net/bnxt: parse ipv6 vtc_flow field for more granularly Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules Somnath Kotur
` (7 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The implicit update of the egress vnic action bitset for a flow
that does not specify the forwarding port explicitly is removed.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index ec576a9..db040e3 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -230,6 +230,9 @@ ulp_rte_parser_vnic_process(struct ulp_rte_parser_params *params)
/* Update the vnic details */
ulp_rte_pf_act_handler(NULL, params);
+ /* Reset the hdr_bitmap with vnic bit */
+ ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_VNIC);
+
return BNXT_TF_RC_SUCCESS;
}
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (27 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 28/36] net/bnxt: remove the implicit bitset update for vnic action Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 30/36] net/bnxt: unify the mapper opcodes into single enum Somnath Kotur
` (6 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The ulp template db file is broken into three parts namely the
table, class and action files.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/meson.build | 4 +-
drivers/net/bnxt/tf_ulp/Makefile | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 696 +++++
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 3428 +++++++++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 587 ++++
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h | 225 ++
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 543 ++++
drivers/net/bnxt/tf_ulp/ulp_utils.h | 2 +-
16 files changed, 5494 insertions(+), 11 deletions(-)
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index 59dda69..4306c60 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -35,7 +35,9 @@ sources = files('bnxt_cpr.c',
'tf_ulp/bnxt_ulp.c',
'tf_ulp/ulp_mark_mgr.c',
'tf_ulp/ulp_flow_db.c',
- 'tf_ulp/ulp_template_db.c',
+ 'tf_ulp/ulp_template_db_tbl.c',
+ 'tf_ulp/ulp_template_db_class.c',
+ 'tf_ulp/ulp_template_db_act.c',
'tf_ulp/ulp_utils.c',
'tf_ulp/ulp_mapper.c',
'tf_ulp/ulp_matcher.c',
diff --git a/drivers/net/bnxt/tf_ulp/Makefile b/drivers/net/bnxt/tf_ulp/Makefile
index d5c22b3..57341f8 100644
--- a/drivers/net/bnxt/tf_ulp/Makefile
+++ b/drivers/net/bnxt/tf_ulp/Makefile
@@ -4,7 +4,9 @@
# Copyright(c) Broadcom Limited.
# All rights reserved.
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_tbl.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_class.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_act.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_rte_parser.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp_flow.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_matcher.c
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 00e21fa..10183ac 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -15,7 +15,7 @@
#include "tf_core.h"
#include "tf_ext_flow_handle.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "ulp_mark_mgr.h"
#include "ulp_flow_db.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 357a589..1fc0601 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -7,7 +7,7 @@
#define _ULP_FLOW_DB_H_
#include "bnxt_ulp.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS 128
#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES 5
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 300dca3..3872921 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -6,7 +6,7 @@
#include <rte_log.h>
#include <rte_malloc.h>
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_utils.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 67410c9..1df23db 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -10,7 +10,7 @@
#include <rte_flow.h>
#include <rte_flow_driver.h>
#include "tf_core.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "ulp_utils.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 0e13a46..0c47768 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -11,7 +11,7 @@
#include "tf_ext_flow_handle.h"
#include "ulp_mark_mgr.h"
#include "bnxt_tf_common.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#define ULP_MARK_DB_ENTRY_SET_VALID(mark_info) ((mark_info)->flags |=\
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
index fc19783..a582188 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
@@ -8,7 +8,7 @@
#include <rte_log.h>
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index db040e3..41ac77c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -4,7 +4,7 @@
*/
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_rte_parser.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index c90bff4..8788431 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -9,7 +9,7 @@
#include <rte_log.h>
#include <rte_flow.h>
#include <rte_flow_driver.h>
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
/* defines to be used in the tunnel header parsing */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
new file mode 100644
index 0000000..bc471fe
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -0,0 +1,696 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
+ [BNXT_ULP_ACT_HID_00a1] = 1,
+ [BNXT_ULP_ACT_HID_0040] = 2,
+ [BNXT_ULP_ACT_HID_0029] = 3
+};
+
+struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
+ [1] = {
+ .act_hid = BNXT_ULP_ACT_HID_00a1,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 0
+ },
+ [2] = {
+ .act_hid = BNXT_ULP_ACT_HID_0040,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VPORT |
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 1
+ },
+ [3] = {
+ .act_hid = BNXT_ULP_ACT_HID_0029,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
+ [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 1
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 2
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 0,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_TX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 26,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 12,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 64,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
new file mode 100644
index 0000000..f33136f
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -0,0 +1,3428 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
+ [BNXT_ULP_CLASS_HID_0080] = 1,
+ [BNXT_ULP_CLASS_HID_0000] = 2,
+ [BNXT_ULP_CLASS_HID_0087] = 3
+};
+
+struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
+ [1] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0080,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 0,
+ .act_vnic = 0,
+ .wc_pri = 0
+ },
+ [2] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0000,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .field_sig = { .bits =
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 1,
+ .act_vnic = 0,
+ .wc_pri = 0
+ },
+ [3] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0087,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 2,
+ .act_vnic = 0,
+ .wc_pri = 0
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
+ [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 5
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 10
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 0,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 0,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 1,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 15,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 14,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 18,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 15,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 60,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 23,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 71,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 32,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 73,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 33,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 86,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 46,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 89,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 47,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 131,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 55,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 142,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 64,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 144,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 157,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 78,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 160,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 79,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 202,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 87,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ }
+};
+
+struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ }
+};
+
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
new file mode 100644
index 0000000..07a3c78
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -0,0 +1,587 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef ULP_TEMPLATE_DB_H_
+#define ULP_TEMPLATE_DB_H_
+
+#define BNXT_ULP_REGFILE_MAX_SZ 15
+#define BNXT_ULP_MAX_NUM_DEVICES 4
+#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
+#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
+#define BNXT_ULP_CLASS_HID_SHFTR 16
+#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_MASK 255
+#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
+#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
+#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
+#define BNXT_ULP_ACT_HID_SHFTR 0
+#define BNXT_ULP_ACT_HID_SHFTL 23
+#define BNXT_ULP_ACT_HID_MASK 255
+#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
+#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
+
+enum bnxt_ulp_action_bit {
+ BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
+ BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002,
+ BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004,
+ BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008,
+ BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010,
+ BNXT_ULP_ACTION_BIT_VNIC = 0x0000000000000020,
+ BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040,
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080,
+ BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100,
+ BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200,
+ BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400,
+ BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800,
+ BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000,
+ BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000,
+ BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000,
+ BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000,
+ BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000,
+ BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000,
+ BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000,
+ BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000200000,
+ BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000400000,
+ BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000800000,
+ BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000001000000,
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000002000000,
+ BNXT_ULP_ACTION_BIT_NVGRE_ENCAP = 0x0000000004000000,
+ BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000
+};
+
+enum bnxt_ulp_hdr_bit {
+ BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001,
+ BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002,
+ BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004,
+ BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008,
+ BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010,
+ BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020,
+ BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040,
+ BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080,
+ BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100,
+ BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200,
+ BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400,
+ BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000
+};
+
+enum bnxt_ulp_act_type {
+ BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
+ BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
+ BNXT_ULP_ACT_TYPE_END = 2,
+ BNXT_ULP_ACT_TYPE_LAST = 3
+};
+
+enum bnxt_ulp_byte_order {
+ BNXT_ULP_BYTE_ORDER_BE = 0,
+ BNXT_ULP_BYTE_ORDER_LE = 1,
+ BNXT_ULP_BYTE_ORDER_LAST = 2
+};
+
+enum bnxt_ulp_cf_idx {
+ BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2,
+ BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
+ BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
+ BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5,
+ BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6,
+ BNXT_ULP_CF_IDX_INCOMING_IF = 7,
+ BNXT_ULP_CF_IDX_DIRECTION = 8,
+ BNXT_ULP_CF_IDX_SVIF_FLAG = 9,
+ BNXT_ULP_CF_IDX_O_L3 = 10,
+ BNXT_ULP_CF_IDX_I_L3 = 11,
+ BNXT_ULP_CF_IDX_O_L4 = 12,
+ BNXT_ULP_CF_IDX_I_L4 = 13,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 14,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
+ BNXT_ULP_CF_IDX_LAST = 28
+};
+
+enum bnxt_ulp_critical_resource {
+ BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
+ BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
+ BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
+};
+
+enum bnxt_ulp_device_id {
+ BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
+ BNXT_ULP_DEVICE_ID_THOR = 1,
+ BNXT_ULP_DEVICE_ID_STINGRAY = 2,
+ BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
+ BNXT_ULP_DEVICE_ID_LAST = 4
+};
+
+enum bnxt_ulp_direction {
+ BNXT_ULP_DIRECTION_INGRESS = 0,
+ BNXT_ULP_DIRECTION_EGRESS = 1,
+ BNXT_ULP_DIRECTION_LAST = 2
+};
+
+enum bnxt_ulp_glb_regfile_index {
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
+ BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
+};
+
+enum bnxt_ulp_hdr_type {
+ BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
+ BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
+ BNXT_ULP_HDR_TYPE_END = 2,
+ BNXT_ULP_HDR_TYPE_LAST = 3
+};
+
+enum bnxt_ulp_mark_enable {
+ BNXT_ULP_MARK_ENABLE_NO = 0,
+ BNXT_ULP_MARK_ENABLE_YES = 1,
+ BNXT_ULP_MARK_ENABLE_LAST = 2
+};
+
+enum bnxt_ulp_mask_opc {
+ BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
+ BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
+ BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3,
+ BNXT_ULP_MASK_OPC_ADD_PAD = 4,
+ BNXT_ULP_MASK_OPC_LAST = 5
+};
+
+enum bnxt_ulp_match_type {
+ BNXT_ULP_MATCH_TYPE_EM = 0,
+ BNXT_ULP_MATCH_TYPE_WC = 1,
+ BNXT_ULP_MATCH_TYPE_LAST = 2
+};
+
+enum bnxt_ulp_priority {
+ BNXT_ULP_PRIORITY_LEVEL_0 = 0,
+ BNXT_ULP_PRIORITY_LEVEL_1 = 1,
+ BNXT_ULP_PRIORITY_LEVEL_2 = 2,
+ BNXT_ULP_PRIORITY_LEVEL_3 = 3,
+ BNXT_ULP_PRIORITY_LEVEL_4 = 4,
+ BNXT_ULP_PRIORITY_LEVEL_5 = 5,
+ BNXT_ULP_PRIORITY_LEVEL_6 = 6,
+ BNXT_ULP_PRIORITY_LEVEL_7 = 7,
+ BNXT_ULP_PRIORITY_NOT_USED = 8,
+ BNXT_ULP_PRIORITY_LAST = 9
+};
+
+enum bnxt_ulp_regfile_index {
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
+ BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
+ BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
+ BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
+ BNXT_ULP_REGFILE_INDEX_LAST = 15
+};
+
+enum bnxt_ulp_result_opc {
+ BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
+ BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
+ BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
+ BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
+ BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
+ BNXT_ULP_RESULT_OPC_LAST = 7
+};
+
+enum bnxt_ulp_search_before_alloc {
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
+};
+
+enum bnxt_ulp_spec_opc {
+ BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
+ BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
+ BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
+ BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4,
+ BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
+ BNXT_ULP_SPEC_OPC_LAST = 6
+};
+
+enum bnxt_ulp_vfr_flag {
+ BNXT_ULP_VFR_FLAG_NO = 0,
+ BNXT_ULP_VFR_FLAG_YES = 1,
+ BNXT_ULP_VFR_FLAG_LAST = 2
+};
+
+enum bnxt_ulp_fdb_resource_flags {
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
+};
+
+enum bnxt_ulp_fdb_type {
+ BNXT_ULP_FDB_TYPE_DEFAULT = 1,
+ BNXT_ULP_FDB_TYPE_REGULAR = 0
+};
+
+enum bnxt_ulp_flow_dir_bitmask {
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
+ BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
+};
+
+enum bnxt_ulp_match_type_bitmask {
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
+ BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
+};
+
+enum bnxt_ulp_resource_func {
+ BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
+ BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
+ BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
+ BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
+ BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
+ BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
+ BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
+ BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
+ BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
+ BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
+};
+
+enum bnxt_ulp_resource_sub_type {
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
+};
+
+enum bnxt_ulp_sym {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_AGG_ERROR_NO = 0,
+ BNXT_ULP_SYM_AGG_ERROR_YES = 1,
+ BNXT_ULP_SYM_BIG_ENDIAN = 0,
+ BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+ BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+ BNXT_ULP_SYM_ECV_VALID_NO = 0,
+ BNXT_ULP_SYM_ECV_VALID_YES = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
+ BNXT_ULP_SYM_HREC_NEXT_NO = 0,
+ BNXT_ULP_SYM_HREC_NEXT_YES = 1,
+ BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
+ BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
+ BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
+ BNXT_ULP_SYM_IP_PROTO_TCP = 6,
+ BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+ BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+ BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
+ BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
+ BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+ BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+ BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+ BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
+ BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
+ BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
+ BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
+ BNXT_ULP_SYM_NO = 0,
+ BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+ BNXT_ULP_SYM_POP_VLAN_NO = 0,
+ BNXT_ULP_SYM_POP_VLAN_YES = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
+ BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
+ BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
+ BNXT_ULP_SYM_RESERVED_IGNORE = 0,
+ BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_YES = 1
+};
+
+enum bnxt_ulp_act_prop_sz {
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
+ BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
+ BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
+ BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
+ BNXT_ULP_ACT_PROP_SZ_MARK = 4,
+ BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
+ BNXT_ULP_ACT_PROP_SZ_METER = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
+ BNXT_ULP_ACT_PROP_SZ_LAST = 4
+};
+
+enum bnxt_ulp_act_prop_idx {
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
+ BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
+ BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
+ BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
+ BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
+ BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
+ BNXT_ULP_ACT_PROP_IDX_MARK = 44,
+ BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
+ BNXT_ULP_ACT_PROP_IDX_METER = 52,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,
+ BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,
+ BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
+ BNXT_ULP_ACT_PROP_IDX_LAST = 268
+};
+
+enum bnxt_ulp_class_hid {
+ BNXT_ULP_CLASS_HID_0080 = 0x0080,
+ BNXT_ULP_CLASS_HID_0000 = 0x0000,
+ BNXT_ULP_CLASS_HID_0087 = 0x0087
+};
+
+enum bnxt_ulp_act_hid {
+ BNXT_ULP_ACT_HID_00a1 = 0x00a1,
+ BNXT_ULP_ACT_HID_0040 = 0x0040,
+ BNXT_ULP_ACT_HID_0029 = 0x0029
+};
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
new file mode 100644
index 0000000..84b9523
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef ULP_HDR_FIELD_ENUMS_H_
+#define ULP_HDR_FIELD_ENUMS_H_
+
+enum bnxt_ulp_hf0 {
+ BNXT_ULP_HF0_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF0_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF0_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF0_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF0_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF0_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF0_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF0_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF0_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF0_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF0_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF0_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF0_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF0_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF0_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF0_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf1 {
+ BNXT_ULP_HF1_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF1_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF1_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF1_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF1_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF1_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF1_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF1_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF1_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF1_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF1_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF1_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF1_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF1_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF1_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF1_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF1_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF1_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf2 {
+ BNXT_ULP_HF2_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF2_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF2_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF2_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF2_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF2_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF2_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF2_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF2_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF2_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF2_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF2_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF2_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF2_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF2_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF2_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF2_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF2_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF2_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF2_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF2_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF2_IDX_O_UDP_CSUM = 23,
+ BNXT_ULP_HF2_IDX_T_VXLAN_FLAGS = 24,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD0 = 25,
+ BNXT_ULP_HF2_IDX_T_VXLAN_VNI = 26,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD1 = 27,
+ BNXT_ULP_HF2_IDX_I_ETH_DMAC = 28,
+ BNXT_ULP_HF2_IDX_I_ETH_SMAC = 29,
+ BNXT_ULP_HF2_IDX_I_ETH_TYPE = 30,
+ BNXT_ULP_HF2_IDX_IO_VLAN_CFI_PRI = 31,
+ BNXT_ULP_HF2_IDX_IO_VLAN_VID = 32,
+ BNXT_ULP_HF2_IDX_IO_VLAN_TYPE = 33,
+ BNXT_ULP_HF2_IDX_II_VLAN_CFI_PRI = 34,
+ BNXT_ULP_HF2_IDX_II_VLAN_VID = 35,
+ BNXT_ULP_HF2_IDX_II_VLAN_TYPE = 36,
+ BNXT_ULP_HF2_IDX_I_IPV4_VER = 37,
+ BNXT_ULP_HF2_IDX_I_IPV4_TOS = 38,
+ BNXT_ULP_HF2_IDX_I_IPV4_LEN = 39,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_ID = 40,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_OFF = 41,
+ BNXT_ULP_HF2_IDX_I_IPV4_TTL = 42,
+ BNXT_ULP_HF2_IDX_I_IPV4_NEXT_PID = 43,
+ BNXT_ULP_HF2_IDX_I_IPV4_CSUM = 44,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR = 45,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR = 46,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT = 47,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT = 48,
+ BNXT_ULP_HF2_IDX_I_UDP_LENGTH = 49,
+ BNXT_ULP_HF2_IDX_I_UDP_CSUM = 50
+};
+
+enum bnxt_ulp_hf_bitmask0 {
+ BNXT_ULP_HF0_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask1 {
+ BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask2 {
+ BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_DMAC = 0x0000000800000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_SMAC = 0x0000000400000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_TYPE = 0x0000000200000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_VID = 0x0000000080000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_VID = 0x0000000010000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_VER = 0x0000000004000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TOS = 0x0000000002000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_LEN = 0x0000000001000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TTL = 0x0000000000200000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_NEXT_PID = 0x0000000000100000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_CSUM = 0x0000000000002000
+};
+
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
new file mode 100644
index 0000000..b49b0a1
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -0,0 +1,543 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint32_t ulp_act_prop_map_table[] = {
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE,
+ [BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_PORT_ID] =
+ BNXT_ULP_ACT_PROP_SZ_PORT_ID,
+ [BNXT_ULP_ACT_PROP_IDX_VNIC] =
+ BNXT_ULP_ACT_PROP_SZ_VNIC,
+ [BNXT_ULP_ACT_PROP_IDX_VPORT] =
+ BNXT_ULP_ACT_PROP_SZ_VPORT,
+ [BNXT_ULP_ACT_PROP_IDX_MARK] =
+ BNXT_ULP_ACT_PROP_SZ_MARK,
+ [BNXT_ULP_ACT_PROP_IDX_COUNT] =
+ BNXT_ULP_ACT_PROP_SZ_COUNT,
+ [BNXT_ULP_ACT_PROP_IDX_METER] =
+ BNXT_ULP_ACT_PROP_SZ_METER,
+ [BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN,
+ [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP] =
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP,
+ [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID] =
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST,
+ [BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_DST,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN,
+ [BNXT_ULP_ACT_PROP_IDX_LAST] =
+ BNXT_ULP_ACT_PROP_SZ_LAST
+};
+
+struct bnxt_ulp_rte_act_info ulp_act_info[] = {
+ [RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_END,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_VOID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_void_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PASSTHRU] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_JUMP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_MARK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_mark_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_FLAG] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_QUEUE] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DROP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_drop_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_COUNT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_count_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_RSS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_rss_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PF] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_pf_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_VF] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vf_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PHY_PORT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_phy_port_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PORT_ID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_port_id_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_METER] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SECURITY] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vxlan_encap_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vxlan_decap_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_RAW_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TP_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_MAC_SWAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
+};
+
+struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_RX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_TX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_RX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_TX] = {
+ .num_entries = 16384
+ }
+};
+
+struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
+ [BNXT_ULP_DEVICE_ID_WH_PLUS] = {
+ .global_fid_enable = BNXT_ULP_SYM_YES,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_swap = 1,
+ .lfid_entries = 16384,
+ .lfid_entry_size = 4,
+ .gfid_entries = 65536,
+ .gfid_entry_size = 4,
+ .num_flows = 32768,
+ .num_resources_per_flow = 8
+ }
+};
+
+struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ [0] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ [1] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ }
+};
+
+struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
+ [RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_END,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VOID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_void_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_INVERT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ANY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PF] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_pf_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_VF] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vf_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_phy_port_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_PORT_ID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_port_id_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_RAW] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_eth_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_VLAN] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vlan_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV4] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ipv4_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV6] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ipv6_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_UDP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_udp_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_TCP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_tcp_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_SCTP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VXLAN] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vxlan_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_E_TAG] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_NVGRE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_MPLS] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GRE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_FUZZY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTPC] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTPU] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ESP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GENEVE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV6_EXT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_MARK] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_META] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GRE_KEY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTP_PSC] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOES] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOED] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_NSH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_IGMP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_AH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_HIGIG2] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ }
+};
+
+uint32_t bnxt_ulp_encap_vtag_map[] = {
+ [0] = BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP,
+ [1] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
+ [2] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI
+};
+
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 2f64bcb..13d9e88 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -7,7 +7,7 @@
#define _ULP_UTILS_H_
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
/*
* Macros for bitmap sets and gets
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 30/36] net/bnxt: unify the mapper opcodes into single enum
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (28 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 31/36] net/bnxt: change opcode for adding pad to setting zero for common usage Somnath Kotur
` (5 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Mike Baucom <michael.baucom@broadcom.com>
Unify the opcodes of the different enums into a single enum for reuse of
common processors.
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 26 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 180 ++--
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 1044 +++++++++++------------
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 39 +-
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 14 +-
5 files changed, 643 insertions(+), 660 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 3872921..8492486 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -615,14 +615,14 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
uint8_t act_val;
switch (fld->result_opcode) {
- case BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT:
val = fld->result_operand;
if (!ulp_blob_push(blob, val, fld->field_bit_size)) {
BNXT_TF_DBG(ERR, "%s failed to add field\n", name);
return -EINVAL;
}
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx, sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
@@ -646,7 +646,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&act_bit, sizeof(uint64_t))) {
BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
@@ -664,7 +664,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
}
val = &act_val;
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx, sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
@@ -696,7 +696,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
val_size = ULP_BYTE_2_BITS(val_size);
ulp_blob_push_encap(blob, val, val_size);
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_REGFILE:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx, sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s operand read failed\n", name);
@@ -717,7 +717,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx,
sizeof(uint16_t))) {
@@ -738,7 +738,7 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD:
if (!ulp_operand_read(fld->result_operand,
(uint8_t *)&idx,
sizeof(uint16_t))) {
@@ -789,21 +789,21 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
bitlen = fld->field_bit_size;
switch (opcode) {
- case BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT:
val = operand;
if (!ulp_blob_push(blob, val, bitlen)) {
BNXT_TF_DBG(ERR, "%s push to key blob failed\n", name);
return -EINVAL;
}
break;
- case BNXT_ULP_SPEC_OPC_ADD_PAD:
+ case BNXT_ULP_MAPPER_OPC_ADD_PAD:
if (!ulp_blob_pad_push(blob, bitlen)) {
BNXT_TF_DBG(ERR, "%s pad too large for blob\n", name);
return -EINVAL;
}
break;
- case BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD:
if (!ulp_operand_read(operand, (uint8_t *)&idx,
sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
@@ -830,7 +830,7 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD:
if (!ulp_operand_read(operand, (uint8_t *)&idx,
sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
@@ -845,7 +845,7 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_SPEC_OPC_SET_TO_REGFILE:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE:
if (!ulp_operand_read(operand, (uint8_t *)&idx,
sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
@@ -865,7 +865,7 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE:
if (!ulp_operand_read(operand, (uint8_t *)&idx,
sizeof(uint16_t))) {
BNXT_TF_DBG(ERR, "%s key operand read failed.\n", name);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index bc471fe..d24851d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -109,127 +109,127 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
{
.field_bit_size = 14,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -237,7 +237,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 12,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
@@ -246,151 +246,151 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 14,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_DECAP_FUNC_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -398,7 +398,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 12,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff,
@@ -407,31 +407,31 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -439,7 +439,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -447,7 +447,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff,
@@ -456,13 +456,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff,
@@ -471,19 +471,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff,
@@ -492,7 +492,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 0,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
@@ -503,7 +503,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 0,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
@@ -514,7 +514,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 32,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff,
@@ -523,7 +523,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 0,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
@@ -534,127 +534,127 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 14,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
BNXT_ULP_SYM_DECAP_FUNC_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -662,7 +662,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 12,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
@@ -671,25 +671,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index f33136f..fbb40eb 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -444,10 +444,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
@@ -456,10 +456,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -467,40 +467,40 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.mask_operand = {
(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
@@ -509,64 +509,64 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -574,37 +574,37 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -613,10 +613,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
@@ -625,10 +625,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -636,10 +636,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -647,10 +647,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -658,10 +658,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -669,10 +669,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -680,10 +680,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -691,10 +691,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -702,10 +702,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -713,10 +713,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -724,10 +724,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -735,10 +735,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -746,10 +746,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -757,10 +757,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -768,10 +768,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -779,10 +779,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -790,10 +790,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -801,10 +801,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -812,10 +812,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -823,10 +823,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -834,10 +834,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -845,10 +845,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -856,10 +856,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -867,10 +867,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -878,10 +878,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -889,10 +889,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -900,10 +900,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -911,10 +911,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -922,10 +922,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -933,10 +933,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -944,10 +944,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -955,10 +955,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -966,10 +966,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -977,10 +977,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -988,10 +988,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -999,10 +999,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1010,10 +1010,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_HREC_NEXT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1021,10 +1021,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
(BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
@@ -1033,10 +1033,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -1045,10 +1045,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_AGG_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1056,10 +1056,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1067,10 +1067,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_PKT_TYPE_L2,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1078,37 +1078,37 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_ADD_PAD,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,
@@ -1117,10 +1117,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,
@@ -1129,10 +1129,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_IP_PROTO_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1140,10 +1140,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,
@@ -1152,10 +1152,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,
@@ -1164,28 +1164,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -1194,10 +1194,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -1206,10 +1206,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
@@ -1218,10 +1218,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1229,40 +1229,40 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.mask_operand = {
(BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
@@ -1271,64 +1271,64 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1336,37 +1336,37 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -1375,10 +1375,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
@@ -1387,10 +1387,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1398,10 +1398,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1409,10 +1409,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1420,10 +1420,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1431,10 +1431,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1442,10 +1442,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1453,10 +1453,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1464,10 +1464,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1475,10 +1475,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1486,10 +1486,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1497,10 +1497,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1508,10 +1508,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1519,10 +1519,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1530,10 +1530,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1541,10 +1541,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1552,10 +1552,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1563,10 +1563,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1574,10 +1574,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1585,10 +1585,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1596,10 +1596,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1607,10 +1607,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1618,10 +1618,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1629,10 +1629,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1640,10 +1640,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1651,10 +1651,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1662,10 +1662,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1673,10 +1673,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1684,10 +1684,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1695,10 +1695,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1706,10 +1706,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1717,10 +1717,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1728,10 +1728,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1739,10 +1739,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1750,10 +1750,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1761,10 +1761,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1772,10 +1772,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_HREC_NEXT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1783,10 +1783,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
(BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
@@ -1795,10 +1795,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -1807,10 +1807,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_AGG_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1818,10 +1818,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1829,10 +1829,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_PKT_TYPE_L2,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1840,37 +1840,37 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_ADD_PAD,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff,
BNXT_ULP_HF1_IDX_O_UDP_DST_PORT & 0xff,
@@ -1879,10 +1879,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT & 0xff,
@@ -1891,10 +1891,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_IP_PROTO_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1902,10 +1902,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR & 0xff,
@@ -1914,10 +1914,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR & 0xff,
@@ -1926,28 +1926,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -1956,10 +1956,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -1968,10 +1968,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
@@ -1980,10 +1980,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -1991,40 +1991,40 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.mask_operand = {
(BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
@@ -2033,64 +2033,64 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2098,37 +2098,37 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -2137,10 +2137,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
@@ -2149,10 +2149,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2160,10 +2160,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2171,10 +2171,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2182,10 +2182,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2193,10 +2193,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2204,10 +2204,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2215,10 +2215,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2226,10 +2226,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2237,10 +2237,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2248,10 +2248,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2259,10 +2259,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2270,10 +2270,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2281,10 +2281,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2292,10 +2292,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2303,10 +2303,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2314,10 +2314,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2325,10 +2325,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2336,10 +2336,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2347,10 +2347,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2358,10 +2358,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2369,10 +2369,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2380,10 +2380,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2391,10 +2391,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2402,10 +2402,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2413,10 +2413,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2424,10 +2424,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2435,10 +2435,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2446,10 +2446,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2457,10 +2457,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ERROR_NO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2468,10 +2468,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2479,10 +2479,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2490,10 +2490,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2501,10 +2501,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2512,10 +2512,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2523,10 +2523,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_VALID_YES,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2534,10 +2534,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_HREC_NEXT_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2545,10 +2545,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
(BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
@@ -2557,10 +2557,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -2569,10 +2569,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_AGG_ERROR_IGNORE,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2580,10 +2580,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2591,10 +2591,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_PKT_TYPE_L2,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2602,37 +2602,37 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_ADD_PAD,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff,
BNXT_ULP_HF2_IDX_I_UDP_DST_PORT & 0xff,
@@ -2641,10 +2641,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT & 0xff,
@@ -2653,10 +2653,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_IP_PROTO_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2664,10 +2664,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR & 0xff,
@@ -2676,10 +2676,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR & 0xff,
@@ -2688,28 +2688,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -2718,10 +2718,10 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -2733,7 +2733,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -2742,7 +2742,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -2751,7 +2751,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 7,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.result_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -2760,73 +2760,73 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 6,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -2835,25 +2835,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
(0x00f9 >> 8) & 0xff,
0x00f9 & 0xff,
@@ -2862,13 +2862,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 5,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -2877,19 +2877,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 33,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
@@ -2898,25 +2898,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 5,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 9,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
(0x00c5 >> 8) & 0xff,
0x00c5 & 0xff,
@@ -2925,31 +2925,31 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -2958,7 +2958,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -2967,7 +2967,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 7,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.result_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -2976,73 +2976,73 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 6,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -3051,25 +3051,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
(0x00f9 >> 8) & 0xff,
0x00f9 & 0xff,
@@ -3078,13 +3078,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 5,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -3093,19 +3093,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 33,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
@@ -3114,25 +3114,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 5,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 9,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
(0x00c5 >> 8) & 0xff,
0x00c5 & 0xff,
@@ -3141,31 +3141,31 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -3174,7 +3174,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
@@ -3183,7 +3183,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 7,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.result_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
@@ -3192,73 +3192,73 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 6,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -3267,25 +3267,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
(0x00f9 >> 8) & 0xff,
0x00f9 & 0xff,
@@ -3294,13 +3294,13 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 5,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
@@ -3309,19 +3309,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 33,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.result_operand = {
(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
@@ -3330,25 +3330,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 5,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 9,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
(0x00c5 >> 8) & 0xff,
0x00c5 & 0xff,
@@ -3357,25 +3357,25 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 07a3c78..6c3e00c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -157,13 +157,17 @@ enum bnxt_ulp_mark_enable {
BNXT_ULP_MARK_ENABLE_LAST = 2
};
-enum bnxt_ulp_mask_opc {
- BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
- BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
- BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
- BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3,
- BNXT_ULP_MASK_OPC_ADD_PAD = 4,
- BNXT_ULP_MASK_OPC_LAST = 5
+enum bnxt_ulp_mapper_opc {
+ BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD = 1,
+ BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD = 2,
+ BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE = 3,
+ BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE = 4,
+ BNXT_ULP_MAPPER_OPC_ADD_PAD = 5,
+ BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT = 6,
+ BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP = 7,
+ BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8,
+ BNXT_ULP_MAPPER_OPC_LAST = 9
};
enum bnxt_ulp_match_type {
@@ -204,33 +208,12 @@ enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_LAST = 15
};
-enum bnxt_ulp_result_opc {
- BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
- BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
- BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
- BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
- BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
- BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
- BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
- BNXT_ULP_RESULT_OPC_LAST = 7
-};
-
enum bnxt_ulp_search_before_alloc {
BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
};
-enum bnxt_ulp_spec_opc {
- BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
- BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
- BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
- BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
- BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4,
- BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
- BNXT_ULP_SPEC_OPC_LAST = 6
-};
-
enum bnxt_ulp_vfr_flag {
BNXT_ULP_VFR_FLAG_NO = 0,
BNXT_ULP_VFR_FLAG_YES = 1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 36bf5a4..8de6c4c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -187,17 +187,17 @@ struct bnxt_ulp_mapper_tbl_info {
};
struct bnxt_ulp_mapper_class_key_field_info {
- uint8_t description[64];
- enum bnxt_ulp_mask_opc mask_opcode;
- enum bnxt_ulp_spec_opc spec_opcode;
- uint16_t field_bit_size;
- uint8_t mask_operand[16];
- uint8_t spec_operand[16];
+ uint8_t description[64];
+ enum bnxt_ulp_mapper_opc mask_opcode;
+ enum bnxt_ulp_mapper_opc spec_opcode;
+ uint16_t field_bit_size;
+ uint8_t mask_operand[16];
+ uint8_t spec_operand[16];
};
struct bnxt_ulp_mapper_result_field_info {
uint8_t description[64];
- enum bnxt_ulp_result_opc result_opcode;
+ enum bnxt_ulp_mapper_opc result_opcode;
uint16_t field_bit_size;
uint8_t result_operand[16];
};
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 31/36] net/bnxt: change opcode for adding pad to setting zero for common usage
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (29 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 30/36] net/bnxt: unify the mapper opcodes into single enum Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 32/36] net/bnxt: optimized key/mask/result fields to use set to zero opcode Somnath Kotur
` (4 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Mike Baucom <michael.baucom@broadcom.com>
The ADD_PAD opcode is now SET_TO_ZERO. This change better reflects the
intent of the opcode and allows it to be used in more circumstances
without overloading the term pad.
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 6 +++---
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 8492486..f35a99e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -796,7 +796,7 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
- case BNXT_ULP_MAPPER_OPC_ADD_PAD:
+ case BNXT_ULP_MAPPER_OPC_SET_TO_ZERO:
if (!ulp_blob_pad_push(blob, bitlen)) {
BNXT_TF_DBG(ERR, "%s pad too large for blob\n", name);
return -EINVAL;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index fbb40eb..bce4442 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -1090,7 +1090,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_ADD_PAD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -1852,7 +1852,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_ADD_PAD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -2614,7 +2614,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_ADD_PAD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 6c3e00c..7f280fd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -163,7 +163,7 @@ enum bnxt_ulp_mapper_opc {
BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD = 2,
BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE = 3,
BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE = 4,
- BNXT_ULP_MAPPER_OPC_ADD_PAD = 5,
+ BNXT_ULP_MAPPER_OPC_SET_TO_ZERO = 5,
BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT = 6,
BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP = 7,
BNXT_ULP_MAPPER_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 8,
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 32/36] net/bnxt: optimized key/mask/result fields to use set to zero opcode
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (30 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 31/36] net/bnxt: change opcode for adding pad to setting zero for common usage Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 33/36] net/bnxt: add support for internal exact match flows Somnath Kotur
` (3 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Mike Baucom <michael.baucom@broadcom.com>
The fields that were setting a constant zero have now been switched to
use the new SET_TO_ZERO opcode as an optimization. The SET_TO_ZERO does
not copy data into the key/result/mask fields, but rather simply
increments the write pointer.
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 292 ++-----
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 1000 ++++++-----------------
2 files changed, 323 insertions(+), 969 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index d24851d..d33d198 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -109,123 +109,83 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
{
.field_bit_size = 14,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -246,147 +206,99 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 14,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -407,27 +319,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
@@ -471,9 +375,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -534,123 +436,83 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 14,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 4,
@@ -671,26 +533,18 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index bce4442..cc81b31 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -444,9 +444,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
@@ -456,9 +454,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
@@ -467,30 +463,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
@@ -509,57 +493,33 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -574,12 +534,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -592,18 +548,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
@@ -613,9 +563,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
@@ -625,9 +573,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
@@ -669,9 +615,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
@@ -680,9 +624,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
@@ -691,9 +633,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
@@ -735,9 +675,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
@@ -746,9 +684,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
@@ -757,9 +693,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
@@ -801,9 +735,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
@@ -812,9 +744,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
@@ -823,9 +753,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
@@ -834,9 +762,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
@@ -845,9 +771,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
@@ -856,9 +780,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
@@ -867,9 +789,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
@@ -878,9 +798,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
@@ -889,9 +807,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
@@ -900,9 +816,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
@@ -911,9 +825,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
@@ -922,9 +834,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
@@ -933,9 +843,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
@@ -944,9 +852,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
@@ -955,9 +861,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
@@ -966,9 +870,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
@@ -977,9 +879,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
@@ -988,9 +888,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
@@ -999,9 +897,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
@@ -1010,9 +906,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_HREC_NEXT_IGNORE,
@@ -1021,9 +915,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
(BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
@@ -1045,9 +937,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_AGG_ERROR_IGNORE,
@@ -1087,27 +977,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
@@ -1117,9 +997,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
@@ -1129,9 +1007,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_IP_PROTO_UDP,
@@ -1140,9 +1016,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
@@ -1152,9 +1026,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
@@ -1164,27 +1036,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
@@ -1194,9 +1056,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
@@ -1206,9 +1066,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
@@ -1218,9 +1076,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
@@ -1229,30 +1085,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
@@ -1271,57 +1115,33 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -1336,12 +1156,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1354,18 +1170,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
@@ -1375,9 +1185,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
@@ -1387,9 +1195,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
@@ -1431,9 +1237,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
@@ -1442,9 +1246,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
@@ -1453,9 +1255,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
@@ -1497,9 +1297,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
@@ -1508,9 +1306,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
@@ -1519,9 +1315,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
@@ -1563,9 +1357,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
@@ -1574,9 +1366,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
@@ -1585,9 +1375,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
@@ -1596,9 +1384,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
@@ -1607,9 +1393,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
@@ -1618,9 +1402,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
@@ -1629,9 +1411,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
@@ -1640,9 +1420,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
@@ -1651,9 +1429,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
@@ -1662,9 +1438,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
@@ -1673,9 +1447,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
@@ -1684,9 +1456,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
@@ -1695,9 +1465,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
@@ -1706,9 +1474,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
@@ -1717,9 +1483,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
@@ -1728,9 +1492,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
@@ -1739,9 +1501,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
@@ -1750,9 +1510,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
@@ -1761,9 +1519,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
@@ -1772,9 +1528,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_HREC_NEXT_IGNORE,
@@ -1783,9 +1537,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
(BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
@@ -1807,9 +1559,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_AGG_ERROR_IGNORE,
@@ -1849,27 +1599,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff,
@@ -1879,9 +1619,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
@@ -1891,9 +1629,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_IP_PROTO_UDP,
@@ -1902,9 +1638,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
@@ -1914,9 +1648,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
@@ -1926,27 +1658,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
@@ -1956,9 +1678,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
@@ -1968,9 +1688,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
@@ -1980,9 +1698,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
@@ -1991,30 +1707,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
@@ -2033,57 +1737,33 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -2098,12 +1778,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -2116,18 +1792,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
@@ -2137,9 +1807,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
@@ -2149,9 +1817,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
@@ -2193,9 +1859,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
@@ -2204,9 +1868,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
@@ -2215,9 +1877,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
@@ -2259,9 +1919,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
@@ -2270,9 +1928,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
@@ -2281,9 +1937,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
@@ -2325,9 +1979,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
@@ -2369,9 +2021,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
@@ -2413,9 +2063,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
@@ -2424,9 +2072,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
@@ -2435,9 +2081,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
@@ -2479,9 +2123,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
@@ -2490,9 +2132,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
@@ -2501,9 +2141,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
@@ -2534,9 +2172,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_HREC_NEXT_IGNORE,
@@ -2545,9 +2181,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
(BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
@@ -2569,9 +2203,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_AGG_ERROR_IGNORE,
@@ -2611,27 +2243,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff,
@@ -2641,9 +2263,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
@@ -2653,9 +2273,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
BNXT_ULP_SYM_IP_PROTO_UDP,
@@ -2664,9 +2282,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
@@ -2676,9 +2292,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
@@ -2688,27 +2302,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
@@ -2718,9 +2322,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
.spec_operand = {
(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
@@ -2760,51 +2362,35 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 6,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -2814,15 +2400,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
@@ -2835,21 +2417,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
@@ -2883,9 +2459,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 33,
@@ -2904,9 +2478,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 5,
@@ -2925,9 +2497,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
@@ -2937,9 +2507,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -2976,51 +2544,35 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 6,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -3030,15 +2582,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
@@ -3051,21 +2599,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
@@ -3099,9 +2641,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 33,
@@ -3120,9 +2660,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 5,
@@ -3141,9 +2679,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
@@ -3153,9 +2689,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -3192,51 +2726,35 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 6,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -3246,15 +2764,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
@@ -3267,21 +2781,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
@@ -3315,9 +2823,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 33,
@@ -3336,9 +2842,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 5,
@@ -3357,9 +2861,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 11,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
@@ -3369,9 +2871,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 33/36] net/bnxt: add support for internal exact match flows
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (31 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 32/36] net/bnxt: optimized key/mask/result fields to use set to zero opcode Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 34/36] net/bnxt: enable vfr flag processing with mark db opcode Somnath Kotur
` (2 subsequent siblings)
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Added support of internal exact match flows and the action
mark is supported for these flows.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/bnxt.h | 2 ++
drivers/net/bnxt/bnxt_rxr.c | 36 +++++++++++++++++++++--------
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 44 ++++++++++++++++++++++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 9 +++++++-
drivers/net/bnxt/tf_ulp/ulp_utils.c | 35 +++++++++++++++++++++++++---
drivers/net/bnxt/tf_ulp/ulp_utils.h | 16 +++++++++++--
6 files changed, 126 insertions(+), 16 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 79e9b28..d455f8d 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -562,6 +562,7 @@ struct bnxt {
#define BNXT_FLAG_FLOW_XSTATS_EN BIT(25)
#define BNXT_FLAG_DFLT_MAC_SET BIT(26)
#define BNXT_FLAG_TRUFLOW_EN BIT(27)
+#define BNXT_FLAG_GFID_ENABLE BIT(28)
#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
#define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF)
@@ -577,6 +578,7 @@ struct bnxt {
#define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
#define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
#define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
+#define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
uint32_t fw_cap;
#define BNXT_FW_CAP_HOT_RESET BIT(0)
diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c
index bd452b7..3bcc624 100644
--- a/drivers/net/bnxt/bnxt_rxr.c
+++ b/drivers/net/bnxt/bnxt_rxr.c
@@ -412,8 +412,12 @@ bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
bool gfid = false;
uint32_t mark_id;
uint32_t flags2;
- int rc;
+ uint32_t gfid_support = 0;
uint32_t vfr_flag;
+ int rc;
+
+ if (BNXT_GFID_ENABLED(bp))
+ gfid_support = 1;
cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code);
flags2 = rte_le_to_cpu_32(rxcmp1->flags2);
@@ -428,8 +432,14 @@ bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
switch (meta_fmt) {
case 0:
- /* Not an LFID or GFID, a flush cmd. */
- goto skip_mark;
+ if (gfid_support) {
+ /* Not an LFID or GFID, a flush cmd. */
+ goto skip_mark;
+ } else {
+ /* LFID mode, no vlan scenario */
+ gfid = false;
+ }
+ break;
case 4:
case 5:
/*
@@ -438,13 +448,19 @@ bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1,
* collisions with EEM. Simply return without setting the mark
* in the mbuf.
*/
- if (BNXT_CFA_META_EM_TEST(meta))
- goto skip_mark;
- /*
- * It is a TCAM entry, so it is an LFID. The TCAM IDX and Mode
- * can also be determined by decoding the meta_data. We are not
- * using these for now.
- */
+ if (BNXT_CFA_META_EM_TEST(meta)) {
+ /*This is EM hit {EM(1), GFID[27:16], 19'd0 or vtag } */
+ gfid = true;
+ meta >>= BNXT_RX_META_CFA_CODE_SHIFT;
+ cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT;
+ } else {
+ /*
+ * It is a TCAM entry, so it is an LFID.
+ * The TCAM IDX and Mode can also be determined
+ * by decoding the meta_data. We are not
+ * using these for now.
+ */
+ }
break;
case 6:
case 7:
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 10183ac..fd3f61b 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -308,6 +308,32 @@ ulp_dparms_init(struct bnxt *bp,
return 0;
}
+/* The function to initialize bp flags with truflow features */
+static int32_t
+ulp_dparms_dev_port_intf_update(struct bnxt *bp,
+ struct bnxt_ulp_context *ulp_ctx)
+{
+ struct bnxt_ulp_device_params *dparms;
+ uint32_t dev_id;
+
+ if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) {
+ BNXT_TF_DBG(DEBUG, "Failed to get device id\n");
+ return -EINVAL;
+ }
+
+ dparms = bnxt_ulp_device_params_get(dev_id);
+ if (!dparms) {
+ BNXT_TF_DBG(DEBUG, "Failed to get device parms\n");
+ return -EINVAL;
+ }
+
+ /* Update the bp flag with gfid flag */
+ if (dparms->global_fid_enable)
+ bp->flags |= BNXT_FLAG_GFID_ENABLE;
+
+ return 0;
+}
+
static int32_t
ulp_ctx_attach(struct bnxt_ulp_context *ulp_ctx,
struct bnxt_ulp_session_state *session)
@@ -510,6 +536,17 @@ bnxt_ulp_init(struct bnxt *bp)
rte_free(bp->ulp_ctx);
return rc;
}
+
+ /* Update bnxt driver flags */
+ rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
+ ulp_ctx_detach(bp, session);
+ ulp_session_deinit(session);
+ rte_free(bp->ulp_ctx);
+ return rc;
+ }
+
/* update the port database */
rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp);
if (rc) {
@@ -539,6 +576,13 @@ bnxt_ulp_init(struct bnxt *bp)
goto jump_to_error;
}
+ /* Update bnxt driver flags */
+ rc = ulp_dparms_dev_port_intf_update(bp, bp->ulp_ctx);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to update driver flags\n");
+ goto jump_to_error;
+ }
+
/* update the port database */
rc = ulp_port_db_dev_port_intf_update(bp->ulp_ctx, bp);
if (rc) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index f35a99e..56c1f13 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -797,7 +797,7 @@ ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
}
break;
case BNXT_ULP_MAPPER_OPC_SET_TO_ZERO:
- if (!ulp_blob_pad_push(blob, bitlen)) {
+ if (ulp_blob_pad_push(blob, bitlen) < 0) {
BNXT_TF_DBG(ERR, "%s pad too large for blob\n", name);
return -EINVAL;
}
@@ -1289,6 +1289,13 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
}
+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
+ ulp_mapper_result_dump("EEM Result", tbl, &data);
+#endif
+
+ /* do the transpose for the internal EM keys */
+ if (tbl->resource_type == TF_MEM_INTERNAL)
+ ulp_blob_perform_byte_reverse(&key);
rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx,
&iparms.tbl_scope_id);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index bd267b6..c6e4dc7 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -403,15 +403,15 @@ ulp_blob_push_encap(struct ulp_blob *blob,
*
* datalen [in] The number of bits of pad to add
*
- * returns the number of pad bits added, zero on failure
+ * returns the number of pad bits added, -1 on failure
*/
-uint32_t
+int32_t
ulp_blob_pad_push(struct ulp_blob *blob,
uint32_t datalen)
{
if (datalen > (uint32_t)(blob->bitlen - blob->write_idx)) {
BNXT_TF_DBG(ERR, "Pad too large for blob\n");
- return 0;
+ return -1;
}
blob->write_idx += datalen;
@@ -495,6 +495,35 @@ ulp_blob_perform_encap_swap(struct ulp_blob *blob)
}
/*
+ * Perform the blob buffer reversal byte wise.
+ * This api makes the first byte the last and
+ * vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_byte_reverse(struct ulp_blob *blob)
+{
+ uint32_t idx = 0, num = 0;
+ uint8_t xchar;
+
+ /* validate the arguments */
+ if (!blob) {
+ BNXT_TF_DBG(ERR, "invalid argument\n");
+ return; /* failure */
+ }
+
+ num = ULP_BITS_2_BYTE_NR(blob->write_idx);
+ for (idx = 0; idx < (num / 2); idx++) {
+ xchar = blob->data[idx];
+ blob->data[idx] = blob->data[(num - 1) - idx];
+ blob->data[(num - 1) - idx] = xchar;
+ }
+}
+
+/*
* Read data from the operand
*
* operand [in] A pointer to a 16 Byte operand
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 13d9e88..97c7750 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -236,9 +236,9 @@ ulp_blob_data_get(struct ulp_blob *blob,
*
* datalen [in] The number of bits of pad to add
*
- * returns the number of pad bits added, zero on failure
+ * returns the number of pad bits added, -1 on failure
*/
-uint32_t
+int32_t
ulp_blob_pad_push(struct ulp_blob *blob,
uint32_t datalen);
@@ -264,6 +264,18 @@ void
ulp_blob_perform_encap_swap(struct ulp_blob *blob);
/*
+ * Perform the blob buffer reversal byte wise.
+ * This api makes the first byte the last and
+ * vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_byte_reverse(struct ulp_blob *blob);
+
+/*
* Read data from the operand
*
* operand [in] A pointer to a 16 Byte operand
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 34/36] net/bnxt: enable vfr flag processing with mark db opcode
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (32 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 33/36] net/bnxt: add support for internal exact match flows Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 35/36] net/bnxt: rename fields in the device params structure Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 36/36] net/bnxt: update ulp template database for new opcodes Somnath Kotur
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Removed the mark and vfr flags and replaced it with the new
opcode and added the vfr flag process in mark database
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 74 ++++++++++++++++++++++---
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 45 +++++----------
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 15 ++---
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 3 +-
4 files changed, 87 insertions(+), 50 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 56c1f13..f86cd76 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -899,11 +899,13 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
{
struct ulp_flow_db_res_params fid_parms;
uint32_t mark, gfid, mark_flag;
+ enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode;
int32_t rc = 0;
- if (!(tbl->mark_enable &&
- (ULP_BITMAP_ISSET(parms->act_bitmap->bits,
- BNXT_ULP_ACTION_BIT_MARK) || tbl->vfr_flag)))
+ if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP ||
+ !(mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION &&
+ ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ BNXT_ULP_ACTION_BIT_MARK)))
return rc; /* no need to perform gfid process */
/* Get the mark id details from action property */
@@ -913,7 +915,7 @@ ulp_mapper_mark_gfid_process(struct bnxt_ulp_mapper_parms *parms,
TF_GET_GFID_FROM_FLOW_ID(flow_id, gfid);
mark_flag = BNXT_ULP_MARK_GLOBAL_HW_FID;
- mark_flag |= (tbl->vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
+
rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
gfid, mark);
if (rc) {
@@ -941,11 +943,13 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
struct ulp_flow_db_res_params fid_parms;
uint32_t act_idx, mark, mark_flag;
uint64_t val64;
+ enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode;
int32_t rc = 0;
- if (!(tbl->mark_enable &&
- (ULP_BITMAP_ISSET(parms->act_bitmap->bits,
- BNXT_ULP_ACTION_BIT_MARK) || tbl->vfr_flag)))
+ if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP ||
+ !(mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION &&
+ ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+ BNXT_ULP_ACTION_BIT_MARK)))
return rc; /* no need to perform mark action process */
/* Get the mark id details from action property */
@@ -961,7 +965,55 @@ ulp_mapper_mark_act_ptr_process(struct bnxt_ulp_mapper_parms *parms,
}
act_idx = tfp_be_to_cpu_64(val64);
mark_flag = BNXT_ULP_MARK_LOCAL_HW_FID;
- mark_flag |= (tbl->vfr_flag) ? BNXT_ULP_MARK_VFR_ID : 0;
+ rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
+ act_idx, mark);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to add mark to flow\n");
+ return rc;
+ }
+ fid_parms.direction = tbl->direction;
+ fid_parms.resource_func = BNXT_ULP_RESOURCE_FUNC_HW_FID;
+ fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
+ fid_parms.resource_type = mark_flag;
+ fid_parms.resource_hndl = act_idx;
+ rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+ parms->tbl_idx,
+ parms->fid,
+ &fid_parms);
+ if (rc)
+ BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n", rc);
+ return rc;
+}
+
+static int32_t
+ulp_mapper_mark_vfr_idx_process(struct bnxt_ulp_mapper_parms *parms,
+ struct bnxt_ulp_mapper_tbl_info *tbl)
+{
+ struct ulp_flow_db_res_params fid_parms;
+ uint32_t act_idx, mark, mark_flag;
+ uint64_t val64;
+ enum bnxt_ulp_mark_db_opcode mark_op = tbl->mark_db_opcode;
+ int32_t rc = 0;
+
+ if (mark_op == BNXT_ULP_MARK_DB_OPCODE_NOP ||
+ mark_op == BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION)
+ return rc; /* no need to perform mark action process */
+
+ /* Get the mark id details from the computed field of dev port id */
+ mark = ULP_COMP_FLD_IDX_RD(parms, BNXT_ULP_CF_IDX_DEV_PORT_ID);
+
+ /* Get the main action pointer */
+ if (!ulp_regfile_read(parms->regfile,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
+ &val64)) {
+ BNXT_TF_DBG(ERR, "read action ptr main failed\n");
+ return -EINVAL;
+ }
+ act_idx = tfp_be_to_cpu_64(val64);
+
+ /* Set the mark flag to local fid and vfr flag */
+ mark_flag = BNXT_ULP_MARK_LOCAL_HW_FID | BNXT_ULP_MARK_VFR_ID;
+
rc = ulp_mark_db_mark_add(parms->ulp_ctx, mark_flag,
act_idx, mark);
if (rc) {
@@ -1525,6 +1577,12 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
goto error;
}
+ /* Perform the VF rep action */
+ rc = ulp_mapper_mark_vfr_idx_process(parms, tbl);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to add vfr mark rc = %d\n", rc);
+ goto error;
+ }
return rc;
error:
/*
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index cc81b31..aa66c7f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -112,8 +112,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 0,
.ident_nums = 1,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -135,8 +134,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 1,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -158,8 +156,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 1,
.ident_nums = 1,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -181,8 +178,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 2,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -204,8 +200,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 2,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -227,8 +222,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 2,
.ident_nums = 1,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -250,8 +244,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 3,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -273,8 +266,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 3,
.ident_nums = 1,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -296,8 +288,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 4,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -319,8 +310,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 4,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -342,8 +332,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 4,
.ident_nums = 1,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -365,8 +354,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 5,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -388,8 +376,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 5,
.ident_nums = 1,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -411,8 +398,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 6,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
},
@@ -434,8 +420,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.encap_num_fields = 0,
.ident_start_idx = 6,
.ident_nums = 0,
- .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
- .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
.regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 7f280fd..5376245 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -151,10 +151,11 @@ enum bnxt_ulp_hdr_type {
BNXT_ULP_HDR_TYPE_LAST = 3
};
-enum bnxt_ulp_mark_enable {
- BNXT_ULP_MARK_ENABLE_NO = 0,
- BNXT_ULP_MARK_ENABLE_YES = 1,
- BNXT_ULP_MARK_ENABLE_LAST = 2
+enum bnxt_ulp_mark_db_opcode {
+ BNXT_ULP_MARK_DB_OPCODE_NOP = 0,
+ BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION = 1,
+ BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG = 2,
+ BNXT_ULP_MARK_DB_OPCODE_LAST = 3
};
enum bnxt_ulp_mapper_opc {
@@ -214,12 +215,6 @@ enum bnxt_ulp_search_before_alloc {
BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
};
-enum bnxt_ulp_vfr_flag {
- BNXT_ULP_VFR_FLAG_NO = 0,
- BNXT_ULP_VFR_FLAG_YES = 1,
- BNXT_ULP_VFR_FLAG_LAST = 2
-};
-
enum bnxt_ulp_fdb_resource_flags {
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 8de6c4c..5d11a7e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -181,9 +181,8 @@ struct bnxt_ulp_mapper_tbl_info {
uint32_t ident_start_idx;
uint16_t ident_nums;
- uint8_t mark_enable;
enum bnxt_ulp_regfile_index regfile_idx;
- enum bnxt_ulp_vfr_flag vfr_flag;
+ enum bnxt_ulp_mark_db_opcode mark_db_opcode;
};
struct bnxt_ulp_mapper_class_key_field_info {
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 35/36] net/bnxt: rename fields in the device params structure
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (33 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 34/36] net/bnxt: enable vfr flag processing with mark db opcode Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 36/36] net/bnxt: update ulp template database for new opcodes Somnath Kotur
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The fields in the device params structure are renamed to reflect
the usage of those fields.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 12 ++++++------
drivers/net/bnxt/tf_ulp/ulp_flow_db.c | 4 ++--
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 5 +++--
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 4 ++--
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 7 +++++++
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 19 ++++++++++---------
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 12 ++++++------
7 files changed, 36 insertions(+), 27 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index fd3f61b..0c3c638 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -146,14 +146,14 @@ bnxt_init_tbl_scope_parms(struct bnxt *bp,
params->rx_max_action_entry_sz_in_bits =
BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY;
params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM;
- params->rx_num_flows_in_k = dparms->num_flows / (1024);
+ params->rx_num_flows_in_k = dparms->flow_db_num_entries / 1024;
params->rx_tbl_if_id = BNXT_ULP_RX_TBL_IF_ID;
params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY;
params->tx_max_action_entry_sz_in_bits =
BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY;
params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM;
- params->tx_num_flows_in_k = dparms->num_flows / (1024);
+ params->tx_num_flows_in_k = dparms->flow_db_num_entries / 1024;
params->tx_tbl_if_id = BNXT_ULP_TX_TBL_IF_ID;
}
}
@@ -299,11 +299,11 @@ ulp_dparms_init(struct bnxt *bp,
}
/* num_flows = max_num_kflows * 1024 */
- dparms->num_flows = bp->max_num_kflows * 1024;
+ dparms->flow_db_num_entries = bp->max_num_kflows * 1024;
/* GFID = 2 * num_flows */
- dparms->gfid_entries = dparms->num_flows * 2;
+ dparms->mark_db_gfid_entries = dparms->flow_db_num_entries * 2;
BNXT_TF_DBG(DEBUG, "Set the number of flows = %"PRIu64"\n",
- dparms->num_flows);
+ dparms->flow_db_num_entries);
return 0;
}
@@ -328,7 +328,7 @@ ulp_dparms_dev_port_intf_update(struct bnxt *bp,
}
/* Update the bp flag with gfid flag */
- if (dparms->global_fid_enable)
+ if (dparms->flow_mem_type == BNXT_ULP_FLOW_MEM_TYPE_EXT)
bp->flags |= BNXT_FLAG_GFID_ENABLE;
return 0;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index fc4c4da..22996e5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -300,7 +300,7 @@ int32_t ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt)
/* Populate the regular flow table limits. */
flow_tbl = &flow_db->flow_tbl[BNXT_ULP_REGULAR_FLOW_TABLE];
- flow_tbl->num_flows = dparms->num_flows + 1;
+ flow_tbl->num_flows = dparms->flow_db_num_entries + 1;
flow_tbl->num_resources = (flow_tbl->num_flows *
dparms->num_resources_per_flow);
@@ -317,7 +317,7 @@ int32_t ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt)
goto error_free;
/* add 1 since we are not using index 0 for flow id */
- flow_db->func_id_tbl_size = dparms->num_flows + 1;
+ flow_db->func_id_tbl_size = dparms->flow_db_num_entries + 1;
/* Allocate the function Id table */
flow_db->func_id_tbl = rte_zmalloc("bnxt_ulp_flow_db_func_id_table",
flow_db->func_id_tbl_size *
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index f86cd76..d8e544f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1285,6 +1285,7 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct tf_insert_em_entry_parms iparms = { 0 };
struct tf_delete_em_entry_parms free_parms = { 0 };
int32_t trc;
+ enum bnxt_ulp_flow_mem_type mtype = parms->device_params->flow_mem_type;
int32_t rc = 0;
kflds = ulp_mapper_key_fields_get(tbl, &num_kflds);
@@ -1375,10 +1376,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
/* Mark action process */
- if (parms->device_params->global_fid_enable &&
+ if (mtype == BNXT_ULP_FLOW_MEM_TYPE_EXT &&
tbl->resource_type == TF_MEM_EXTERNAL)
rc = ulp_mapper_mark_gfid_process(parms, tbl, iparms.flow_id);
- else if (!parms->device_params->global_fid_enable &&
+ else if (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT &&
tbl->resource_type == TF_MEM_INTERNAL)
rc = ulp_mapper_mark_act_ptr_process(parms, tbl);
if (rc) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 0c47768..89c08ab 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -77,7 +77,7 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt)
goto mem_error;
/* Need to allocate 2 * Num flows to account for hash type bit.*/
- mark_tbl->lfid_num_entries = dparms->lfid_entries;
+ mark_tbl->lfid_num_entries = dparms->mark_db_lfid_entries;
mark_tbl->lfid_tbl = rte_zmalloc("ulp_rx_em_flow_mark_table",
mark_tbl->lfid_num_entries *
sizeof(struct bnxt_lfid_mark_info),
@@ -86,7 +86,7 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt)
goto mem_error;
/* Need to allocate 2 * Num flows to account for hash type bit */
- mark_tbl->gfid_num_entries = dparms->gfid_entries;
+ mark_tbl->gfid_num_entries = dparms->mark_db_gfid_entries;
mark_tbl->gfid_tbl = rte_zmalloc("ulp_rx_eem_flow_mark_table",
mark_tbl->gfid_num_entries *
sizeof(struct bnxt_gfid_mark_info),
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 5376245..50a28af 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -139,6 +139,13 @@ enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_LAST = 2
};
+enum bnxt_ulp_flow_mem_type {
+ BNXT_ULP_FLOW_MEM_TYPE_INT = 0,
+ BNXT_ULP_FLOW_MEM_TYPE_EXT = 1,
+ BNXT_ULP_FLOW_MEM_TYPE_BOTH = 2,
+ BNXT_ULP_FLOW_MEM_TYPE_LAST = 3
+};
+
enum bnxt_ulp_glb_regfile_index {
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
index b49b0a1..bd36368 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -313,15 +313,16 @@ struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
- .global_fid_enable = BNXT_ULP_SYM_YES,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .encap_byte_swap = 1,
- .lfid_entries = 16384,
- .lfid_entry_size = 4,
- .gfid_entries = 65536,
- .gfid_entry_size = 4,
- .num_flows = 32768,
- .num_resources_per_flow = 8
+ .description = "Whitney_Plus",
+ .flow_mem_type = BNXT_ULP_FLOW_MEM_TYPE_EXT,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_swap = 1,
+ .flow_db_num_entries = 32768,
+ .mark_db_lfid_entries = 65536,
+ .mark_db_gfid_entries = 65536,
+ .flow_count_db_entries = 16384,
+ .num_resources_per_flow = 8,
+ .num_phy_ports = 2
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 5d11a7e..5c43358 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -137,14 +137,14 @@ extern struct bnxt_ulp_act_match_info ulp_act_match_list[];
/* Device specific parameters */
struct bnxt_ulp_device_params {
uint8_t description[16];
- uint32_t global_fid_enable;
+ enum bnxt_ulp_flow_mem_type flow_mem_type;
enum bnxt_ulp_byte_order byte_order;
uint8_t encap_byte_swap;
- uint32_t lfid_entries;
- uint32_t lfid_entry_size;
- uint64_t gfid_entries;
- uint32_t gfid_entry_size;
- uint64_t num_flows;
+ uint8_t num_phy_ports;
+ uint32_t mark_db_lfid_entries;
+ uint64_t mark_db_gfid_entries;
+ uint64_t flow_db_num_entries;
+ uint32_t flow_count_db_entries;
uint32_t num_resources_per_flow;
};
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 36/36] net/bnxt: update ulp template database for new opcodes
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
` (34 preceding siblings ...)
2020-06-10 6:57 ` [dpdk-dev] [PATCH 35/36] net/bnxt: rename fields in the device params structure Somnath Kotur
@ 2020-06-10 6:57 ` Somnath Kotur
35 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 6:57 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The ulp template database is updated to support the new
combined opcodes.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 263 +++++-----
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 641 +++++-------------------
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 57 ++-
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 15 +-
4 files changed, 290 insertions(+), 686 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index d33d198..8af23ef 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -10,8 +10,8 @@
uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_ACT_HID_00a1] = 1,
- [BNXT_ULP_ACT_HID_0040] = 2,
- [BNXT_ULP_ACT_HID_0029] = 3
+ [BNXT_ULP_ACT_HID_0029] = 2,
+ [BNXT_ULP_ACT_HID_0040] = 3
};
struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
@@ -25,20 +25,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 0
},
[2] = {
- .act_hid = BNXT_ULP_ACT_HID_0040,
- .act_sig = { .bits =
- BNXT_ULP_ACTION_BIT_VPORT |
- BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
- BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 1
- },
- [3] = {
.act_hid = BNXT_ULP_ACT_HID_0029,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_RSS |
BNXT_ULP_ACTION_BIT_VNIC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [3] = {
+ .act_hid = BNXT_ULP_ACT_HID_0040,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
+ BNXT_ULP_ACTION_BIT_VPORT |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 2
}
};
@@ -76,33 +76,36 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0,
- .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
- .direction = TF_DIR_TX,
+ .direction = TF_DIR_RX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
.result_start_idx = 26,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 12,
- .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
- .direction = TF_DIR_RX,
+ .direction = TF_DIR_TX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .result_start_idx = 64,
+ .result_start_idx = 52,
.result_bit_size = 128,
.result_num_fields = 26,
- .encap_num_fields = 0,
- .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ .encap_num_fields = 12,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
}
};
@@ -302,11 +305,116 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
.result_operand = {
- BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
@@ -433,118 +541,5 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
- },
- {
- .field_bit_size = 14,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 8,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 11,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 10,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {
- BNXT_ULP_SYM_DECAP_FUNC_NONE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
- },
- {
- .field_bit_size = 12,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
- .result_operand = {
- (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
- BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 2,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- },
- {
- .field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
}
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index aa66c7f..1945893 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -164,7 +164,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -274,7 +274,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_TX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -384,7 +384,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
@@ -559,11 +559,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -581,11 +577,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -601,51 +593,31 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -661,51 +633,33 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -721,192 +675,107 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 3,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_HREC_NEXT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 9,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
- BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 7,
@@ -923,33 +792,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_AGG_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_PKT_TYPE_L2,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1181,11 +1038,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -1203,11 +1056,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1223,51 +1072,31 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1283,51 +1112,31 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1343,192 +1152,107 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 3,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_HREC_NEXT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 9,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
- BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 7,
@@ -1545,33 +1269,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_AGG_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_PKT_TYPE_L2,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1755,11 +1467,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
@@ -1803,11 +1511,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -1825,11 +1529,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1845,51 +1545,31 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1905,51 +1585,31 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -1965,33 +1625,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 3,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -2007,11 +1655,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
@@ -2029,11 +1673,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -2049,51 +1689,31 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_ERROR_NO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -2109,40 +1729,26 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -2158,21 +1764,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_HREC_NEXT_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 9,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
- BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 7,
@@ -2189,33 +1786,21 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 1,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_AGG_ERROR_IGNORE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_PKT_TYPE_L2,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 50a28af..ac84f88 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -6,7 +6,7 @@
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 15
+#define BNXT_ULP_REGFILE_MAX_SZ 16
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
@@ -25,7 +25,7 @@
#define BNXT_ULP_ACT_HID_SHFTL 23
#define BNXT_ULP_ACT_HID_MASK 255
#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
-#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
+#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 3
enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
@@ -133,6 +133,11 @@ enum bnxt_ulp_device_id {
BNXT_ULP_DEVICE_ID_LAST = 4
};
+enum bnxt_ulp_df_param_type {
+ BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID = 0,
+ BNXT_ULP_DF_PARAM_TYPE_LAST = 1
+};
+
enum bnxt_ulp_direction {
BNXT_ULP_DIRECTION_INGRESS = 0,
BNXT_ULP_DIRECTION_EGRESS = 1,
@@ -148,7 +153,8 @@ enum bnxt_ulp_flow_mem_type {
enum bnxt_ulp_glb_regfile_index {
BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
- BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID = 1,
+ BNXT_ULP_GLB_REGFILE_INDEX_LAST = 2
};
enum bnxt_ulp_hdr_type {
@@ -158,13 +164,6 @@ enum bnxt_ulp_hdr_type {
BNXT_ULP_HDR_TYPE_LAST = 3
};
-enum bnxt_ulp_mark_db_opcode {
- BNXT_ULP_MARK_DB_OPCODE_NOP = 0,
- BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION = 1,
- BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG = 2,
- BNXT_ULP_MARK_DB_OPCODE_LAST = 3
-};
-
enum bnxt_ulp_mapper_opc {
BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT = 0,
BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD = 1,
@@ -178,9 +177,16 @@ enum bnxt_ulp_mapper_opc {
BNXT_ULP_MAPPER_OPC_LAST = 9
};
+enum bnxt_ulp_mark_db_opcode {
+ BNXT_ULP_MARK_DB_OPCODE_NOP = 0,
+ BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION = 1,
+ BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG = 2,
+ BNXT_ULP_MARK_DB_OPCODE_LAST = 3
+};
+
enum bnxt_ulp_match_type {
BNXT_ULP_MATCH_TYPE_EM = 0,
- BNXT_ULP_MATCH_TYPE_WC = 1,
+ BNXT_ULP_MATCH_TYPE_WM = 1,
BNXT_ULP_MATCH_TYPE_LAST = 2
};
@@ -212,8 +218,9 @@ enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
- BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
- BNXT_ULP_REGFILE_INDEX_LAST = 15
+ BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 14,
+ BNXT_ULP_REGFILE_INDEX_NOT_USED = 15,
+ BNXT_ULP_REGFILE_INDEX_LAST = 16
};
enum bnxt_ulp_search_before_alloc {
@@ -258,14 +265,20 @@ enum bnxt_ulp_resource_func {
enum bnxt_ulp_resource_sub_type {
BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT_INDEX = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_INDEX = 2,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
};
enum bnxt_ulp_sym {
+ BNXT_ULP_SYM_ACT_REC_DROP_NO = 0,
+ BNXT_ULP_SYM_ACT_REC_DROP_YES = 1,
+ BNXT_ULP_SYM_ACT_REC_METER_EN_NO = 0,
+ BNXT_ULP_SYM_ACT_REC_METER_EN_YES = 1,
+ BNXT_ULP_SYM_ACT_REC_POP_VLAN_NO = 0,
+ BNXT_ULP_SYM_ACT_REC_POP_VLAN_YES = 1,
BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
BNXT_ULP_SYM_AGG_ERROR_NO = 0,
BNXT_ULP_SYM_AGG_ERROR_YES = 1,
@@ -399,8 +412,9 @@ enum bnxt_ulp_sym {
BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
BNXT_ULP_SYM_RESERVED_IGNORE = 0,
+ BNXT_ULP_SYM_STINGRAY_EXT_EM_MAX_KEY_SIZE = 448,
+ BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 16,
BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
- BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
@@ -466,7 +480,12 @@ enum bnxt_ulp_sym {
BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
- BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_WH_PLUS_EXT_ACT_REC = 0,
+ BNXT_ULP_SYM_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448,
+ BNXT_ULP_SYM_WH_PLUS_INT_ACT_REC = 1,
+ BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 4,
+ BNXT_ULP_SYM_WH_PLUS_MC_ACT_REC = 1,
+ BNXT_ULP_SYM_WH_PLUS_UC_ACT_REC = 0,
BNXT_ULP_SYM_YES = 1
};
@@ -566,7 +585,7 @@ enum bnxt_ulp_class_hid {
enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_00a1 = 0x00a1,
- BNXT_ULP_ACT_HID_0040 = 0x0040,
- BNXT_ULP_ACT_HID_0029 = 0x0029
+ BNXT_ULP_ACT_HID_0029 = 0x0029,
+ BNXT_ULP_ACT_HID_0040 = 0x0040
};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
index bd36368..e4b564a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -313,7 +313,6 @@ struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
- .description = "Whitney_Plus",
.flow_mem_type = BNXT_ULP_FLOW_MEM_TYPE_EXT,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
@@ -334,10 +333,16 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
.direction = TF_DIR_RX
},
[1] = {
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ },
+ [2] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID,
+ .direction = TF_DIR_RX
}
};
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules
2020-06-12 12:49 [dpdk-dev] [PATCH v3 00/36] bnxt patches Somnath Kotur
@ 2020-06-12 12:50 ` Somnath Kotur
0 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-12 12:50 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The ulp template db file is broken into three parts namely the
table, class and action files.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/meson.build | 4 +-
drivers/net/bnxt/tf_ulp/Makefile | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 696 +++++
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 3428 +++++++++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 587 ++++
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h | 225 ++
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 543 ++++
drivers/net/bnxt/tf_ulp/ulp_utils.h | 2 +-
16 files changed, 5494 insertions(+), 11 deletions(-)
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index 59dda69..4306c60 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -35,7 +35,9 @@ sources = files('bnxt_cpr.c',
'tf_ulp/bnxt_ulp.c',
'tf_ulp/ulp_mark_mgr.c',
'tf_ulp/ulp_flow_db.c',
- 'tf_ulp/ulp_template_db.c',
+ 'tf_ulp/ulp_template_db_tbl.c',
+ 'tf_ulp/ulp_template_db_class.c',
+ 'tf_ulp/ulp_template_db_act.c',
'tf_ulp/ulp_utils.c',
'tf_ulp/ulp_mapper.c',
'tf_ulp/ulp_matcher.c',
diff --git a/drivers/net/bnxt/tf_ulp/Makefile b/drivers/net/bnxt/tf_ulp/Makefile
index d5c22b3..57341f8 100644
--- a/drivers/net/bnxt/tf_ulp/Makefile
+++ b/drivers/net/bnxt/tf_ulp/Makefile
@@ -4,7 +4,9 @@
# Copyright(c) Broadcom Limited.
# All rights reserved.
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_tbl.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_class.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_act.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_rte_parser.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp_flow.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_matcher.c
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 00e21fa..10183ac 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -15,7 +15,7 @@
#include "tf_core.h"
#include "tf_ext_flow_handle.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "ulp_mark_mgr.h"
#include "ulp_flow_db.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 357a589..1fc0601 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -7,7 +7,7 @@
#define _ULP_FLOW_DB_H_
#include "bnxt_ulp.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS 128
#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES 5
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 300dca3..3872921 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -6,7 +6,7 @@
#include <rte_log.h>
#include <rte_malloc.h>
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_utils.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 67410c9..1df23db 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -10,7 +10,7 @@
#include <rte_flow.h>
#include <rte_flow_driver.h>
#include "tf_core.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "ulp_utils.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 0e13a46..0c47768 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -11,7 +11,7 @@
#include "tf_ext_flow_handle.h"
#include "ulp_mark_mgr.h"
#include "bnxt_tf_common.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#define ULP_MARK_DB_ENTRY_SET_VALID(mark_info) ((mark_info)->flags |=\
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
index fc19783..a582188 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
@@ -8,7 +8,7 @@
#include <rte_log.h>
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index db040e3..41ac77c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -4,7 +4,7 @@
*/
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_rte_parser.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index c90bff4..8788431 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -9,7 +9,7 @@
#include <rte_log.h>
#include <rte_flow.h>
#include <rte_flow_driver.h>
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
/* defines to be used in the tunnel header parsing */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
new file mode 100644
index 0000000..bc471fe
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -0,0 +1,696 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
+ [BNXT_ULP_ACT_HID_00a1] = 1,
+ [BNXT_ULP_ACT_HID_0040] = 2,
+ [BNXT_ULP_ACT_HID_0029] = 3
+};
+
+struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
+ [1] = {
+ .act_hid = BNXT_ULP_ACT_HID_00a1,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 0
+ },
+ [2] = {
+ .act_hid = BNXT_ULP_ACT_HID_0040,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VPORT |
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 1
+ },
+ [3] = {
+ .act_hid = BNXT_ULP_ACT_HID_0029,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
+ [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 1
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 2
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 0,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_TX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 26,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 12,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 64,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
new file mode 100644
index 0000000..f33136f
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -0,0 +1,3428 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
+ [BNXT_ULP_CLASS_HID_0080] = 1,
+ [BNXT_ULP_CLASS_HID_0000] = 2,
+ [BNXT_ULP_CLASS_HID_0087] = 3
+};
+
+struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
+ [1] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0080,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 0,
+ .act_vnic = 0,
+ .wc_pri = 0
+ },
+ [2] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0000,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .field_sig = { .bits =
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 1,
+ .act_vnic = 0,
+ .wc_pri = 0
+ },
+ [3] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0087,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 2,
+ .act_vnic = 0,
+ .wc_pri = 0
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
+ [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 5
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 10
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 0,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 0,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 1,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 15,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 14,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 18,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 15,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 60,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 23,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 71,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 32,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 73,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 33,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 86,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 46,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 89,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 47,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 131,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 55,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 142,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 64,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 144,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 157,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 78,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 160,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 79,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 202,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 87,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ }
+};
+
+struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ }
+};
+
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
new file mode 100644
index 0000000..07a3c78
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -0,0 +1,587 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef ULP_TEMPLATE_DB_H_
+#define ULP_TEMPLATE_DB_H_
+
+#define BNXT_ULP_REGFILE_MAX_SZ 15
+#define BNXT_ULP_MAX_NUM_DEVICES 4
+#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
+#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
+#define BNXT_ULP_CLASS_HID_SHFTR 16
+#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_MASK 255
+#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
+#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
+#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
+#define BNXT_ULP_ACT_HID_SHFTR 0
+#define BNXT_ULP_ACT_HID_SHFTL 23
+#define BNXT_ULP_ACT_HID_MASK 255
+#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
+#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
+
+enum bnxt_ulp_action_bit {
+ BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
+ BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002,
+ BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004,
+ BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008,
+ BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010,
+ BNXT_ULP_ACTION_BIT_VNIC = 0x0000000000000020,
+ BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040,
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080,
+ BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100,
+ BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200,
+ BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400,
+ BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800,
+ BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000,
+ BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000,
+ BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000,
+ BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000,
+ BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000,
+ BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000,
+ BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000,
+ BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000200000,
+ BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000400000,
+ BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000800000,
+ BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000001000000,
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000002000000,
+ BNXT_ULP_ACTION_BIT_NVGRE_ENCAP = 0x0000000004000000,
+ BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000
+};
+
+enum bnxt_ulp_hdr_bit {
+ BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001,
+ BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002,
+ BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004,
+ BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008,
+ BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010,
+ BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020,
+ BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040,
+ BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080,
+ BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100,
+ BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200,
+ BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400,
+ BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000
+};
+
+enum bnxt_ulp_act_type {
+ BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
+ BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
+ BNXT_ULP_ACT_TYPE_END = 2,
+ BNXT_ULP_ACT_TYPE_LAST = 3
+};
+
+enum bnxt_ulp_byte_order {
+ BNXT_ULP_BYTE_ORDER_BE = 0,
+ BNXT_ULP_BYTE_ORDER_LE = 1,
+ BNXT_ULP_BYTE_ORDER_LAST = 2
+};
+
+enum bnxt_ulp_cf_idx {
+ BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2,
+ BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
+ BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
+ BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5,
+ BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6,
+ BNXT_ULP_CF_IDX_INCOMING_IF = 7,
+ BNXT_ULP_CF_IDX_DIRECTION = 8,
+ BNXT_ULP_CF_IDX_SVIF_FLAG = 9,
+ BNXT_ULP_CF_IDX_O_L3 = 10,
+ BNXT_ULP_CF_IDX_I_L3 = 11,
+ BNXT_ULP_CF_IDX_O_L4 = 12,
+ BNXT_ULP_CF_IDX_I_L4 = 13,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 14,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
+ BNXT_ULP_CF_IDX_LAST = 28
+};
+
+enum bnxt_ulp_critical_resource {
+ BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
+ BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
+ BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
+};
+
+enum bnxt_ulp_device_id {
+ BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
+ BNXT_ULP_DEVICE_ID_THOR = 1,
+ BNXT_ULP_DEVICE_ID_STINGRAY = 2,
+ BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
+ BNXT_ULP_DEVICE_ID_LAST = 4
+};
+
+enum bnxt_ulp_direction {
+ BNXT_ULP_DIRECTION_INGRESS = 0,
+ BNXT_ULP_DIRECTION_EGRESS = 1,
+ BNXT_ULP_DIRECTION_LAST = 2
+};
+
+enum bnxt_ulp_glb_regfile_index {
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
+ BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
+};
+
+enum bnxt_ulp_hdr_type {
+ BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
+ BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
+ BNXT_ULP_HDR_TYPE_END = 2,
+ BNXT_ULP_HDR_TYPE_LAST = 3
+};
+
+enum bnxt_ulp_mark_enable {
+ BNXT_ULP_MARK_ENABLE_NO = 0,
+ BNXT_ULP_MARK_ENABLE_YES = 1,
+ BNXT_ULP_MARK_ENABLE_LAST = 2
+};
+
+enum bnxt_ulp_mask_opc {
+ BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
+ BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
+ BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3,
+ BNXT_ULP_MASK_OPC_ADD_PAD = 4,
+ BNXT_ULP_MASK_OPC_LAST = 5
+};
+
+enum bnxt_ulp_match_type {
+ BNXT_ULP_MATCH_TYPE_EM = 0,
+ BNXT_ULP_MATCH_TYPE_WC = 1,
+ BNXT_ULP_MATCH_TYPE_LAST = 2
+};
+
+enum bnxt_ulp_priority {
+ BNXT_ULP_PRIORITY_LEVEL_0 = 0,
+ BNXT_ULP_PRIORITY_LEVEL_1 = 1,
+ BNXT_ULP_PRIORITY_LEVEL_2 = 2,
+ BNXT_ULP_PRIORITY_LEVEL_3 = 3,
+ BNXT_ULP_PRIORITY_LEVEL_4 = 4,
+ BNXT_ULP_PRIORITY_LEVEL_5 = 5,
+ BNXT_ULP_PRIORITY_LEVEL_6 = 6,
+ BNXT_ULP_PRIORITY_LEVEL_7 = 7,
+ BNXT_ULP_PRIORITY_NOT_USED = 8,
+ BNXT_ULP_PRIORITY_LAST = 9
+};
+
+enum bnxt_ulp_regfile_index {
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
+ BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
+ BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
+ BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
+ BNXT_ULP_REGFILE_INDEX_LAST = 15
+};
+
+enum bnxt_ulp_result_opc {
+ BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
+ BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
+ BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
+ BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
+ BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
+ BNXT_ULP_RESULT_OPC_LAST = 7
+};
+
+enum bnxt_ulp_search_before_alloc {
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
+};
+
+enum bnxt_ulp_spec_opc {
+ BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
+ BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
+ BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
+ BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4,
+ BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
+ BNXT_ULP_SPEC_OPC_LAST = 6
+};
+
+enum bnxt_ulp_vfr_flag {
+ BNXT_ULP_VFR_FLAG_NO = 0,
+ BNXT_ULP_VFR_FLAG_YES = 1,
+ BNXT_ULP_VFR_FLAG_LAST = 2
+};
+
+enum bnxt_ulp_fdb_resource_flags {
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
+};
+
+enum bnxt_ulp_fdb_type {
+ BNXT_ULP_FDB_TYPE_DEFAULT = 1,
+ BNXT_ULP_FDB_TYPE_REGULAR = 0
+};
+
+enum bnxt_ulp_flow_dir_bitmask {
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
+ BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
+};
+
+enum bnxt_ulp_match_type_bitmask {
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
+ BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
+};
+
+enum bnxt_ulp_resource_func {
+ BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
+ BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
+ BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
+ BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
+ BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
+ BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
+ BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
+ BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
+ BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
+ BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
+};
+
+enum bnxt_ulp_resource_sub_type {
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
+};
+
+enum bnxt_ulp_sym {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_AGG_ERROR_NO = 0,
+ BNXT_ULP_SYM_AGG_ERROR_YES = 1,
+ BNXT_ULP_SYM_BIG_ENDIAN = 0,
+ BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+ BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+ BNXT_ULP_SYM_ECV_VALID_NO = 0,
+ BNXT_ULP_SYM_ECV_VALID_YES = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
+ BNXT_ULP_SYM_HREC_NEXT_NO = 0,
+ BNXT_ULP_SYM_HREC_NEXT_YES = 1,
+ BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
+ BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
+ BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
+ BNXT_ULP_SYM_IP_PROTO_TCP = 6,
+ BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+ BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+ BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
+ BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
+ BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+ BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+ BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+ BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
+ BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
+ BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
+ BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
+ BNXT_ULP_SYM_NO = 0,
+ BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+ BNXT_ULP_SYM_POP_VLAN_NO = 0,
+ BNXT_ULP_SYM_POP_VLAN_YES = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
+ BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
+ BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
+ BNXT_ULP_SYM_RESERVED_IGNORE = 0,
+ BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_YES = 1
+};
+
+enum bnxt_ulp_act_prop_sz {
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
+ BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
+ BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
+ BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
+ BNXT_ULP_ACT_PROP_SZ_MARK = 4,
+ BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
+ BNXT_ULP_ACT_PROP_SZ_METER = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
+ BNXT_ULP_ACT_PROP_SZ_LAST = 4
+};
+
+enum bnxt_ulp_act_prop_idx {
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
+ BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
+ BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
+ BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
+ BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
+ BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
+ BNXT_ULP_ACT_PROP_IDX_MARK = 44,
+ BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
+ BNXT_ULP_ACT_PROP_IDX_METER = 52,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,
+ BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,
+ BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
+ BNXT_ULP_ACT_PROP_IDX_LAST = 268
+};
+
+enum bnxt_ulp_class_hid {
+ BNXT_ULP_CLASS_HID_0080 = 0x0080,
+ BNXT_ULP_CLASS_HID_0000 = 0x0000,
+ BNXT_ULP_CLASS_HID_0087 = 0x0087
+};
+
+enum bnxt_ulp_act_hid {
+ BNXT_ULP_ACT_HID_00a1 = 0x00a1,
+ BNXT_ULP_ACT_HID_0040 = 0x0040,
+ BNXT_ULP_ACT_HID_0029 = 0x0029
+};
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
new file mode 100644
index 0000000..84b9523
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef ULP_HDR_FIELD_ENUMS_H_
+#define ULP_HDR_FIELD_ENUMS_H_
+
+enum bnxt_ulp_hf0 {
+ BNXT_ULP_HF0_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF0_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF0_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF0_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF0_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF0_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF0_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF0_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF0_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF0_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF0_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF0_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF0_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF0_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF0_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF0_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf1 {
+ BNXT_ULP_HF1_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF1_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF1_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF1_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF1_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF1_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF1_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF1_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF1_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF1_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF1_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF1_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF1_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF1_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF1_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF1_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF1_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF1_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf2 {
+ BNXT_ULP_HF2_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF2_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF2_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF2_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF2_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF2_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF2_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF2_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF2_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF2_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF2_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF2_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF2_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF2_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF2_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF2_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF2_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF2_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF2_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF2_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF2_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF2_IDX_O_UDP_CSUM = 23,
+ BNXT_ULP_HF2_IDX_T_VXLAN_FLAGS = 24,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD0 = 25,
+ BNXT_ULP_HF2_IDX_T_VXLAN_VNI = 26,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD1 = 27,
+ BNXT_ULP_HF2_IDX_I_ETH_DMAC = 28,
+ BNXT_ULP_HF2_IDX_I_ETH_SMAC = 29,
+ BNXT_ULP_HF2_IDX_I_ETH_TYPE = 30,
+ BNXT_ULP_HF2_IDX_IO_VLAN_CFI_PRI = 31,
+ BNXT_ULP_HF2_IDX_IO_VLAN_VID = 32,
+ BNXT_ULP_HF2_IDX_IO_VLAN_TYPE = 33,
+ BNXT_ULP_HF2_IDX_II_VLAN_CFI_PRI = 34,
+ BNXT_ULP_HF2_IDX_II_VLAN_VID = 35,
+ BNXT_ULP_HF2_IDX_II_VLAN_TYPE = 36,
+ BNXT_ULP_HF2_IDX_I_IPV4_VER = 37,
+ BNXT_ULP_HF2_IDX_I_IPV4_TOS = 38,
+ BNXT_ULP_HF2_IDX_I_IPV4_LEN = 39,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_ID = 40,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_OFF = 41,
+ BNXT_ULP_HF2_IDX_I_IPV4_TTL = 42,
+ BNXT_ULP_HF2_IDX_I_IPV4_NEXT_PID = 43,
+ BNXT_ULP_HF2_IDX_I_IPV4_CSUM = 44,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR = 45,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR = 46,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT = 47,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT = 48,
+ BNXT_ULP_HF2_IDX_I_UDP_LENGTH = 49,
+ BNXT_ULP_HF2_IDX_I_UDP_CSUM = 50
+};
+
+enum bnxt_ulp_hf_bitmask0 {
+ BNXT_ULP_HF0_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask1 {
+ BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask2 {
+ BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_DMAC = 0x0000000800000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_SMAC = 0x0000000400000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_TYPE = 0x0000000200000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_VID = 0x0000000080000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_VID = 0x0000000010000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_VER = 0x0000000004000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TOS = 0x0000000002000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_LEN = 0x0000000001000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TTL = 0x0000000000200000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_NEXT_PID = 0x0000000000100000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_CSUM = 0x0000000000002000
+};
+
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
new file mode 100644
index 0000000..b49b0a1
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -0,0 +1,543 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint32_t ulp_act_prop_map_table[] = {
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE,
+ [BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_PORT_ID] =
+ BNXT_ULP_ACT_PROP_SZ_PORT_ID,
+ [BNXT_ULP_ACT_PROP_IDX_VNIC] =
+ BNXT_ULP_ACT_PROP_SZ_VNIC,
+ [BNXT_ULP_ACT_PROP_IDX_VPORT] =
+ BNXT_ULP_ACT_PROP_SZ_VPORT,
+ [BNXT_ULP_ACT_PROP_IDX_MARK] =
+ BNXT_ULP_ACT_PROP_SZ_MARK,
+ [BNXT_ULP_ACT_PROP_IDX_COUNT] =
+ BNXT_ULP_ACT_PROP_SZ_COUNT,
+ [BNXT_ULP_ACT_PROP_IDX_METER] =
+ BNXT_ULP_ACT_PROP_SZ_METER,
+ [BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN,
+ [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP] =
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP,
+ [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID] =
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST,
+ [BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_DST,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN,
+ [BNXT_ULP_ACT_PROP_IDX_LAST] =
+ BNXT_ULP_ACT_PROP_SZ_LAST
+};
+
+struct bnxt_ulp_rte_act_info ulp_act_info[] = {
+ [RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_END,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_VOID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_void_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PASSTHRU] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_JUMP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_MARK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_mark_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_FLAG] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_QUEUE] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DROP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_drop_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_COUNT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_count_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_RSS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_rss_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PF] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_pf_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_VF] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vf_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PHY_PORT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_phy_port_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PORT_ID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_port_id_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_METER] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SECURITY] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vxlan_encap_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vxlan_decap_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_RAW_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TP_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_MAC_SWAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
+};
+
+struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_RX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_TX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_RX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_TX] = {
+ .num_entries = 16384
+ }
+};
+
+struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
+ [BNXT_ULP_DEVICE_ID_WH_PLUS] = {
+ .global_fid_enable = BNXT_ULP_SYM_YES,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_swap = 1,
+ .lfid_entries = 16384,
+ .lfid_entry_size = 4,
+ .gfid_entries = 65536,
+ .gfid_entry_size = 4,
+ .num_flows = 32768,
+ .num_resources_per_flow = 8
+ }
+};
+
+struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ [0] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ [1] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ }
+};
+
+struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
+ [RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_END,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VOID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_void_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_INVERT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ANY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PF] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_pf_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_VF] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vf_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_phy_port_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_PORT_ID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_port_id_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_RAW] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_eth_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_VLAN] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vlan_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV4] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ipv4_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV6] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ipv6_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_UDP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_udp_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_TCP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_tcp_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_SCTP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VXLAN] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vxlan_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_E_TAG] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_NVGRE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_MPLS] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GRE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_FUZZY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTPC] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTPU] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ESP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GENEVE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV6_EXT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_MARK] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_META] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GRE_KEY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTP_PSC] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOES] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOED] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_NSH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_IGMP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_AH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_HIGIG2] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ }
+};
+
+uint32_t bnxt_ulp_encap_vtag_map[] = {
+ [0] = BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP,
+ [1] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
+ [2] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI
+};
+
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 2f64bcb..13d9e88 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -7,7 +7,7 @@
#define _ULP_UTILS_H_
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
/*
* Macros for bitmap sets and gets
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules
2020-06-10 11:43 [dpdk-dev] [PATCH 00/36] bnxt patches Somnath Kotur
@ 2020-06-10 11:44 ` Somnath Kotur
0 siblings, 0 replies; 39+ messages in thread
From: Somnath Kotur @ 2020-06-10 11:44 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The ulp template db file is broken into three parts namely the
table, class and action files.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/meson.build | 4 +-
drivers/net/bnxt/tf_ulp/Makefile | 4 +-
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_matcher.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 2 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 696 +++++
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 3428 +++++++++++++++++++++++
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 587 ++++
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h | 225 ++
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 543 ++++
drivers/net/bnxt/tf_ulp/ulp_utils.h | 2 +-
16 files changed, 5494 insertions(+), 11 deletions(-)
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index 59dda69..4306c60 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -35,7 +35,9 @@ sources = files('bnxt_cpr.c',
'tf_ulp/bnxt_ulp.c',
'tf_ulp/ulp_mark_mgr.c',
'tf_ulp/ulp_flow_db.c',
- 'tf_ulp/ulp_template_db.c',
+ 'tf_ulp/ulp_template_db_tbl.c',
+ 'tf_ulp/ulp_template_db_class.c',
+ 'tf_ulp/ulp_template_db_act.c',
'tf_ulp/ulp_utils.c',
'tf_ulp/ulp_mapper.c',
'tf_ulp/ulp_matcher.c',
diff --git a/drivers/net/bnxt/tf_ulp/Makefile b/drivers/net/bnxt/tf_ulp/Makefile
index d5c22b3..57341f8 100644
--- a/drivers/net/bnxt/tf_ulp/Makefile
+++ b/drivers/net/bnxt/tf_ulp/Makefile
@@ -4,7 +4,9 @@
# Copyright(c) Broadcom Limited.
# All rights reserved.
-SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_tbl.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_class.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_template_db_act.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_rte_parser.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/bnxt_ulp_flow.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_ulp/ulp_matcher.c
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 00e21fa..10183ac 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -15,7 +15,7 @@
#include "tf_core.h"
#include "tf_ext_flow_handle.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "ulp_mark_mgr.h"
#include "ulp_flow_db.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 357a589..1fc0601 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -7,7 +7,7 @@
#define _ULP_FLOW_DB_H_
#include "bnxt_ulp.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#define BNXT_FLOW_DB_DEFAULT_NUM_FLOWS 128
#define BNXT_FLOW_DB_DEFAULT_NUM_RESOURCES 5
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 300dca3..3872921 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -6,7 +6,7 @@
#include <rte_log.h>
#include <rte_malloc.h>
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_utils.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 67410c9..1df23db 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -10,7 +10,7 @@
#include <rte_flow.h>
#include <rte_flow_driver.h>
#include "tf_core.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_ulp.h"
#include "ulp_utils.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 0e13a46..0c47768 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -11,7 +11,7 @@
#include "tf_ext_flow_handle.h"
#include "ulp_mark_mgr.h"
#include "bnxt_tf_common.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#define ULP_MARK_DB_ENTRY_SET_VALID(mark_info) ((mark_info)->flags |=\
diff --git a/drivers/net/bnxt/tf_ulp/ulp_matcher.h b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
index fc19783..a582188 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_matcher.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_matcher.h
@@ -8,7 +8,7 @@
#include <rte_log.h>
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index db040e3..41ac77c 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -4,7 +4,7 @@
*/
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#include "bnxt_tf_common.h"
#include "ulp_rte_parser.h"
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index c90bff4..8788431 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -9,7 +9,7 @@
#include <rte_log.h>
#include <rte_flow.h>
#include <rte_flow_driver.h>
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
/* defines to be used in the tunnel header parsing */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
new file mode 100644
index 0000000..bc471fe
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -0,0 +1,696 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
+ [BNXT_ULP_ACT_HID_00a1] = 1,
+ [BNXT_ULP_ACT_HID_0040] = 2,
+ [BNXT_ULP_ACT_HID_0029] = 3
+};
+
+struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
+ [1] = {
+ .act_hid = BNXT_ULP_ACT_HID_00a1,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 0
+ },
+ [2] = {
+ .act_hid = BNXT_ULP_ACT_HID_0040,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VPORT |
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 1
+ },
+ [3] = {
+ .act_hid = BNXT_ULP_ACT_HID_0029,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
+ [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 1
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 2
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 0,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_TX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 26,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 12,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_EXT,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 64,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VPORT >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VPORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 0,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN & 0xff,
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
new file mode 100644
index 0000000..f33136f
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -0,0 +1,3428 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
+ [BNXT_ULP_CLASS_HID_0080] = 1,
+ [BNXT_ULP_CLASS_HID_0000] = 2,
+ [BNXT_ULP_CLASS_HID_0087] = 3
+};
+
+struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
+ [1] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0080,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 0,
+ .act_vnic = 0,
+ .wc_pri = 0
+ },
+ [2] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0000,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .field_sig = { .bits =
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 1,
+ .act_vnic = 0,
+ .wc_pri = 0
+ },
+ [3] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0087,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 2,
+ .act_vnic = 0,
+ .wc_pri = 0
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
+ [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 0
+ },
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 5
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 10
+ }
+};
+
+struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 0,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 0,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 0,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 2,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 1,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 15,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 14,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 18,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 15,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 60,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 23,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 71,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 32,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 73,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 33,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 86,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 46,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 89,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 47,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 131,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 55,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 142,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 64,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 144,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 65,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 157,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 78,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 1,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 160,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 79,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_NO,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 202,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 87,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_enable = BNXT_ULP_MARK_ENABLE_YES,
+ .vfr_flag = BNXT_ULP_VFR_FLAG_NO,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_NOT_USED
+ }
+};
+
+struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ (BNXT_ULP_SYM_RESERVED_IGNORE >> 8) & 0xff,
+ BNXT_ULP_SYM_RESERVED_IGNORE & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_PKT_TYPE_L2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00f9 >> 8) & 0xff,
+ 0x00f9 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 33,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 5,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 9,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (0x00c5 >> 8) & 0xff,
+ 0x00c5 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_L2_CTXT,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .ident_type = TF_IDENT_TYPE_EM_PROF,
+ .regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+ .ident_bit_size = 10,
+ .ident_bit_pos = 0
+ }
+};
+
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
new file mode 100644
index 0000000..07a3c78
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -0,0 +1,587 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef ULP_TEMPLATE_DB_H_
+#define ULP_TEMPLATE_DB_H_
+
+#define BNXT_ULP_REGFILE_MAX_SZ 15
+#define BNXT_ULP_MAX_NUM_DEVICES 4
+#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
+#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
+#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 4
+#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
+#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
+#define BNXT_ULP_CLASS_HID_SHFTR 16
+#define BNXT_ULP_CLASS_HID_SHFTL 23
+#define BNXT_ULP_CLASS_HID_MASK 255
+#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
+#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
+#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
+#define BNXT_ULP_ACT_HID_SHFTR 0
+#define BNXT_ULP_ACT_HID_SHFTL 23
+#define BNXT_ULP_ACT_HID_MASK 255
+#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
+#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 2
+
+enum bnxt_ulp_action_bit {
+ BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
+ BNXT_ULP_ACTION_BIT_DROP = 0x0000000000000002,
+ BNXT_ULP_ACTION_BIT_COUNT = 0x0000000000000004,
+ BNXT_ULP_ACTION_BIT_RSS = 0x0000000000000008,
+ BNXT_ULP_ACTION_BIT_METER = 0x0000000000000010,
+ BNXT_ULP_ACTION_BIT_VNIC = 0x0000000000000020,
+ BNXT_ULP_ACTION_BIT_VPORT = 0x0000000000000040,
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP = 0x0000000000000080,
+ BNXT_ULP_ACTION_BIT_NVGRE_DECAP = 0x0000000000000100,
+ BNXT_ULP_ACTION_BIT_POP_MPLS = 0x0000000000000200,
+ BNXT_ULP_ACTION_BIT_PUSH_MPLS = 0x0000000000000400,
+ BNXT_ULP_ACTION_BIT_MAC_SWAP = 0x0000000000000800,
+ BNXT_ULP_ACTION_BIT_SET_MAC_SRC = 0x0000000000001000,
+ BNXT_ULP_ACTION_BIT_SET_MAC_DST = 0x0000000000002000,
+ BNXT_ULP_ACTION_BIT_POP_VLAN = 0x0000000000004000,
+ BNXT_ULP_ACTION_BIT_PUSH_VLAN = 0x0000000000008000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_PCP = 0x0000000000010000,
+ BNXT_ULP_ACTION_BIT_SET_VLAN_VID = 0x0000000000020000,
+ BNXT_ULP_ACTION_BIT_SET_IPV4_SRC = 0x0000000000040000,
+ BNXT_ULP_ACTION_BIT_SET_IPV4_DST = 0x0000000000080000,
+ BNXT_ULP_ACTION_BIT_SET_IPV6_SRC = 0x0000000000100000,
+ BNXT_ULP_ACTION_BIT_SET_IPV6_DST = 0x0000000000200000,
+ BNXT_ULP_ACTION_BIT_DEC_TTL = 0x0000000000400000,
+ BNXT_ULP_ACTION_BIT_SET_TP_SRC = 0x0000000000800000,
+ BNXT_ULP_ACTION_BIT_SET_TP_DST = 0x0000000001000000,
+ BNXT_ULP_ACTION_BIT_VXLAN_ENCAP = 0x0000000002000000,
+ BNXT_ULP_ACTION_BIT_NVGRE_ENCAP = 0x0000000004000000,
+ BNXT_ULP_ACTION_BIT_LAST = 0x0000000008000000
+};
+
+enum bnxt_ulp_hdr_bit {
+ BNXT_ULP_HDR_BIT_O_ETH = 0x0000000000000001,
+ BNXT_ULP_HDR_BIT_O_IPV4 = 0x0000000000000002,
+ BNXT_ULP_HDR_BIT_O_IPV6 = 0x0000000000000004,
+ BNXT_ULP_HDR_BIT_O_TCP = 0x0000000000000008,
+ BNXT_ULP_HDR_BIT_O_UDP = 0x0000000000000010,
+ BNXT_ULP_HDR_BIT_T_VXLAN = 0x0000000000000020,
+ BNXT_ULP_HDR_BIT_T_GRE = 0x0000000000000040,
+ BNXT_ULP_HDR_BIT_I_ETH = 0x0000000000000080,
+ BNXT_ULP_HDR_BIT_I_IPV4 = 0x0000000000000100,
+ BNXT_ULP_HDR_BIT_I_IPV6 = 0x0000000000000200,
+ BNXT_ULP_HDR_BIT_I_TCP = 0x0000000000000400,
+ BNXT_ULP_HDR_BIT_I_UDP = 0x0000000000000800,
+ BNXT_ULP_HDR_BIT_LAST = 0x0000000000001000
+};
+
+enum bnxt_ulp_act_type {
+ BNXT_ULP_ACT_TYPE_NOT_SUPPORTED = 0,
+ BNXT_ULP_ACT_TYPE_SUPPORTED = 1,
+ BNXT_ULP_ACT_TYPE_END = 2,
+ BNXT_ULP_ACT_TYPE_LAST = 3
+};
+
+enum bnxt_ulp_byte_order {
+ BNXT_ULP_BYTE_ORDER_BE = 0,
+ BNXT_ULP_BYTE_ORDER_LE = 1,
+ BNXT_ULP_BYTE_ORDER_LAST = 2
+};
+
+enum bnxt_ulp_cf_idx {
+ BNXT_ULP_CF_IDX_MPLS_TAG_NUM = 0,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM = 1,
+ BNXT_ULP_CF_IDX_O_VTAG_PRESENT = 2,
+ BNXT_ULP_CF_IDX_O_TWO_VTAGS = 3,
+ BNXT_ULP_CF_IDX_I_VTAG_NUM = 4,
+ BNXT_ULP_CF_IDX_I_VTAG_PRESENT = 5,
+ BNXT_ULP_CF_IDX_I_TWO_VTAGS = 6,
+ BNXT_ULP_CF_IDX_INCOMING_IF = 7,
+ BNXT_ULP_CF_IDX_DIRECTION = 8,
+ BNXT_ULP_CF_IDX_SVIF_FLAG = 9,
+ BNXT_ULP_CF_IDX_O_L3 = 10,
+ BNXT_ULP_CF_IDX_I_L3 = 11,
+ BNXT_ULP_CF_IDX_O_L4 = 12,
+ BNXT_ULP_CF_IDX_I_L4 = 13,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID = 14,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF = 15,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SPIF = 16,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PARIF = 17,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC = 18,
+ BNXT_ULP_CF_IDX_DRV_FUNC_PHY_PORT = 19,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF = 20,
+ BNXT_ULP_CF_IDX_VF_FUNC_SPIF = 21,
+ BNXT_ULP_CF_IDX_VF_FUNC_PARIF = 22,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC = 23,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF = 24,
+ BNXT_ULP_CF_IDX_PHY_PORT_SPIF = 25,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF = 26,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT = 27,
+ BNXT_ULP_CF_IDX_LAST = 28
+};
+
+enum bnxt_ulp_critical_resource {
+ BNXT_ULP_CRITICAL_RESOURCE_NO = 0,
+ BNXT_ULP_CRITICAL_RESOURCE_YES = 1,
+ BNXT_ULP_CRITICAL_RESOURCE_LAST = 2
+};
+
+enum bnxt_ulp_device_id {
+ BNXT_ULP_DEVICE_ID_WH_PLUS = 0,
+ BNXT_ULP_DEVICE_ID_THOR = 1,
+ BNXT_ULP_DEVICE_ID_STINGRAY = 2,
+ BNXT_ULP_DEVICE_ID_STINGRAY2 = 3,
+ BNXT_ULP_DEVICE_ID_LAST = 4
+};
+
+enum bnxt_ulp_direction {
+ BNXT_ULP_DIRECTION_INGRESS = 0,
+ BNXT_ULP_DIRECTION_EGRESS = 1,
+ BNXT_ULP_DIRECTION_LAST = 2
+};
+
+enum bnxt_ulp_glb_regfile_index {
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID = 0,
+ BNXT_ULP_GLB_REGFILE_INDEX_LAST = 1
+};
+
+enum bnxt_ulp_hdr_type {
+ BNXT_ULP_HDR_TYPE_NOT_SUPPORTED = 0,
+ BNXT_ULP_HDR_TYPE_SUPPORTED = 1,
+ BNXT_ULP_HDR_TYPE_END = 2,
+ BNXT_ULP_HDR_TYPE_LAST = 3
+};
+
+enum bnxt_ulp_mark_enable {
+ BNXT_ULP_MARK_ENABLE_NO = 0,
+ BNXT_ULP_MARK_ENABLE_YES = 1,
+ BNXT_ULP_MARK_ENABLE_LAST = 2
+};
+
+enum bnxt_ulp_mask_opc {
+ BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
+ BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
+ BNXT_ULP_MASK_OPC_SET_TO_GLB_REGFILE = 3,
+ BNXT_ULP_MASK_OPC_ADD_PAD = 4,
+ BNXT_ULP_MASK_OPC_LAST = 5
+};
+
+enum bnxt_ulp_match_type {
+ BNXT_ULP_MATCH_TYPE_EM = 0,
+ BNXT_ULP_MATCH_TYPE_WC = 1,
+ BNXT_ULP_MATCH_TYPE_LAST = 2
+};
+
+enum bnxt_ulp_priority {
+ BNXT_ULP_PRIORITY_LEVEL_0 = 0,
+ BNXT_ULP_PRIORITY_LEVEL_1 = 1,
+ BNXT_ULP_PRIORITY_LEVEL_2 = 2,
+ BNXT_ULP_PRIORITY_LEVEL_3 = 3,
+ BNXT_ULP_PRIORITY_LEVEL_4 = 4,
+ BNXT_ULP_PRIORITY_LEVEL_5 = 5,
+ BNXT_ULP_PRIORITY_LEVEL_6 = 6,
+ BNXT_ULP_PRIORITY_LEVEL_7 = 7,
+ BNXT_ULP_PRIORITY_NOT_USED = 8,
+ BNXT_ULP_PRIORITY_LAST = 9
+};
+
+enum bnxt_ulp_regfile_index {
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID = 0,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 1,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 2,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 3,
+ BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 4,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 5,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 6,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 7,
+ BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 8,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR = 9,
+ BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 10,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 11,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 12,
+ BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 13,
+ BNXT_ULP_REGFILE_INDEX_NOT_USED = 14,
+ BNXT_ULP_REGFILE_INDEX_LAST = 15
+};
+
+enum bnxt_ulp_result_opc {
+ BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
+ BNXT_ULP_RESULT_OPC_SET_TO_ACT_BIT = 2,
+ BNXT_ULP_RESULT_OPC_SET_TO_ENCAP_ACT_PROP_SZ = 3,
+ BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 4,
+ BNXT_ULP_RESULT_OPC_SET_TO_GLB_REGFILE = 5,
+ BNXT_ULP_RESULT_OPC_SET_TO_COMP_FIELD = 6,
+ BNXT_ULP_RESULT_OPC_LAST = 7
+};
+
+enum bnxt_ulp_search_before_alloc {
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
+ BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
+};
+
+enum bnxt_ulp_spec_opc {
+ BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
+ BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
+ BNXT_ULP_SPEC_OPC_SET_TO_COMP_FIELD = 2,
+ BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 3,
+ BNXT_ULP_SPEC_OPC_SET_TO_GLB_REGFILE = 4,
+ BNXT_ULP_SPEC_OPC_ADD_PAD = 5,
+ BNXT_ULP_SPEC_OPC_LAST = 6
+};
+
+enum bnxt_ulp_vfr_flag {
+ BNXT_ULP_VFR_FLAG_NO = 0,
+ BNXT_ULP_VFR_FLAG_YES = 1,
+ BNXT_ULP_VFR_FLAG_LAST = 2
+};
+
+enum bnxt_ulp_fdb_resource_flags {
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
+};
+
+enum bnxt_ulp_fdb_type {
+ BNXT_ULP_FDB_TYPE_DEFAULT = 1,
+ BNXT_ULP_FDB_TYPE_REGULAR = 0
+};
+
+enum bnxt_ulp_flow_dir_bitmask {
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
+ BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
+};
+
+enum bnxt_ulp_match_type_bitmask {
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM = 0x0000000000000000,
+ BNXT_ULP_MATCH_TYPE_BITMASK_WM = 0x0000000000000001
+};
+
+enum bnxt_ulp_resource_func {
+ BNXT_ULP_RESOURCE_FUNC_INVALID = 0x00,
+ BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 0x20,
+ BNXT_ULP_RESOURCE_FUNC_RSVD1 = 0x40,
+ BNXT_ULP_RESOURCE_FUNC_RSVD2 = 0x60,
+ BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0x80,
+ BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 0x81,
+ BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE = 0x82,
+ BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 0x83,
+ BNXT_ULP_RESOURCE_FUNC_IF_TABLE = 0x84,
+ BNXT_ULP_RESOURCE_FUNC_HW_FID = 0x85
+};
+
+enum bnxt_ulp_resource_sub_type {
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_CNT_IDX = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_CNT_IDX = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_ACT_IDX = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
+};
+
+enum bnxt_ulp_sym {
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_AGG_ERROR_NO = 0,
+ BNXT_ULP_SYM_AGG_ERROR_YES = 1,
+ BNXT_ULP_SYM_BIG_ENDIAN = 0,
+ BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+ BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+ BNXT_ULP_SYM_ECV_VALID_NO = 0,
+ BNXT_ULP_SYM_ECV_VALID_YES = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
+ BNXT_ULP_SYM_HREC_NEXT_NO = 0,
+ BNXT_ULP_SYM_HREC_NEXT_YES = 1,
+ BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
+ BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
+ BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
+ BNXT_ULP_SYM_IP_PROTO_TCP = 6,
+ BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+ BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+ BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
+ BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
+ BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+ BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+ BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+ BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
+ BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
+ BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
+ BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
+ BNXT_ULP_SYM_NO = 0,
+ BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+ BNXT_ULP_SYM_POP_VLAN_NO = 0,
+ BNXT_ULP_SYM_POP_VLAN_YES = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
+ BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
+ BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
+ BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
+ BNXT_ULP_SYM_RESERVED_IGNORE = 0,
+ BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_YES = 1
+};
+
+enum bnxt_ulp_act_prop_sz {
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
+ BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
+ BNXT_ULP_ACT_PROP_SZ_PORT_ID = 4,
+ BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
+ BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
+ BNXT_ULP_ACT_PROP_SZ_MARK = 4,
+ BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
+ BNXT_ULP_ACT_PROP_SZ_METER = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
+ BNXT_ULP_ACT_PROP_SZ_LAST = 4
+};
+
+enum bnxt_ulp_act_prop_idx {
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
+ BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
+ BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
+ BNXT_ULP_ACT_PROP_IDX_PORT_ID = 32,
+ BNXT_ULP_ACT_PROP_IDX_VNIC = 36,
+ BNXT_ULP_ACT_PROP_IDX_VPORT = 40,
+ BNXT_ULP_ACT_PROP_IDX_MARK = 44,
+ BNXT_ULP_ACT_PROP_IDX_COUNT = 48,
+ BNXT_ULP_ACT_PROP_IDX_METER = 52,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 56,
+ BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 64,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 72,
+ BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 76,
+ BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 80,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 84,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 88,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 92,
+ BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 108,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 124,
+ BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 128,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 132,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 136,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 140,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 144,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 148,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 152,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 156,
+ BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 160,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 164,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 170,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 176,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 184,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 216,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 232,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 236,
+ BNXT_ULP_ACT_PROP_IDX_LAST = 268
+};
+
+enum bnxt_ulp_class_hid {
+ BNXT_ULP_CLASS_HID_0080 = 0x0080,
+ BNXT_ULP_CLASS_HID_0000 = 0x0000,
+ BNXT_ULP_CLASS_HID_0087 = 0x0087
+};
+
+enum bnxt_ulp_act_hid {
+ BNXT_ULP_ACT_HID_00a1 = 0x00a1,
+ BNXT_ULP_ACT_HID_0040 = 0x0040,
+ BNXT_ULP_ACT_HID_0029 = 0x0029
+};
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
new file mode 100644
index 0000000..84b9523
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef ULP_HDR_FIELD_ENUMS_H_
+#define ULP_HDR_FIELD_ENUMS_H_
+
+enum bnxt_ulp_hf0 {
+ BNXT_ULP_HF0_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF0_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF0_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF0_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF0_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF0_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF0_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF0_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF0_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF0_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF0_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF0_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF0_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF0_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF0_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF0_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf1 {
+ BNXT_ULP_HF1_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF1_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF1_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF1_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF1_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF1_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF1_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF1_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF1_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF1_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF1_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF1_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF1_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF1_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF1_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF1_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF1_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF1_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF1_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF1_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf2 {
+ BNXT_ULP_HF2_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF2_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF2_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF2_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF2_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF2_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF2_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF2_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF2_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF2_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF2_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF2_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF2_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF2_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF2_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF2_IDX_O_IPV4_NEXT_PID = 16,
+ BNXT_ULP_HF2_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF2_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF2_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF2_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF2_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF2_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF2_IDX_O_UDP_CSUM = 23,
+ BNXT_ULP_HF2_IDX_T_VXLAN_FLAGS = 24,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD0 = 25,
+ BNXT_ULP_HF2_IDX_T_VXLAN_VNI = 26,
+ BNXT_ULP_HF2_IDX_T_VXLAN_RSVD1 = 27,
+ BNXT_ULP_HF2_IDX_I_ETH_DMAC = 28,
+ BNXT_ULP_HF2_IDX_I_ETH_SMAC = 29,
+ BNXT_ULP_HF2_IDX_I_ETH_TYPE = 30,
+ BNXT_ULP_HF2_IDX_IO_VLAN_CFI_PRI = 31,
+ BNXT_ULP_HF2_IDX_IO_VLAN_VID = 32,
+ BNXT_ULP_HF2_IDX_IO_VLAN_TYPE = 33,
+ BNXT_ULP_HF2_IDX_II_VLAN_CFI_PRI = 34,
+ BNXT_ULP_HF2_IDX_II_VLAN_VID = 35,
+ BNXT_ULP_HF2_IDX_II_VLAN_TYPE = 36,
+ BNXT_ULP_HF2_IDX_I_IPV4_VER = 37,
+ BNXT_ULP_HF2_IDX_I_IPV4_TOS = 38,
+ BNXT_ULP_HF2_IDX_I_IPV4_LEN = 39,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_ID = 40,
+ BNXT_ULP_HF2_IDX_I_IPV4_FRAG_OFF = 41,
+ BNXT_ULP_HF2_IDX_I_IPV4_TTL = 42,
+ BNXT_ULP_HF2_IDX_I_IPV4_NEXT_PID = 43,
+ BNXT_ULP_HF2_IDX_I_IPV4_CSUM = 44,
+ BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR = 45,
+ BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR = 46,
+ BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT = 47,
+ BNXT_ULP_HF2_IDX_I_UDP_DST_PORT = 48,
+ BNXT_ULP_HF2_IDX_I_UDP_LENGTH = 49,
+ BNXT_ULP_HF2_IDX_I_UDP_CSUM = 50
+};
+
+enum bnxt_ulp_hf_bitmask0 {
+ BNXT_ULP_HF0_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF0_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask1 {
+ BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF1_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF1_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF1_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF1_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask2 {
+ BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF2_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF2_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF2_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF2_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF2_BITMASK_O_UDP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
+ BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_DMAC = 0x0000000800000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_SMAC = 0x0000000400000000,
+ BNXT_ULP_HF2_BITMASK_I_ETH_TYPE = 0x0000000200000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_VID = 0x0000000080000000,
+ BNXT_ULP_HF2_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_VID = 0x0000000010000000,
+ BNXT_ULP_HF2_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_VER = 0x0000000004000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TOS = 0x0000000002000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_LEN = 0x0000000001000000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_TTL = 0x0000000000200000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_NEXT_PID = 0x0000000000100000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
+ BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
+ BNXT_ULP_HF2_BITMASK_I_UDP_CSUM = 0x0000000000002000
+};
+
+#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
new file mode 100644
index 0000000..b49b0a1
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -0,0 +1,543 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_db_field.h"
+#include "ulp_template_struct.h"
+#include "ulp_rte_parser.h"
+
+uint32_t ulp_act_prop_map_table[] = {
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE,
+ [BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM] =
+ BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM,
+ [BNXT_ULP_ACT_PROP_IDX_PORT_ID] =
+ BNXT_ULP_ACT_PROP_SZ_PORT_ID,
+ [BNXT_ULP_ACT_PROP_IDX_VNIC] =
+ BNXT_ULP_ACT_PROP_SZ_VNIC,
+ [BNXT_ULP_ACT_PROP_IDX_VPORT] =
+ BNXT_ULP_ACT_PROP_SZ_VPORT,
+ [BNXT_ULP_ACT_PROP_IDX_MARK] =
+ BNXT_ULP_ACT_PROP_SZ_MARK,
+ [BNXT_ULP_ACT_PROP_IDX_COUNT] =
+ BNXT_ULP_ACT_PROP_SZ_COUNT,
+ [BNXT_ULP_ACT_PROP_IDX_METER] =
+ BNXT_ULP_ACT_PROP_SZ_METER,
+ [BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN,
+ [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP] =
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP,
+ [BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID] =
+ BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST,
+ [BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_SET_TP_DST] =
+ BNXT_ULP_ACT_PROP_SZ_SET_TP_DST,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6,
+ [BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7] =
+ BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP,
+ [BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] =
+ BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN,
+ [BNXT_ULP_ACT_PROP_IDX_LAST] =
+ BNXT_ULP_ACT_PROP_SZ_LAST
+};
+
+struct bnxt_ulp_rte_act_info ulp_act_info[] = {
+ [RTE_FLOW_ACTION_TYPE_END] = {
+ .act_type = BNXT_ULP_ACT_TYPE_END,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_VOID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_void_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PASSTHRU] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_JUMP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_MARK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_mark_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_FLAG] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_QUEUE] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DROP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_drop_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_COUNT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_count_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_RSS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_rss_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PF] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_pf_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_VF] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vf_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PHY_PORT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_phy_port_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_PORT_ID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_port_id_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_METER] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SECURITY] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_MPLS_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_DEC_MPLS_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_NW_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_DEC_NW_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_OUT] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_COPY_TTL_IN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_POP_VLAN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_POP_MPLS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_OF_PUSH_MPLS] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vxlan_encap_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_VXLAN_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
+ .proto_act_func = ulp_rte_vxlan_decap_act_handler
+ },
+ [RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_NVGRE_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_RAW_ENCAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_RAW_DECAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV4_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_IPV6_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TP_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TP_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_MAC_SWAP] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_TTL] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_MAC_SRC] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_SET_MAC_DST] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_INC_TCP_ACK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ },
+ [RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = {
+ .act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
+ .proto_act_func = NULL
+ }
+};
+
+struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_RX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
+ TF_DIR_TX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_RX] = {
+ .num_entries = 16384
+ },
+ [BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
+ TF_DIR_TX] = {
+ .num_entries = 16384
+ }
+};
+
+struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
+ [BNXT_ULP_DEVICE_ID_WH_PLUS] = {
+ .global_fid_enable = BNXT_ULP_SYM_YES,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_swap = 1,
+ .lfid_entries = 16384,
+ .lfid_entry_size = 4,
+ .gfid_entries = 65536,
+ .gfid_entry_size = 4,
+ .num_flows = 32768,
+ .num_resources_per_flow = 8
+ }
+};
+
+struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
+ [0] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
+ },
+ [1] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
+ }
+};
+
+struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
+ [RTE_FLOW_ITEM_TYPE_END] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_END,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VOID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_void_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_INVERT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ANY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PF] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_pf_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_VF] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vf_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_phy_port_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_PORT_ID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_port_id_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_RAW] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_eth_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_VLAN] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vlan_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV4] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ipv4_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV6] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_ipv6_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_UDP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_udp_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_TCP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_tcp_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_SCTP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VXLAN] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
+ .proto_hdr_func = ulp_rte_vxlan_hdr_handler
+ },
+ [RTE_FLOW_ITEM_TYPE_E_TAG] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_NVGRE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_MPLS] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GRE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_FUZZY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTPC] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTPU] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ESP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GENEVE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_VXLAN_GPE] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_IPV6_EXT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NS] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_NA] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_SLA_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_ICMP6_ND_OPT_TLA_ETH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_MARK] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_META] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GRE_KEY] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_GTP_PSC] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOES] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOED] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_PPPOE_PROTO_ID] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_NSH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_IGMP] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_AH] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ },
+ [RTE_FLOW_ITEM_TYPE_HIGIG2] = {
+ .hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
+ .proto_hdr_func = NULL
+ }
+};
+
+uint32_t bnxt_ulp_encap_vtag_map[] = {
+ [0] = BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP,
+ [1] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
+ [2] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI
+};
+
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 2f64bcb..13d9e88 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -7,7 +7,7 @@
#define _ULP_UTILS_H_
#include "bnxt.h"
-#include "ulp_template_db.h"
+#include "ulp_template_db_enum.h"
/*
* Macros for bitmap sets and gets
--
2.7.4
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2020-06-12 13:00 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-10 6:56 [dpdk-dev] [PATCH 00/36] bnxt fixes and enhancements Somnath Kotur
2020-06-10 6:56 ` [dpdk-dev] [PATCH 01/36] net/bnxt: Makefile changes Somnath Kotur
2020-06-10 6:56 ` [dpdk-dev] [PATCH 02/36] net/bnxt: remove svif and vlan information from header bitmap Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 03/36] net/bnxt: add vfr flag to the mark manager Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 04/36] net/bnxt: support for mark action for LFID rules Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 05/36] net/bnxt: remove mem field from mapper class table Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 06/36] net/bnxt: support more resource functions in flow database Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 07/36] net/bnxt: rename the ulp action bitmap enumeration values Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 08/36] net/bnxt: add support for computed header field in result opcode Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 09/36] net/bnxt: updated compute field list and access macros Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 10/36] net/bnxt: extend default identifier list to be global resource list Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 11/36] net/bnxt: add resource sub type to class and action tables Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 12/36] net/bnxt: remove cache tbl id from the mapper class table Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 13/36] net/bnxt: move vfr flag from computed field list to " Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 14/36] net/bnxt: add support for action bitmap opcode in result field processing Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 15/36] net/bnxt: direction bit needs to be added to the action bitmap Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 16/36] net/bnxt: remove cache_tbl_id enums Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 17/36] net/bnxt: extend index table processing to process action templates Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 18/36] net/bnxt: use vport in the phy port act handler Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 19/36] net/bnxt: add enum to the critical resource Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 20/36] net/bnxt: rename regfile_wr_idx to regfile_idx Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 21/36] net/bnxt: remove unused enum in regfile index Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 22/36] net/bnxt: rename an enum in the " Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 23/36] net/bnxt: rename the enums in the bnxt_ulp_resource_sub_type Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 24/36] net/bnxt: add a devarg to set max flow count Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 25/36] net/bnxt: add support for vxlan encap and decap templates Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 26/36] net/bnxt: flow db api to get vf rep action record Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 27/36] net/bnxt: parse ipv6 vtc_flow field for more granularly Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 28/36] net/bnxt: remove the implicit bitset update for vnic action Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 30/36] net/bnxt: unify the mapper opcodes into single enum Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 31/36] net/bnxt: change opcode for adding pad to setting zero for common usage Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 32/36] net/bnxt: optimized key/mask/result fields to use set to zero opcode Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 33/36] net/bnxt: add support for internal exact match flows Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 34/36] net/bnxt: enable vfr flag processing with mark db opcode Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 35/36] net/bnxt: rename fields in the device params structure Somnath Kotur
2020-06-10 6:57 ` [dpdk-dev] [PATCH 36/36] net/bnxt: update ulp template database for new opcodes Somnath Kotur
2020-06-10 11:43 [dpdk-dev] [PATCH 00/36] bnxt patches Somnath Kotur
2020-06-10 11:44 ` [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules Somnath Kotur
2020-06-12 12:49 [dpdk-dev] [PATCH v3 00/36] bnxt patches Somnath Kotur
2020-06-12 12:50 ` [dpdk-dev] [PATCH 29/36] net/bnxt: divide the ulp template db file to smaller modules Somnath Kotur
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