From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 73F58A00C5; Thu, 11 Jun 2020 10:40:22 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0913B1BE9B; Thu, 11 Jun 2020 10:39:45 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 31D851BE8E for ; Thu, 11 Jun 2020 10:39:43 +0200 (CEST) IronPort-SDR: 0WWWaHB4uat/sIAkyrtLs0iBukpkeiozYSpa4gXz9QT7uvIimHf3yvbNQfs7JU11DfttBMh5Gb j3DpDF6E/guA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2020 01:39:43 -0700 IronPort-SDR: 4vSYXS3PkgY0RMPWNsZnTtYt85yPkxknZlfOYp0YJzsdkBkCNR9BdyiRBFtYiyNaRCx4DizxTM lGU1CXiS0M2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,499,1583222400"; d="scan'208";a="419039172" Received: from dpdk51.sh.intel.com ([10.67.111.82]) by orsmga004.jf.intel.com with ESMTP; 11 Jun 2020 01:39:41 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Nick Nunley , Paul M Stillwell Jr Date: Thu, 11 Jun 2020 16:43:25 +0800 Message-Id: <20200611084330.18301-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200611084330.18301-1-qi.z.zhang@intel.com> References: <20200611084330.18301-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 05/10] net/ice/base: rename misleading variable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The grst_delay variable in ice_check_reset contains the maximum time (in 100 msec units) that the driver will wait for a reset event to transition to the Device Active state. The value is the sum of three separate components: 1) The maximum time it may take for the firmware to process its outstanding command before handling the reset request. 2) The value in RSTCTL.GRSTDEL (the delay firmware inserts between first seeing the driver reset request and the actual hardware assertion). 3) The maximum expected reset processing time in hardware. Referring to this total time as "grst_delay" is misleading and potentially confusing to someone checking the code and cross-referencing the hardware specification. Fix this by renaming the variable to "grst_timeout", which is more descriptive of its actual use. Signed-off-by: Nick Nunley Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 85b6e1a37..1683daf28 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -882,23 +882,23 @@ void ice_deinit_hw(struct ice_hw *hw) */ enum ice_status ice_check_reset(struct ice_hw *hw) { - u32 cnt, reg = 0, grst_delay, uld_mask; + u32 cnt, reg = 0, grst_timeout, uld_mask; /* Poll for Device Active state in case a recent CORER, GLOBR, * or EMPR has occurred. The grst delay value is in 100ms units. * Add 1sec for outstanding AQ commands that can take a long time. */ - grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> - GLGEN_RSTCTL_GRSTDEL_S) + 10; + grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> + GLGEN_RSTCTL_GRSTDEL_S) + 10; - for (cnt = 0; cnt < grst_delay; cnt++) { + for (cnt = 0; cnt < grst_timeout; cnt++) { ice_msec_delay(100, true); reg = rd32(hw, GLGEN_RSTAT); if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) break; } - if (cnt == grst_delay) { + if (cnt == grst_timeout) { ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); return ICE_ERR_RESET_FAILED; -- 2.13.6