From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CDA9A0093; Mon, 15 Jun 2020 04:01:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1F22CAAB7; Mon, 15 Jun 2020 04:01:26 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id EEA6D5323 for ; Mon, 15 Jun 2020 04:01:21 +0200 (CEST) IronPort-SDR: 15DBHpYN5jmhYTYB2MJYiPl65VoRfPDqDv19i1irvPMp9FSc1gV90yXtFo/ptwVFv11LDWOelh SYZIkOT7M0uw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jun 2020 19:01:21 -0700 IronPort-SDR: 4S4JrFSq9VBTog29nNrjaucJIlkyR+NVRa1GOkxW3x5vwzrmRGHtuiXgd/q9FRF9e0m+vOj8DY Y3zp+LM8sxuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,513,1583222400"; d="scan'208";a="298318795" Received: from dpdk51.sh.intel.com ([10.67.111.82]) by fmsmga004.fm.intel.com with ESMTP; 14 Jun 2020 19:01:19 -0700 From: Qi Zhang To: ferruh.yigit@intel.com Cc: xiaolong.ye@intel.com, qiming.yang@intel.com, dev@dpdk.org, Qi Zhang , Yahui Cao , "Paul M . Stillwell Jr" Date: Mon, 15 Jun 2020 10:04:24 +0800 Message-Id: <20200615020515.1359-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200615020515.1359-1-qi.z.zhang@intel.com> References: <20200603024016.30636-1-qi.z.zhang@intel.com> <20200615020515.1359-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 02/53] net/ice/base: add FDIR program status WB macro X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add descriptor field offset and mask definition. It is used to parse FDIR rx descriptor field value. Signed-off-by: Yahui Cao Signed-off-by: Paul M. Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_lan_tx_rx.h | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index a0e284a8d..99edcc8ae 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -175,6 +175,50 @@ struct ice_fltr_desc { (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S) #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL +/* definition for FD filter programming status descriptor WB format */ +#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S 28 +#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_M \ + (0xFULL << ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S) + +#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S 32 +#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_M \ + (0xFFFFFFFFULL << ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S) + +#define ICE_FXD_FLTR_WB_QW1_DD_S 0 +#define ICE_FXD_FLTR_WB_QW1_DD_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S) +#define ICE_FXD_FLTR_WB_QW1_DD_YES 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S 1 +#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M \ + (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S) +#define ICE_FXD_FLTR_WB_QW1_PROG_ADD 0x0ULL +#define ICE_FXD_FLTR_WB_QW1_PROG_DEL 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_FAIL_S 4 +#define ICE_FXD_FLTR_WB_QW1_FAIL_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S) +#define ICE_FXD_FLTR_WB_QW1_FAIL_YES 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S 5 +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \ + (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S) +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES 0x1ULL + +#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S 8 +#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_M \ + (0x3FFFULL << ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S) + +#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_S 28 +#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_M \ + (0x7FULL << ICE_FXD_FLTR_WB_QW1_PKT_PROF_S) + +#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S 38 +#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_M \ + (0x3FFFFFF << ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S) + +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \ + (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S) +#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES 0x1ULL + enum ice_rx_desc_status_bits { /* Note: These are predefined bit offsets */ ICE_RX_DESC_STATUS_DD_S = 0, -- 2.13.6