From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C7BCA0350; Mon, 22 Jun 2020 09:17:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 372F61D62E; Mon, 22 Jun 2020 09:07:30 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 0F1D61D627 for ; Mon, 22 Jun 2020 09:07:26 +0200 (CEST) IronPort-SDR: vRzlCM/mBjp5+WSgbvHTYfJMncnTe77+FbBCeo7wwYBlkMNlGpMFfPF7OFLv3G66NwNv2gD3Ik 3wsanZG32R6A== X-IronPort-AV: E=McAfee;i="6000,8403,9659"; a="131070905" X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="131070905" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2020 00:07:26 -0700 IronPort-SDR: f9sCOtNCfapQ1Y2nBt8aJbsgWeqG7EyXoJzlxSCflNCUfttjIAjcC2Z0/BpzQHmjjWSN4Dp9Yu MVnGrZ55Q5hA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="384409308" Received: from dpdk.sh.intel.com ([10.239.255.83]) by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:07:24 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Zhao1 Wei , Guinan Sun Date: Mon, 22 Jun 2020 06:46:31 +0000 Message-Id: <20200622064634.70941-68-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200622064634.70941-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 67/70] net/e1000/base: remove conditional compilation wrapper X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove conditional compilation statements. Signed-off-by: Guinan Sun --- drivers/net/e1000/base/e1000_defines.h | 13 +-- drivers/net/e1000/base/e1000_hw.h | 4 - drivers/net/e1000/base/e1000_i210.c | 2 +- drivers/net/e1000/base/e1000_i225.c | 1 - drivers/net/e1000/base/e1000_ich8lan.c | 19 ---- drivers/net/e1000/base/e1000_ich8lan.h | 17 +--- drivers/net/e1000/base/e1000_mac.c | 132 ------------------------- drivers/net/e1000/base/e1000_mac.h | 2 - drivers/net/e1000/base/e1000_nvm.c | 2 - drivers/net/e1000/base/e1000_phy.h | 2 - drivers/net/e1000/base/e1000_regs.h | 5 - 11 files changed, 5 insertions(+), 194 deletions(-) diff --git a/drivers/net/e1000/base/e1000_defines.h b/drivers/net/e1000/base/e1000_defines.h index 75f983817..4a1d230c3 100644 --- a/drivers/net/e1000/base/e1000_defines.h +++ b/drivers/net/e1000/base/e1000_defines.h @@ -147,9 +147,7 @@ E1000_RXDEXT_STATERR_CXE | \ E1000_RXDEXT_STATERR_RXE) -#if !defined(EXTERNAL_RELEASE) || defined(E1000E_MQ) #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 -#endif /* !EXTERNAL_RELEASE || E1000E_MQ */ #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 @@ -1129,9 +1127,7 @@ /* NVM Addressing bits based on type 0=small, 1=large */ #define E1000_EECD_ADDR_BITS 0x00000400 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ -#ifndef E1000_NVM_GRANT_ATTEMPTS #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ -#endif #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ #define E1000_EECD_SIZE_EX_SHIFT 11 @@ -1347,9 +1343,7 @@ #define PCIE_LINK_SPEED_5000 0x02 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 -#ifndef ETH_ADDR_LEN #define ETH_ADDR_LEN 6 -#endif #define PHY_REVISION_MASK 0xFFFFFFF0 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ @@ -1606,7 +1600,6 @@ #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ -#ifndef NO_I225_SUPPORT #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ #define E1000_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */ @@ -1641,7 +1634,7 @@ #define E1000_INVM_DEFAULT_AL 0x202F #define E1000_INVM_AUTOLOAD 0x0A #define E1000_INVM_PLL_WO_VAL 0x0010 -#endif /* NO_I225_SUPPORT */ + /* Proxy Filter Control Extended */ #define E1000_PROXYFCEX_MDNS 0x00000001 /* mDNS */ #define E1000_PROXYFCEX_MDNS_M 0x00000002 /* mDNS Multicast */ @@ -1682,10 +1675,6 @@ #define E1000_STATUS_LAN_ID_OFFSET 2 #define E1000_VFTA_ENTRIES 128 -#ifndef E1000_UNUSEDARG #define E1000_UNUSEDARG -#endif /* E1000_UNUSEDARG */ -#ifndef ERROR_REPORT #define ERROR_REPORT(fmt) do { } while (0) -#endif /* ERROR_REPORT */ #endif /* _E1000_DEFINES_H_ */ diff --git a/drivers/net/e1000/base/e1000_hw.h b/drivers/net/e1000/base/e1000_hw.h index cf6b55172..210c7da16 100644 --- a/drivers/net/e1000/base/e1000_hw.h +++ b/drivers/net/e1000/base/e1000_hw.h @@ -963,7 +963,6 @@ struct e1000_shadow_ram { #define E1000_SHADOW_RAM_WORDS 2048 -#ifdef ULP_SUPPORT /* I218 PHY Ultra Low Power (ULP) states */ enum e1000_ulp_state { e1000_ulp_state_unknown, @@ -971,7 +970,6 @@ enum e1000_ulp_state { e1000_ulp_state_on, }; -#endif /* ULP_SUPPORT */ struct e1000_dev_spec_ich8lan { bool kmrn_lock_loss_workaround_enabled; struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; @@ -981,12 +979,10 @@ struct e1000_dev_spec_ich8lan { bool disable_k1_off; bool eee_disable; u16 eee_lp_ability; -#ifdef ULP_SUPPORT enum e1000_ulp_state ulp_state; bool ulp_capability_disabled; bool during_suspend_flow; bool during_dpg_exit; -#endif /* ULP_SUPPORT */ u16 lat_enc; u16 max_ltr_enc; bool smbus_disable; diff --git a/drivers/net/e1000/base/e1000_i210.c b/drivers/net/e1000/base/e1000_i210.c index 8dadde8ca..d32b0f089 100644 --- a/drivers/net/e1000/base/e1000_i210.c +++ b/drivers/net/e1000/base/e1000_i210.c @@ -310,7 +310,7 @@ STATIC s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, } for (i = 0; i < words; i++) { - eewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | + eewr = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) | (data[i] << E1000_NVM_RW_REG_DATA) | E1000_NVM_RW_REG_START; diff --git a/drivers/net/e1000/base/e1000_i225.c b/drivers/net/e1000/base/e1000_i225.c index 85f0a72b1..628695760 100644 --- a/drivers/net/e1000/base/e1000_i225.c +++ b/drivers/net/e1000/base/e1000_i225.c @@ -1137,7 +1137,6 @@ s32 e1000_set_d3_lplu_state_i225(struct e1000_hw *hw, bool active) return E1000_SUCCESS; } - /** * e1000_set_eee_i225 - Enable/disable EEE support * @hw: pointer to the HW structure diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c index 61dcc1e61..bf77bfa1d 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.c +++ b/drivers/net/e1000/base/e1000_ich8lan.c @@ -51,11 +51,9 @@ STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); -#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count); -#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */ STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); @@ -297,13 +295,11 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) */ e1000_gate_hw_phy_config_ich8lan(hw, true); -#ifdef ULP_SUPPORT /* It is not possible to be certain of the current state of ULP * so forcibly disable it. */ hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; -#endif /* ULP_SUPPORT */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) { DEBUGOUT("Failed to initialize PHY flow\n"); @@ -701,9 +697,7 @@ STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; -#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) u16 pci_cfg; -#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */ DEBUGFUNC("e1000_init_mac_params_ich8lan"); @@ -780,7 +774,6 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) e1000_update_mc_addr_list_pch2lan; /* fall-through */ case e1000_pchlan: -#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) /* save PCH revision_id */ e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg); /* SPT uses full byte for revision ID, @@ -790,7 +783,6 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) hw->revision_id = (u8)(pci_cfg &= 0x00FF); else hw->revision_id = (u8)(pci_cfg &= 0x000F); -#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */ /* check management mode */ mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; /* ID LED init */ @@ -1074,7 +1066,6 @@ STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) return ret_val; } -#ifdef ULP_SUPPORT /** * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP * @hw: pointer to the HW structure @@ -1453,7 +1444,6 @@ s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) return ret_val; } -#endif /* ULP_SUPPORT */ /** @@ -2080,7 +2070,6 @@ STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) return -E1000_ERR_CONFIG; } -#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT /** * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses * @hw: pointer to the HW structure @@ -2125,7 +2114,6 @@ STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, hw->phy.ops.release(hw); } -#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */ /** * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked * @hw: pointer to the HW structure @@ -2677,7 +2665,6 @@ void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) hw->phy.ops.release(hw); } -#ifndef CRC32_OS_SUPPORT STATIC u32 e1000_calc_rx_da_crc(u8 mac[]) { u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ @@ -2696,7 +2683,6 @@ STATIC u32 e1000_calc_rx_da_crc(u8 mac[]) return ~crc; } -#endif /* CRC32_OS_SUPPORT */ /** * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation * with 82579 PHY @@ -2741,13 +2727,8 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) mac_addr[4] = (addr_high & 0xFF); mac_addr[5] = ((addr_high >> 8) & 0xFF); -#ifndef CRC32_OS_SUPPORT E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), e1000_calc_rx_da_crc(mac_addr)); -#else /* CRC32_OS_SUPPORT */ - E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), - E1000_CRC32(ETH_ADDR_LEN, mac_addr)); -#endif /* CRC32_OS_SUPPORT */ } /* Write Rx addresses to the PHY */ diff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h index 0fe0b71a4..5e89f4442 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.h +++ b/drivers/net/e1000/base/e1000_ich8lan.h @@ -40,22 +40,16 @@ #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 #define E1000_FWSM_WLOCK_MAC_SHIFT 7 -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ /* Shared Receive Address Registers */ #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_H2ME 0x05B50 /* Host to ME */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */ #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_OFF1_ON2 << 4) | \ @@ -68,11 +62,9 @@ #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) /* FEXT register bit definition */ #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004 -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ #define E1000_FEXTNVM_SW_CONFIG 1 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ @@ -172,7 +164,6 @@ #define CV_SMB_CTRL PHY_REG(769, 23) #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) /* I218 Ultra Low Power Configuration 1 Register */ #define I218_ULP_CONFIG1 PHY_REG(779, 16) #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ @@ -187,7 +178,7 @@ #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ + /* SMBus Address Phy Register */ #define HV_SMB_ADDR PHY_REG(768, 26) #define HV_SMB_ADDR_MASK 0x007F @@ -285,10 +276,10 @@ /* Receive Address Initial CRC Calculation */ #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) + #define E1000_PCI_VENDOR_ID_REGISTER 0x00 -#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) + #define E1000_PCI_REVISION_ID_REG 0x08 -#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */ void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, bool state); void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); @@ -302,9 +293,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); s32 e1000_set_eee_pchlan(struct e1000_hw *hw); -#ifdef ULP_SUPPORT s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); -#endif /* ULP_SUPPORT */ #endif /* _E1000_ICH8LAN_H_ */ void e1000_demote_ltr(struct e1000_hw *hw, bool demote, bool link); diff --git a/drivers/net/e1000/base/e1000_mac.c b/drivers/net/e1000/base/e1000_mac.c index 577ba9c1b..4b67acea3 100644 --- a/drivers/net/e1000/base/e1000_mac.c +++ b/drivers/net/e1000/base/e1000_mac.c @@ -1276,7 +1276,6 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; s32 ret_val = E1000_SUCCESS; - u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; u16 speed, duplex; @@ -1287,10 +1286,6 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) * configuration of the MAC to match the "fc" parameter. */ if (mac->autoneg_failed) { - if (hw->phy.media_type == e1000_media_type_fiber || - hw->phy.media_type == e1000_media_type_internal_serdes) - ret_val = e1000_force_mac_fc_generic(hw); - } else { if (hw->phy.media_type == e1000_media_type_copper) ret_val = e1000_force_mac_fc_generic(hw); } @@ -1444,130 +1439,6 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) } } - /* Check for the case where we have SerDes media and auto-neg is - * enabled. In this case, we need to check and see if Auto-Neg - * has completed, and if so, how the PHY and link partner has - * flow control configured. - */ - if ((hw->phy.media_type == e1000_media_type_internal_serdes) && - mac->autoneg) { - /* Read the PCS_LSTS and check to see if AutoNeg - * has completed. - */ - pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); - - if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { - DEBUGOUT("PCS Auto Neg has not completed.\n"); - return ret_val; - } - - /* The AutoNeg process has completed, so we now need to - * read both the Auto Negotiation Advertisement - * Register (PCS_ANADV) and the Auto_Negotiation Base - * Page Ability Register (PCS_LPAB) to determine how - * flow control was negotiated. - */ - pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); - pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); - - /* Two bits in the Auto Negotiation Advertisement Register - * (PCS_ANADV) and two bits in the Auto Negotiation Base - * Page Ability Register (PCS_LPAB) determine flow control - * for both the PHY and the link partner. The following - * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, - * 1999, describes these PAUSE resolution bits and how flow - * control is determined based upon these settings. - * NOTE: DC = Don't Care - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution - *-------|---------|-------|---------|-------------------- - * 0 | 0 | DC | DC | e1000_fc_none - * 0 | 1 | 0 | DC | e1000_fc_none - * 0 | 1 | 1 | 0 | e1000_fc_none - * 0 | 1 | 1 | 1 | e1000_fc_tx_pause - * 1 | 0 | 0 | DC | e1000_fc_none - * 1 | DC | 1 | DC | e1000_fc_full - * 1 | 1 | 0 | 0 | e1000_fc_none - * 1 | 1 | 0 | 1 | e1000_fc_rx_pause - * - * Are both PAUSE bits set to 1? If so, this implies - * Symmetric Flow Control is enabled at both ends. The - * ASM_DIR bits are irrelevant per the spec. - * - * For Symmetric Flow Control: - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result - *-------|---------|-------|---------|-------------------- - * 1 | DC | 1 | DC | e1000_fc_full - * - */ - if ((pcs_adv_reg & E1000_TXCW_PAUSE) && - (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { - /* Now we need to check if the user selected Rx ONLY - * of pause frames. In this case, we had to advertise - * FULL flow control because we could not advertise Rx - * ONLY. Hence, we must now check to see if we need to - * turn OFF the TRANSMISSION of PAUSE frames. - */ - if (hw->fc.requested_mode == e1000_fc_full) { - hw->fc.current_mode = e1000_fc_full; - DEBUGOUT("Flow Control = FULL.\n"); - } else { - hw->fc.current_mode = e1000_fc_rx_pause; - DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); - } - } - /* For receiving PAUSE frames ONLY. - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result - *-------|---------|-------|---------|-------------------- - * 0 | 1 | 1 | 1 | e1000_fc_tx_pause - */ - else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && - (pcs_adv_reg & E1000_TXCW_ASM_DIR) && - (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && - (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { - hw->fc.current_mode = e1000_fc_tx_pause; - DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); - } - /* For transmitting PAUSE frames ONLY. - * - * LOCAL DEVICE | LINK PARTNER - * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result - *-------|---------|-------|---------|-------------------- - * 1 | 1 | 0 | 1 | e1000_fc_rx_pause - */ - else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && - (pcs_adv_reg & E1000_TXCW_ASM_DIR) && - !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && - (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { - hw->fc.current_mode = e1000_fc_rx_pause; - DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); - } else { - /* Per the IEEE spec, at this point flow control - * should be disabled. - */ - hw->fc.current_mode = e1000_fc_none; - DEBUGOUT("Flow Control = NONE.\n"); - } - - /* Now we call a subroutine to actually force the MAC - * controller to use the correct flow control settings. - */ - pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); - pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; - E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); - - ret_val = e1000_force_mac_fc_generic(hw); - if (ret_val) { - DEBUGOUT("Error forcing flow control settings\n"); - return ret_val; - } - } - return E1000_SUCCESS; } @@ -2024,9 +1895,6 @@ s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) DEBUGFUNC("e1000_disable_pcie_master_generic"); - if (hw->bus.type != e1000_bus_type_pci_express) - return E1000_SUCCESS; - ctrl = E1000_READ_REG(hw, E1000_CTRL); ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; E1000_WRITE_REG(hw, E1000_CTRL, ctrl); diff --git a/drivers/net/e1000/base/e1000_mac.h b/drivers/net/e1000/base/e1000_mac.h index 35a691f63..8a4f1635b 100644 --- a/drivers/net/e1000/base/e1000_mac.h +++ b/drivers/net/e1000/base/e1000_mac.h @@ -6,9 +6,7 @@ #define _E1000_MAC_H_ void e1000_init_mac_ops_generic(struct e1000_hw *hw); -#ifndef E1000_REMOVED #define E1000_REMOVED(a) (0) -#endif /* E1000_REMOVED */ void e1000_null_mac_generic(struct e1000_hw *hw); s32 e1000_null_ops_generic(struct e1000_hw *hw); s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d); diff --git a/drivers/net/e1000/base/e1000_nvm.c b/drivers/net/e1000/base/e1000_nvm.c index 93d10ebb3..6aa432834 100644 --- a/drivers/net/e1000/base/e1000_nvm.c +++ b/drivers/net/e1000/base/e1000_nvm.c @@ -1295,9 +1295,7 @@ void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) return; } /* fall through */ -#ifndef NO_I225_SUPPORT case e1000_i225: -#endif /* NO_I225_SUPPORT */ case e1000_i350: hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); /* find combo image version */ diff --git a/drivers/net/e1000/base/e1000_phy.h b/drivers/net/e1000/base/e1000_phy.h index 3321bc0ba..a6f3d1021 100644 --- a/drivers/net/e1000/base/e1000_phy.h +++ b/drivers/net/e1000/base/e1000_phy.h @@ -122,8 +122,6 @@ s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, #define GS40G_MAC_SPEED_1G 0X0006 #define GS40G_COPPER_SPEC 0x0010 -#endif /* NO_I210_SUPPORT */ -#ifndef NO_I225_SUPPORT #define E1000_I225_PHPM 0x0E14 /* I225 PHY Power Management */ #define E1000_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */ #define E1000_I225_PHPM_LINK_ENERGY 0x0010 /* Link Energy Detect */ diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h index b0f9ff487..e374083e5 100644 --- a/drivers/net/e1000/base/e1000_regs.h +++ b/drivers/net/e1000/base/e1000_regs.h @@ -93,14 +93,10 @@ #define E1000_IOSFPC 0x00F28 /* TX corrupted data */ #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ #define E1000_EEMNGCTL_I210 0x01010 /* i210 MNG EEprom Mode Control */ -#ifndef NO_I225_SUPPORT #define E1000_EEMNGCTL_I225 0x01010 /* i225 MNG EEprom Mode Control */ -#endif /* NO_I225_SUPPORT */ #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ #define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */ -#ifndef NO_I225_SUPPORT #define E1000_EEARBC_I225 0x12024 /* EEPROM Auto Read Bus Control */ -#endif /* NO_I225_SUPPORT */ #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ #define E1000_FLSWCTL 0x01030 /* FLASH control register */ #define E1000_FLSWDATA 0x01034 /* FLASH data register */ @@ -215,7 +211,6 @@ #define E1000_MMDAC 13 /* MMD Access Control */ #define E1000_MMDAAD 14 /* MMD Access Address/Data */ - /* Convenience macros * * Note: "_n" is the queue number of the register to be written to. -- 2.17.1