From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A6D29A0350; Tue, 23 Jun 2020 13:19:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 624A31D62F; Tue, 23 Jun 2020 13:19:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 9BFBE1D649 for ; Tue, 23 Jun 2020 13:19:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 05NBFwgS030173; Tue, 23 Jun 2020 04:19:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=xBJs5+234e4i1NGFuOORx/rLeJeToAl/lE1SWHXlyfw=; b=httNt6QsDvqpXVre3XydLRjQ4Z2FVMdRW+EtbKiFpOQmc4yW+dBAXtxI9xS29VmKI5ag XVHyjZBvUuCij20sApdBDYS9vf6Cx0QkhUduJbUVgmYJkYPKAqsF1tR3kw3z1GFp1Pbi 6lXu9MF7Vn9jfcPdnSq7q1s9LM/d+URW0mc/JmyGmpny9HH5y5Umcgxx5PEmkmekfFQK cb44VuKbG+OS3X/nBB0UDkqQCCn/uxwZXWQcfhslT+Kj9uaJgGUigfIzbXaLN2pH7xce 0gvnaJVg5a1sY/mbrTiRUQ8hNcIxsbjIQdzlymcjjHXXQ3VYxBgN4SNt2W9r/z909/WF Og== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 31shynw00v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 23 Jun 2020 04:19:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Jun 2020 04:19:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Jun 2020 04:19:11 -0700 Received: from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 105F03F703F; Tue, 23 Jun 2020 04:19:08 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal , Radu Nicolau CC: Tejasree Kondoj , Narayana Prasad , Anoob Joseph , Vamsi Attunuru , Date: Tue, 23 Jun 2020 17:42:23 +0530 Message-ID: <20200623121228.10355-4-ktejasree@marvell.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623121228.10355-1-ktejasree@marvell.com> References: <20200623121228.10355-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.687 definitions=2020-06-23_06:2020-06-23, 2020-06-23 signatures=0 Subject: [dpdk-dev] [PATCH 3/8] crypto/octeontx2: add cryptodev sec registration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Vamsi Attunuru Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx2/Makefile | 1 + drivers/crypto/octeontx2/meson.build | 3 +- drivers/crypto/octeontx2/otx2_cryptodev.c | 12 ++++- drivers/crypto/octeontx2/otx2_cryptodev_sec.c | 46 +++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev_sec.h | 8 +++- 5 files changed, 67 insertions(+), 3 deletions(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_sec.c diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile index 5f9a6a0e3f..14152c6117 100644 --- a/drivers/crypto/octeontx2/Makefile +++ b/drivers/crypto/octeontx2/Makefile @@ -38,6 +38,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_capabilities.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_sec.c # export include files SYMLINK-y-include += diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index a28c700b9f..2bea53c47b 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -16,7 +16,8 @@ sources = files('otx2_cryptodev.c', 'otx2_cryptodev_capabilities.c', 'otx2_cryptodev_hw_access.c', 'otx2_cryptodev_mbox.c', - 'otx2_cryptodev_ops.c') + 'otx2_cryptodev_ops.c', + 'otx2_cryptodev_sec.c') extra_flags = [] # This integrated controller runs only on a arm64 machine, remove 32bit warnings diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index 77aa315dc0..f11773f107 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -17,6 +17,7 @@ #include "otx2_cryptodev_capabilities.h" #include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" +#include "otx2_cryptodev_sec.h" #include "otx2_dev.h" /* CPT common headers */ @@ -103,6 +104,11 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, goto otx2_dev_fini; } + /* Create security ctx */ + ret = otx2_crypto_sec_ctx_create(dev); + if (ret < 0) + goto otx2_dev_fini; + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | @@ -112,7 +118,8 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT | RTE_CRYPTODEV_FF_NON_BYTE_ALIGNED_DATA | - RTE_CRYPTODEV_FF_SYM_SESSIONLESS; + RTE_CRYPTODEV_FF_SYM_SESSIONLESS | + RTE_CRYPTODEV_FF_SECURITY; return 0; @@ -141,6 +148,9 @@ otx2_cpt_pci_remove(struct rte_pci_device *pci_dev) if (dev == NULL) return -ENODEV; + /* Destroy security ctx */ + otx2_crypto_sec_ctx_destroy(dev); + return rte_cryptodev_pmd_destroy(dev); } diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_sec.c b/drivers/crypto/octeontx2/otx2_cryptodev_sec.c new file mode 100644 index 0000000000..d937e6f37a --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_sec.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include +#include +#include + +#include "otx2_cryptodev_sec.h" + +static struct rte_security_ops otx2_crypto_sec_ops = { + .session_create = NULL, + .session_destroy = NULL, + .session_get_size = NULL, + .set_pkt_metadata = NULL, + .get_userdata = NULL, + .capabilities_get = NULL +}; + +int +otx2_crypto_sec_ctx_create(struct rte_cryptodev *cdev) +{ + struct rte_security_ctx *ctx; + + ctx = rte_malloc("otx2_cpt_dev_sec_ctx", + sizeof(struct rte_security_ctx), 0); + + if (ctx == NULL) + return -ENOMEM; + + /* Populate ctx */ + ctx->device = cdev; + ctx->ops = &otx2_crypto_sec_ops; + ctx->sess_cnt = 0; + + cdev->security_ctx = ctx; + + return 0; +} + +void +otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *cdev) +{ + rte_free(cdev->security_ctx); +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_sec.h b/drivers/crypto/octeontx2/otx2_cryptodev_sec.h index af62207d07..209baf35f4 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_sec.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_sec.h @@ -5,6 +5,8 @@ #ifndef __OTX2_CRYPTODEV_SEC_H__ #define __OTX2_CRYPTODEV_SEC_H__ +#include + #include "otx2_ipsec_po.h" struct otx2_sec_session_ipsec_lp { @@ -49,4 +51,8 @@ struct otx2_sec_session_ipsec_lp { uint8_t auth_iv_length; }; -#endif /* __OTX2_CRYPTODEV_SEC_H__ */ +int otx2_crypto_sec_ctx_create(struct rte_cryptodev *crypto_dev); + +void otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *crypto_dev); + +#endif /* __OTX2_CRYPTODEEV_SEC_H__ */ -- 2.27.0