From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3312EA0540; Wed, 15 Jul 2020 10:33:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C37E71C0D7; Wed, 15 Jul 2020 10:33:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 0E7591C0D6 for ; Wed, 15 Jul 2020 10:33:43 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06F8UMgB028877; Wed, 15 Jul 2020 01:33:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=wAogfNgD83m6IeEyNXpN3zgiGLFU6u1Pp8Fnf4Tzv3o=; b=UwXrh9nREDqi75YqIGqlFuNuDy4dDGLFRN/6PUSN92VLN0j+vA0v2VaLdSdIKJCspj9j GvN8Um/oNQJ39Cuxqp/I9GGRufJ83Wfa0fw1eoz5AJkEvqD8SC5awLnWWHmWoEZSZO+5 hiMFqR1zhm0Xym12Wgojy21U0yjUe3CPFq111M9k1WTAMxaLMKZ7fKi7Uh3wuV7hXZ4+ 9B59k1R34VECA8GL54eInI5VJmfFR+24FHvRtnB0L1lgDtHAqgtKCSlGjg4Zw0shA8DI DcthYmm4c1FKe6KaH5Ij84k4cv8FmJe5WWnujoFqK3ZeuxXhkie0DWAwlTRzuO6Y2QA0 3A== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 328mmhsv51-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 15 Jul 2020 01:33:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 15 Jul 2020 01:33:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 15 Jul 2020 01:33:41 -0700 Received: from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id D99463F703F; Wed, 15 Jul 2020 01:33:38 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal , Radu Nicolau CC: Tejasree Kondoj , Narayana Prasad , Anoob Joseph , Vamsi Attunuru , Date: Wed, 15 Jul 2020 14:56:55 +0530 Message-ID: <20200715092703.17936-2-ktejasree@marvell.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200715092703.17936-1-ktejasree@marvell.com> References: <20200715092703.17936-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-15_06:2020-07-15, 2020-07-15 signatures=0 Subject: [dpdk-dev] [PATCH v2 1/9] crypto/octeontx2: move capabilities initialization into probe X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch moves capabilities initialization into probe. Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx2/otx2_cryptodev.c | 2 ++ drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c | 9 ++++++--- drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h | 8 +++++++- drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 2 +- 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index 9aa0fe35b4..a51d532553 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -101,6 +101,8 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, goto otx2_dev_fini; } + otx2_crypto_capabilities_init(vf->hw_caps); + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c index f6f4dee6cf..f0ed1e2df9 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c @@ -737,10 +737,9 @@ cpt_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps) cur_pos += nb_caps; } -const struct rte_cryptodev_capabilities * -otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps) +void +otx2_crypto_capabilities_init(union cpt_eng_caps *hw_caps) { - CPT_CAPS_ADD(hw_caps, mul); CPT_CAPS_ADD(hw_caps, sha1_sha2); CPT_CAPS_ADD(hw_caps, chacha20); @@ -751,6 +750,10 @@ otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps) cpt_caps_add(caps_null, RTE_DIM(caps_null)); cpt_caps_add(caps_end, RTE_DIM(caps_end)); +} +const struct rte_cryptodev_capabilities * +otx2_cpt_capabilities_get(void) +{ return otx2_cpt_caps; } diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h index e07a2a8c92..a439cbefd3 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h @@ -16,11 +16,17 @@ enum otx2_cpt_egrp { OTX2_CPT_EGRP_MAX, }; +/* + * Initialize crypto capabilities for the device + * + */ +void otx2_crypto_capabilities_init(union cpt_eng_caps *hw_caps); + /* * Get capabilities list for the device * */ const struct rte_cryptodev_capabilities * -otx2_cpt_capabilities_get(union cpt_eng_caps *hw_caps); +otx2_cpt_capabilities_get(void); #endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index a3703682a0..229b719b42 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -1071,7 +1071,7 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev, if (info != NULL) { info->max_nb_queue_pairs = vf->max_queues; info->feature_flags = dev->feature_flags; - info->capabilities = otx2_cpt_capabilities_get(vf->hw_caps); + info->capabilities = otx2_cpt_capabilities_get(); info->sym.max_nb_sessions = 0; info->driver_id = otx2_cryptodev_driver_id; info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ; -- 2.27.0