From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from dpdk.org (dpdk.org [92.243.14.124])
by inbox.dpdk.org (Postfix) with ESMTP id 96EFBA0526;
Wed, 22 Jul 2020 04:12:56 +0200 (CEST)
Received: from [92.243.14.124] (localhost [127.0.0.1])
by dpdk.org (Postfix) with ESMTP id 5DAB41BFBA;
Wed, 22 Jul 2020 04:12:55 +0200 (CEST)
Received: from mga11.intel.com (mga11.intel.com [192.55.52.93])
by dpdk.org (Postfix) with ESMTP id 5B7EC2C01;
Wed, 22 Jul 2020 04:12:53 +0200 (CEST)
IronPort-SDR: 0NrqmZEDWEj8nwAFGniJv/xx67MXAXwumW+NkxwvYJfSjIDvcV4vf9DuhLk9c6JbeSoOSJ+MzF
1nlQUmhXDnNw==
X-IronPort-AV: E=McAfee;i="6000,8403,9689"; a="148197055"
X-IronPort-AV: E=Sophos;i="5.75,381,1589266800"; d="scan'208";a="148197055"
X-Amp-Result: SKIPPED(no attachment in message)
X-Amp-File-Uploaded: False
Received: from fmsmga004.fm.intel.com ([10.253.24.48])
by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
21 Jul 2020 19:12:52 -0700
IronPort-SDR: pQlo0GjsxPhAG+f74NVQP36KdNYSAsHdA5OndX/euVRGVtQxUEuOoTHk0CBLiIc1tTvG2njdsR
iKX4IQ6RrV+g==
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.75,381,1589266800"; d="scan'208";a="310456302"
Received: from dpdk-xuting-second.sh.intel.com ([10.67.116.154])
by fmsmga004.fm.intel.com with ESMTP; 21 Jul 2020 19:12:50 -0700
From: Ting Xu <ting.xu@intel.com>
To: dev@dpdk.org
Cc: cristian.dumitrescu@intel.com, Ting Xu <ting.xu@intel.com>, stable@dpdk.org
Date: Wed, 22 Jul 2020 10:16:28 +0800
Message-Id: <20200722021628.17194-1-ting.xu@intel.com>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20200616162705.83575-1-ting.xu@intel.com>
References: <20200616162705.83575-1-ting.xu@intel.com>
Subject: [dpdk-dev] [PATCH v4] lib/table: fix cache alignment issue
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
When create softnic hash table with 16 keys, it failed on 32-bit
environment, because the pointer field in structure rte_bucket_4_16
is only 32 bits. Add a padding field in 32-bit environment to keep
the structure to a multiple of 64 bytes. Apply this to 8-byte and
32-byte key hash function as well.
Fixes: 8aa327214c ("table: hash")
Cc: stable@dpdk.org
Signed-off-by: Ting Xu <ting.xu@intel.com>
---
v3->v4: Change design based on comment
v2->v3: Rebase
v1->v2: Correct patch time
---
lib/librte_table/rte_table_hash_key16.c | 17 +++++++++++++++++
lib/librte_table/rte_table_hash_key32.c | 17 +++++++++++++++++
lib/librte_table/rte_table_hash_key8.c | 16 ++++++++++++++++
3 files changed, 50 insertions(+)
diff --git a/lib/librte_table/rte_table_hash_key16.c b/lib/librte_table/rte_table_hash_key16.c
index 2cca1c924..c4384b114 100644
--- a/lib/librte_table/rte_table_hash_key16.c
+++ b/lib/librte_table/rte_table_hash_key16.c
@@ -33,6 +33,7 @@
#endif
+#ifdef RTE_ARCH_64
struct rte_bucket_4_16 {
/* Cache line 0 */
uint64_t signature[4 + 1];
@@ -46,6 +47,22 @@ struct rte_bucket_4_16 {
/* Cache line 2 */
uint8_t data[0];
};
+#else
+struct rte_bucket_4_16 {
+ /* Cache line 0 */
+ uint64_t signature[4 + 1];
+ uint64_t lru_list;
+ struct rte_bucket_4_16 *next;
+ uint32_t pad;
+ uint64_t next_valid;
+
+ /* Cache line 1 */
+ uint64_t key[4][2];
+
+ /* Cache line 2 */
+ uint8_t data[0];
+};
+#endif
struct rte_table_hash {
struct rte_table_stats stats;
diff --git a/lib/librte_table/rte_table_hash_key32.c b/lib/librte_table/rte_table_hash_key32.c
index a137c5028..3e0031fe1 100644
--- a/lib/librte_table/rte_table_hash_key32.c
+++ b/lib/librte_table/rte_table_hash_key32.c
@@ -33,6 +33,7 @@
#endif
+#ifdef RTE_ARCH_64
struct rte_bucket_4_32 {
/* Cache line 0 */
uint64_t signature[4 + 1];
@@ -46,6 +47,22 @@ struct rte_bucket_4_32 {
/* Cache line 3 */
uint8_t data[0];
};
+#else
+struct rte_bucket_4_32 {
+ /* Cache line 0 */
+ uint64_t signature[4 + 1];
+ uint64_t lru_list;
+ struct rte_bucket_4_32 *next;
+ uint32_t pad;
+ uint64_t next_valid;
+
+ /* Cache lines 1 and 2 */
+ uint64_t key[4][4];
+
+ /* Cache line 3 */
+ uint8_t data[0];
+};
+#endif
struct rte_table_hash {
struct rte_table_stats stats;
diff --git a/lib/librte_table/rte_table_hash_key8.c b/lib/librte_table/rte_table_hash_key8.c
index 1811ad8d0..34e3ed1af 100644
--- a/lib/librte_table/rte_table_hash_key8.c
+++ b/lib/librte_table/rte_table_hash_key8.c
@@ -31,6 +31,7 @@
#endif
+#ifdef RTE_ARCH_64
struct rte_bucket_4_8 {
/* Cache line 0 */
uint64_t signature;
@@ -43,6 +44,21 @@ struct rte_bucket_4_8 {
/* Cache line 1 */
uint8_t data[0];
};
+#else
+struct rte_bucket_4_8 {
+ /* Cache line 0 */
+ uint64_t signature;
+ uint64_t lru_list;
+ struct rte_bucket_4_8 *next;
+ uint32_t pad;
+ uint64_t next_valid;
+
+ uint64_t key[4];
+
+ /* Cache line 1 */
+ uint8_t data[0];
+};
+#endif
struct rte_table_hash {
struct rte_table_stats stats;
--
2.17.1