From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AEEC8A0524; Mon, 27 Jul 2020 00:47:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 646671C0AD; Mon, 27 Jul 2020 00:47:52 +0200 (CEST) Received: from relay10.mail.gandi.net (relay10.mail.gandi.net [217.70.178.230]) by dpdk.org (Postfix) with ESMTP id E8F061BFF2 for ; Mon, 27 Jul 2020 00:47:50 +0200 (CEST) Received: from u256.net (lfbn-idf2-1-1144-40.w90-92.abo.wanadoo.fr [90.92.205.40]) (Authenticated sender: grive@u256.net) by relay10.mail.gandi.net (Postfix) with ESMTPSA id 01292240007; Sun, 26 Jul 2020 22:47:47 +0000 (UTC) Date: Mon, 27 Jul 2020 00:47:42 +0200 From: =?utf-8?Q?Ga=C3=ABtan?= Rivet To: Manish Chopra Cc: "jerinjacobk@gmail.com" , Jerin Jacob Kollanukkaran , "ferruh.yigit@intel.com" , "dev@dpdk.org" , Igor Russkikh , Rasesh Mody , GR-Everest-DPDK-Dev , "rosen.xu@intel.com" , "tianfei.zhang@intel.com" , "heinrich.kuhn@netronome.com" , "qiming.yang@intel.com" , "qi.z.zhang@intel.com" Message-ID: <20200726224742.zyf7mn52zh3nvxpk@u256.net> References: <20200724103846.12640-1-manishc@marvell.com> <20200724103846.12640-2-manishc@marvell.com> <20200725173224.okzt3owicgdjun5s@u256.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Subject: Re: [dpdk-dev] [EXT] Re: [PATCH v3 1/6] drivers: add generic API to find PCI extended cap X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 26/07/20 19:47 +0000, Manish Chopra wrote: [...] > > > diff --git a/lib/librte_pci/rte_pci.h b/lib/librte_pci/rte_pci.h index > > > a03235da1..fec51e15a 100644 > > > --- a/lib/librte_pci/rte_pci.h > > > +++ b/lib/librte_pci/rte_pci.h > > > @@ -22,6 +22,22 @@ extern "C" { > > > #include > > > #include > > > > > > + > > > +/* > > > + * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of > > > + * configuration space. PCI-X Mode 2 and PCIe devices have 4096 > > > +bytes of > > > + * configuration space. > > > + */ > > > +#define RTE_PCI_CFG_SPACE_SIZE 256 > > > +#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096 > > > + > > > +/* Extended Capabilities (PCI-X 2.0 and Express) */ > > > +#define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff) > > > +#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) > > > + > > > +#define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting > > */ > > > +#define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ > > > + > > > > I understand that it is more natural to have those defines in the PCI lib, but I > > think there is no point in adding them in a separate lib, while the function > > using those is in the PCI bus. > > > > I think the defines should be put right before the > > rte_pci_find_next_ext_capability() prototype in > > drivers/bus/pci/rte_bus_pci.h. > > Hello Gaetan, > > I think these comes in the category of all RTE_PCI_* generic defines (not just use in drivers/bus/pci/), > Since caller of the API also need to use it, For example, couple of RTE_PCI_* were added in patch #2 > used by qede drivers specifically. rte_pci.h sounds more generic than rte_bus_pci.h hence I thought it > is the suitable place to consolidate them in there. > > Thanks !! Reading the additional symbols, particularly about SRIOV capa, I think you are right, it's probably better to have it all within rte_pci.h. To help developers, it would be better to point in the doc that the capability IDs useable as parameter `cap` can be any from RTE_PCI_EXT_CAP_ID_*, defined within librte_pci. The dev can then grep it. One additional thing: > > > +#define RTE_PCI_CFG_SPACE_SIZE 256 > > > +#define RTE_PCI_CFG_SPACE_EXP_SIZE 4096 > > > + > > > +/* Extended Capabilities (PCI-X 2.0 and Express) */ > > > +#define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff) > > > +#define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) I think those macros are not useful as part of the public API, they are only used to implement rte_pci_find_next_ext_capability(). Can you confirm? If this is correct, I think they should be moved to the compilation unit implementing rte_pci_find_next_ext_capability(). Regards, -- Gaëtan