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* [dpdk-dev] [PATCH 0/4] bnxt patches
@ 2020-07-29 14:04 Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 1/4] net/bnxt: configure loopback parif for full offload egress flows Somnath Kotur
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Somnath Kotur @ 2020-07-29 14:04 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit

fixes and cleanups in bnxt TRUFlow 

Kishore Padmanabha (2):
  net/bnxt: configure loopback parif for full offload egress flows
  net/bnxt: enable lookup default action record parif entry

Somnath Kotur (1):
  net/bnxt: cleanups and checks for ulp context allocation

Venkat Duvvuru (1):
  net/bnxt: fix vfrep port add when it's endpoint interface is down

 drivers/net/bnxt/bnxt.h                         |  21 ++
 drivers/net/bnxt/bnxt_cpr.c                     |  51 ++++
 drivers/net/bnxt/bnxt_ethdev.c                  |  12 +-
 drivers/net/bnxt/bnxt_hwrm.c                    |   4 +
 drivers/net/bnxt/bnxt_hwrm.h                    |   2 +
 drivers/net/bnxt/bnxt_reps.c                    |  88 +++++--
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c              |   2 +
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c         |   2 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c        |   6 +
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 314 ++++++++++++++----------
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h  |   3 +-
 11 files changed, 356 insertions(+), 149 deletions(-)

-- 
2.7.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-dev] [PATCH 1/4] net/bnxt: configure loopback parif for full offload egress flows
  2020-07-29 14:04 [dpdk-dev] [PATCH 0/4] bnxt patches Somnath Kotur
@ 2020-07-29 14:04 ` Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 2/4] net/bnxt: enable lookup default action record parif entry Somnath Kotur
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Somnath Kotur @ 2020-07-29 14:04 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The full offload egress flows for the VF rep interface should
use loopback parif to offload missed flows.

Fixes: fe82f3e02701 ("net/bnxt: support exact match templates")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c        |  6 ++++++
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 20 ++++++++++----------
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h  |  3 ++-
 3 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 861414d..fcb7c44 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -211,6 +211,12 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
 			ULP_COMP_FLD_IDX_WR(params,
 					    BNXT_ULP_CF_IDX_VF_FUNC_PARIF,
 					    parif);
+
+			/* populate the loopback parif */
+			ULP_COMP_FLD_IDX_WR(params,
+					    BNXT_ULP_CF_IDX_LOOPBACK_PARIF,
+					    BNXT_ULP_SYM_VF_FUNC_PARIF);
+
 		} else {
 			/* Set DRV func PARIF */
 			if (ulp_port_db_parif_get(params->ulp_ctx, ifindex,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index 94160a9..aaa552a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -16731,8 +16731,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_true = {
-		(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,
+		(BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_false = {
@@ -16933,8 +16933,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_true = {
-		(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,
+		(BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_false = {
@@ -17135,8 +17135,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_true = {
-		(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,
+		(BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_false = {
@@ -17337,8 +17337,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_true = {
-		(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,
+		(BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_false = {
@@ -17530,8 +17530,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_true = {
-		(BNXT_ULP_CF_IDX_VF_FUNC_PARIF >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_VF_FUNC_PARIF & 0xff,
+		(BNXT_ULP_CF_IDX_LOOPBACK_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_LOOPBACK_PARIF & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.result_operand_false = {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 9855918..4c6c359 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -132,7 +132,8 @@ enum bnxt_ulp_cf_idx {
 	BNXT_ULP_CF_IDX_L3_HDR_CNT = 40,
 	BNXT_ULP_CF_IDX_L4_HDR_CNT = 41,
 	BNXT_ULP_CF_IDX_VFR_MODE = 42,
-	BNXT_ULP_CF_IDX_LAST = 43
+	BNXT_ULP_CF_IDX_LOOPBACK_PARIF = 43,
+	BNXT_ULP_CF_IDX_LAST = 44
 };
 
 enum bnxt_ulp_cond_opcode {
-- 
2.7.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-dev] [PATCH 2/4] net/bnxt: enable lookup default action record parif entry
  2020-07-29 14:04 [dpdk-dev] [PATCH 0/4] bnxt patches Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 1/4] net/bnxt: configure loopback parif for full offload egress flows Somnath Kotur
@ 2020-07-29 14:04 ` Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 3/4] net/bnxt: cleanups and checks for ulp context allocation Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 4/4] net/bnxt: fix vfrep port add when it's endpoint interface is down Somnath Kotur
  3 siblings, 0 replies; 5+ messages in thread
From: Somnath Kotur @ 2020-07-29 14:04 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The lookup default action record parif table is updated to catch
the miss path for the entries in the exact match table.

Fixes: fe82f3e02701 ("net/bnxt: support exact match templates")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 294 ++++++++++++++----------
 1 file changed, 177 insertions(+), 117 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index aaa552a..1f650e0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -3240,148 +3240,148 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
 	[((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 5,
+	.num_tbls = 6,
 	.start_tbl_idx = 0,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
 	},
 	[((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 6,
-	.start_tbl_idx = 5,
+	.num_tbls = 7,
+	.start_tbl_idx = 6,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
 	},
 	[((3 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 7,
-	.start_tbl_idx = 11,
+	.start_tbl_idx = 13,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
 	},
 	[((4 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 6,
-	.start_tbl_idx = 18,
+	.num_tbls = 7,
+	.start_tbl_idx = 20,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
 	},
 	[((5 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 1,
-	.start_tbl_idx = 24,
+	.start_tbl_idx = 27,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
 	},
 	[((6 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 25,
+	.start_tbl_idx = 28,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((7 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 29,
+	.start_tbl_idx = 32,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((8 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 34,
+	.start_tbl_idx = 37,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((9 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 39,
+	.start_tbl_idx = 42,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((10 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 44,
+	.start_tbl_idx = 47,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((11 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 49,
+	.start_tbl_idx = 52,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((12 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 53,
+	.start_tbl_idx = 56,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((13 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 57,
+	.start_tbl_idx = 60,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((14 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 61,
+	.start_tbl_idx = 64,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((15 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 65,
+	.start_tbl_idx = 68,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((16 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 69,
+	.start_tbl_idx = 72,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((17 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 73,
+	.start_tbl_idx = 76,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((18 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 78,
+	.start_tbl_idx = 81,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((19 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 83,
+	.start_tbl_idx = 86,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((20 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 88,
+	.start_tbl_idx = 91,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	},
 	[((21 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
 		BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 4,
-	.start_tbl_idx = 93,
+	.start_tbl_idx = 96,
 	.flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
 	}
 };
@@ -3439,7 +3439,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_RX,
 	.result_start_idx = 40,
 	.result_bit_size = 32,
@@ -3450,7 +3450,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
-	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_RX,
 	.result_start_idx = 41,
 	.result_bit_size = 32,
@@ -3460,12 +3460,23 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF
 	},
 	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+	.direction = TF_DIR_RX,
+	.result_start_idx = 42,
+	.result_bit_size = 32,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD,
+	.index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF
+	},
+	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
 	.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 42,
+	.result_start_idx = 43,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
@@ -3485,7 +3496,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 68,
+	.result_start_idx = 69,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3506,7 +3517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 81,
+	.result_start_idx = 82,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3525,7 +3536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 82,
+	.result_start_idx = 83,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3536,9 +3547,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.result_start_idx = 96,
+	.result_bit_size = 32,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD,
+	.index_operand = BNXT_ULP_CF_IDX_DRV_FUNC_PARIF
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 95,
+	.result_start_idx = 97,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3549,7 +3571,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 96,
+	.result_start_idx = 98,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3562,7 +3584,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 97,
+	.result_start_idx = 99,
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
@@ -3576,7 +3598,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 109,
+	.result_start_idx = 111,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
@@ -3594,7 +3616,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 135,
+	.result_start_idx = 137,
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 0,
@@ -3611,7 +3633,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 135,
+	.result_start_idx = 137,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3626,7 +3648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
-	.result_start_idx = 148,
+	.result_start_idx = 150,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
@@ -3644,7 +3666,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 174,
+	.result_start_idx = 176,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3663,7 +3685,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 187,
+	.result_start_idx = 189,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3682,7 +3704,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 200,
+	.result_start_idx = 202,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3699,7 +3721,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 201,
+	.result_start_idx = 203,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3710,9 +3732,20 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+	.resource_type = TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
+	.direction = TF_DIR_TX,
+	.result_start_idx = 216,
+	.result_bit_size = 32,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.index_opcode = BNXT_ULP_INDEX_OPCODE_CONSTANT,
+	.index_operand = BNXT_ULP_SYM_VF_FUNC_PARIF
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 214,
+	.result_start_idx = 217,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3723,7 +3756,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
 	.resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 215,
+	.result_start_idx = 218,
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3736,7 +3769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
-	.result_start_idx = 216,
+	.result_start_idx = 219,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
@@ -3754,7 +3787,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 242,
+	.result_start_idx = 245,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3769,7 +3802,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
-	.result_start_idx = 255,
+	.result_start_idx = 258,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
@@ -3787,7 +3820,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 281,
+	.result_start_idx = 284,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3806,7 +3839,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 294,
+	.result_start_idx = 297,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3823,7 +3856,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 295,
+	.result_start_idx = 298,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -3840,7 +3873,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 303,
+	.result_start_idx = 306,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -3859,7 +3892,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 312,
+	.result_start_idx = 315,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3876,7 +3909,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 313,
+	.result_start_idx = 316,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3895,7 +3928,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 326,
+	.result_start_idx = 329,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3912,7 +3945,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 327,
+	.result_start_idx = 330,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -3929,7 +3962,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 335,
+	.result_start_idx = 338,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -3948,7 +3981,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 344,
+	.result_start_idx = 347,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -3965,7 +3998,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 345,
+	.result_start_idx = 348,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -3984,7 +4017,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 358,
+	.result_start_idx = 361,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4001,7 +4034,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 359,
+	.result_start_idx = 362,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4018,7 +4051,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 367,
+	.result_start_idx = 370,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4037,7 +4070,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 376,
+	.result_start_idx = 379,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4054,7 +4087,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 377,
+	.result_start_idx = 380,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4073,7 +4106,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 390,
+	.result_start_idx = 393,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4090,7 +4123,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 391,
+	.result_start_idx = 394,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4107,7 +4140,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 399,
+	.result_start_idx = 402,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4126,7 +4159,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 408,
+	.result_start_idx = 411,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4143,7 +4176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 409,
+	.result_start_idx = 412,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4162,7 +4195,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 422,
+	.result_start_idx = 425,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4179,7 +4212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 423,
+	.result_start_idx = 426,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4196,7 +4229,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 431,
+	.result_start_idx = 434,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4215,7 +4248,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 440,
+	.result_start_idx = 443,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4234,7 +4267,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 453,
+	.result_start_idx = 456,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4251,7 +4284,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 454,
+	.result_start_idx = 457,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4268,7 +4301,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 462,
+	.result_start_idx = 465,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4287,7 +4320,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 471,
+	.result_start_idx = 474,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4306,7 +4339,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 484,
+	.result_start_idx = 487,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4323,7 +4356,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 485,
+	.result_start_idx = 488,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4340,7 +4373,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 493,
+	.result_start_idx = 496,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4359,7 +4392,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 502,
+	.result_start_idx = 505,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4378,7 +4411,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 515,
+	.result_start_idx = 518,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4395,7 +4428,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 516,
+	.result_start_idx = 519,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4412,7 +4445,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 524,
+	.result_start_idx = 527,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4431,7 +4464,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 533,
+	.result_start_idx = 536,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4450,7 +4483,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 546,
+	.result_start_idx = 549,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4467,7 +4500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 547,
+	.result_start_idx = 550,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4484,7 +4517,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 555,
+	.result_start_idx = 558,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4503,7 +4536,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 564,
+	.result_start_idx = 567,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4522,7 +4555,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 577,
+	.result_start_idx = 580,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4539,7 +4572,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 578,
+	.result_start_idx = 581,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4556,7 +4589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 586,
+	.result_start_idx = 589,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4575,7 +4608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 595,
+	.result_start_idx = 598,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4594,7 +4627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 608,
+	.result_start_idx = 611,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4611,7 +4644,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 609,
+	.result_start_idx = 612,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4628,7 +4661,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 617,
+	.result_start_idx = 620,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4647,7 +4680,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 626,
+	.result_start_idx = 629,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4664,7 +4697,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 627,
+	.result_start_idx = 630,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4683,7 +4716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 640,
+	.result_start_idx = 643,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4700,7 +4733,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 641,
+	.result_start_idx = 644,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4717,7 +4750,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 649,
+	.result_start_idx = 652,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4736,7 +4769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 658,
+	.result_start_idx = 661,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4753,7 +4786,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 659,
+	.result_start_idx = 662,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4772,7 +4805,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 672,
+	.result_start_idx = 675,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4789,7 +4822,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 673,
+	.result_start_idx = 676,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4806,7 +4839,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 681,
+	.result_start_idx = 684,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4825,7 +4858,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 690,
+	.result_start_idx = 693,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4842,7 +4875,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 691,
+	.result_start_idx = 694,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4861,7 +4894,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 704,
+	.result_start_idx = 707,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4878,7 +4911,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 705,
+	.result_start_idx = 708,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4895,7 +4928,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 713,
+	.result_start_idx = 716,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -4914,7 +4947,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 722,
+	.result_start_idx = 725,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4931,7 +4964,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 723,
+	.result_start_idx = 726,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -4950,7 +4983,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 736,
+	.result_start_idx = 739,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -4967,7 +5000,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 737,
+	.result_start_idx = 740,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -4984,7 +5017,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 745,
+	.result_start_idx = 748,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -5003,7 +5036,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 754,
+	.result_start_idx = 757,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
@@ -5022,7 +5055,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 767,
+	.result_start_idx = 770,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
@@ -5039,7 +5072,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 42,
-	.result_start_idx = 768,
+	.result_start_idx = 771,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
@@ -5056,7 +5089,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
-	.result_start_idx = 776,
+	.result_start_idx = 779,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
@@ -13591,6 +13624,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 32,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
 	.field_bit_size = 14,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -13859,6 +13901,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 32,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
 	.field_bit_size = 3,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -14419,6 +14470,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 32,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
 	.field_bit_size = 14,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
-- 
2.7.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-dev] [PATCH 3/4] net/bnxt: cleanups and checks for ulp context allocation
  2020-07-29 14:04 [dpdk-dev] [PATCH 0/4] bnxt patches Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 1/4] net/bnxt: configure loopback parif for full offload egress flows Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 2/4] net/bnxt: enable lookup default action record parif entry Somnath Kotur
@ 2020-07-29 14:04 ` Somnath Kotur
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 4/4] net/bnxt: fix vfrep port add when it's endpoint interface is down Somnath Kotur
  3 siblings, 0 replies; 5+ messages in thread
From: Somnath Kotur @ 2020-07-29 14:04 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit

Set ulp_ctx explicitly to NULL in ulp_ctx_deinit() so that representor
init is aborted if parent ulp context is not initialized.
Also check for the same before creation of port default rules.
Additional checks in VF rep dev ops for proper parent dev initialization

Fixes: 322bd6e70272 ("net/bnxt: add port representor infrastructure")
Fixes: 313ac35ac701 ("net/bnxt: support ULP session manager init")

Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
 drivers/net/bnxt/bnxt_reps.c            | 18 ++++++++++++++++++
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c      |  2 ++
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c |  2 +-
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 6fa9a30..2941aff 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -319,6 +319,7 @@ static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 {
 	int rc = 0;
 	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
+	struct bnxt *parent_bp;
 
 	if (!vfr || !vfr->parent_dev) {
 		PMD_DRV_LOG(ERR,
@@ -326,6 +327,13 @@ static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 		return -ENOMEM;
 	}
 
+	parent_bp = vfr->parent_dev->data->dev_private;
+	if (parent_bp && !parent_bp->ulp_ctx) {
+		PMD_DRV_LOG(ERR,
+			    "ulp context not allocated for parent\n");
+		return -EIO;
+	}
+
 	/* Check if representor has been already allocated in FW */
 	if (vfr->vfr_tx_cfa_action)
 		return 0;
@@ -534,6 +542,11 @@ int bnxt_vf_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
 		return -EINVAL;
 	}
 
+	if (!parent_bp->rx_queues) {
+		PMD_DRV_LOG(ERR, "Parent Rx qs not configured yet\n");
+		return -EINVAL;
+	}
+
 	parent_rxq = parent_bp->rx_queues[queue_idx];
 	if (!parent_rxq) {
 		PMD_DRV_LOG(ERR, "Parent RxQ has not been configured yet\n");
@@ -628,6 +641,11 @@ int bnxt_vf_rep_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
 		return -EINVAL;
 	}
 
+	if (!parent_bp->tx_queues) {
+		PMD_DRV_LOG(ERR, "Parent Tx qs not configured yet\n");
+		return -EINVAL;
+	}
+
 	parent_txq = parent_bp->tx_queues[queue_idx];
 	if (!parent_txq) {
 		PMD_DRV_LOG(ERR, "Parent TxQ has not been configured yet\n");
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 077527f..c19cd1d 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -884,6 +884,8 @@ bnxt_ulp_deinit(struct bnxt *bp)
 	ulp_session_deinit(session);
 
 	rte_free(bp->ulp_ctx);
+
+	bp->ulp_ctx = NULL;
 }
 
 /* Function to set the Mark DB into the context */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index 9fb1a02..46acc1d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -465,7 +465,7 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
 	int rc;
 
 	if (!BNXT_TRUFLOW_EN(bp) ||
-	    BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev))
+	    BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev) || !bp->ulp_ctx)
 		return 0;
 
 	port_id = bp->eth_dev->data->port_id;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [dpdk-dev] [PATCH 4/4] net/bnxt: fix vfrep port add when it's endpoint interface is down
  2020-07-29 14:04 [dpdk-dev] [PATCH 0/4] bnxt patches Somnath Kotur
                   ` (2 preceding siblings ...)
  2020-07-29 14:04 ` [dpdk-dev] [PATCH 3/4] net/bnxt: cleanups and checks for ulp context allocation Somnath Kotur
@ 2020-07-29 14:04 ` Somnath Kotur
  3 siblings, 0 replies; 5+ messages in thread
From: Somnath Kotur @ 2020-07-29 14:04 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit

From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>

While adding vfrep port to OVS bridge, vnic & svif information of
vfrep's endpoint(VF) would be needed to program default flow rules.
However, if the endpoint interface is down when vfrep port is added,
firmware will return invalid vnic & svif information.

This patch fixes the problem by registering to DEFAULT_VNIC_CHANGE
async event and once the async event is received, use the endpoint
information(VF's fid) to fetch it's vnic & svif information and
program the default flow rules.

Fixes: 322bd6e70272 ("net/bnxt: add port representor infrastructure")

Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
 drivers/net/bnxt/bnxt.h        | 21 +++++++++++++
 drivers/net/bnxt/bnxt_cpr.c    | 51 ++++++++++++++++++++++++++++++
 drivers/net/bnxt/bnxt_ethdev.c | 12 +++++++-
 drivers/net/bnxt/bnxt_hwrm.c   |  4 +++
 drivers/net/bnxt/bnxt_hwrm.h   |  2 ++
 drivers/net/bnxt/bnxt_reps.c   | 70 ++++++++++++++++++++++++++++++------------
 6 files changed, 140 insertions(+), 20 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index f4b2a3f..74e2c9a 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -147,6 +147,23 @@
 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT	50
 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT	12
 
+#define	BNXT_DEFAULT_VNIC_STATE_MASK			\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
+#define	BNXT_DEFAULT_VNIC_STATE_SFT			\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
+#define	BNXT_DEFAULT_VNIC_ALLOC				\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
+#define	BNXT_DEFAULT_VNIC_FREE				\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
+#define	BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK		\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
+#define	BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT		\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
+#define	BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK		\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
+#define	BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT		\
+	HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
+
 struct bnxt_led_info {
 	uint8_t	     num_leds;
 	uint8_t      led_id;
@@ -498,6 +515,8 @@ struct bnxt_mark_info {
 struct bnxt_rep_info {
 	struct rte_eth_dev	*vfr_eth_dev;
 	pthread_mutex_t		vfr_lock;
+	pthread_mutex_t		vfr_start_lock;
+	bool			conduit_valid;
 };
 
 /* address space location of register */
@@ -796,6 +815,7 @@ struct bnxt_vf_representor {
 	uint16_t		switch_domain_id;
 	uint16_t		vf_id;
 	uint16_t		fw_fid;
+#define	BNXT_DFLT_VNIC_ID_INVALID	0xFFFF
 	uint16_t		dflt_vnic_id;
 	uint16_t		svif;
 	uint16_t		vfr_tx_cfa_action;
@@ -884,6 +904,7 @@ uint16_t bnxt_get_phy_port_id(uint16_t port);
 uint16_t bnxt_get_vport(uint16_t port);
 enum bnxt_ulp_intf_type
 bnxt_get_interface_type(uint16_t port);
+int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev);
 
 void bnxt_cancel_fc_thread(struct bnxt *bp);
 void bnxt_flow_cnt_alarm_cb(void *arg);
diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c
index 40e5350..464ca8b 100644
--- a/drivers/net/bnxt/bnxt_cpr.c
+++ b/drivers/net/bnxt/bnxt_cpr.c
@@ -46,6 +46,54 @@ void bnxt_wait_for_device_shutdown(struct bnxt *bp)
 	} while (timeout);
 }
 
+static void
+bnxt_process_default_vnic_change(struct bnxt *bp,
+				 struct hwrm_async_event_cmpl *async_cmp)
+{
+	uint16_t fid, vnic_state, parent_id, vf_fid, vf_id;
+	struct bnxt_vf_representor *vf_rep_bp;
+	struct rte_eth_dev *eth_dev;
+	bool vfr_found = false;
+	uint32_t event_data;
+
+	if (!BNXT_TRUFLOW_EN(bp))
+		return;
+
+	PMD_DRV_LOG(INFO, "Default vnic change async event received\n");
+	event_data = rte_le_to_cpu_32(async_cmp->event_data1);
+
+	vnic_state = (event_data & BNXT_DEFAULT_VNIC_STATE_MASK) >>
+			BNXT_DEFAULT_VNIC_STATE_SFT;
+	if (vnic_state != BNXT_DEFAULT_VNIC_ALLOC)
+		return;
+
+	parent_id = (event_data & BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK) >>
+			BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT;
+	fid = BNXT_PF(bp) ? bp->fw_fid : bp->parent->fid;
+	if (parent_id != fid || !bp->rep_info)
+		return;
+
+	vf_fid = (event_data & BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK) >>
+			BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT;
+	PMD_DRV_LOG(INFO, "async event received vf_id 0x%x\n", vf_fid);
+
+	for (vf_id = 0; vf_id < BNXT_MAX_VF_REPS; vf_id++) {
+		eth_dev = bp->rep_info[vf_id].vfr_eth_dev;
+		if (!eth_dev)
+			continue;
+		vf_rep_bp = eth_dev->data->dev_private;
+		if (vf_rep_bp &&
+		    vf_rep_bp->fw_fid == vf_fid) {
+			vfr_found = true;
+			break;
+		}
+	}
+	if (!vfr_found)
+		return;
+
+	bnxt_vf_rep_dev_start_op(eth_dev);
+}
+
 /*
  * Async event handling
  */
@@ -144,6 +192,9 @@ void bnxt_handle_async_event(struct bnxt *bp,
 			    rte_le_to_cpu_32(async_cmp->event_data1),
 			    rte_le_to_cpu_32(async_cmp->event_data2));
 		break;
+	case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE:
+		bnxt_process_default_vnic_change(bp, async_cmp);
+		break;
 	default:
 		PMD_DRV_LOG(DEBUG, "handle_async_event id = 0x%x\n", event_id);
 		break;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 510a0d9..c2dda07 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -5833,8 +5833,10 @@ bnxt_uninit_locks(struct bnxt *bp)
 {
 	pthread_mutex_destroy(&bp->flow_lock);
 	pthread_mutex_destroy(&bp->def_cp_lock);
-	if (bp->rep_info)
+	if (bp->rep_info) {
 		pthread_mutex_destroy(&bp->rep_info->vfr_lock);
+		pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
+	}
 }
 
 static int
@@ -5937,6 +5939,14 @@ static int bnxt_init_rep_info(struct bnxt *bp)
 		bnxt_free_rep_info(bp);
 		return rc;
 	}
+
+	rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
+	if (rc) {
+		PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
+		bnxt_free_rep_info(bp);
+		return rc;
+	}
+
 	return rc;
 }
 
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 8296d1d..b0a0aab 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -918,6 +918,10 @@ int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 		req.async_event_fwd[1] |=
 			rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
 
+	if (BNXT_VF_IS_TRUSTED(bp))
+		req.async_event_fwd[1] |=
+		rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
+
 	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 
 	HWRM_CHECK_RESULT();
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index 4a2af13..f55b6f9 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -34,6 +34,8 @@ struct hwrm_func_qstats_output;
 	(1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE - 32))
 #define ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION	\
 	(1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION - 32))
+#define	ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE	\
+	(1 << (HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE - 32))
 
 #define HWRM_QUEUE_SERVICE_PROFILE_LOSSY \
 	HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 2941aff..a1b2c4b 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -135,6 +135,32 @@ bnxt_vf_rep_tx_burst(void *tx_queue,
 	return rc;
 }
 
+static int
+bnxt_get_dflt_vnic_svif(struct bnxt *bp, struct bnxt_vf_representor *vf_rep_bp)
+{
+	struct bnxt_rep_info *rep_info;
+	int rc;
+
+	rc = bnxt_hwrm_get_dflt_vnic_svif(bp, vf_rep_bp->fw_fid,
+					  &vf_rep_bp->dflt_vnic_id,
+					  &vf_rep_bp->svif);
+	if (rc) {
+		PMD_DRV_LOG(ERR, "Failed to get default vnic id of VF\n");
+		vf_rep_bp->dflt_vnic_id = BNXT_DFLT_VNIC_ID_INVALID;
+		vf_rep_bp->svif = BNXT_SVIF_INVALID;
+	} else {
+		PMD_DRV_LOG(INFO, "vf_rep->dflt_vnic_id = %d\n",
+				vf_rep_bp->dflt_vnic_id);
+	}
+	if (vf_rep_bp->dflt_vnic_id != BNXT_DFLT_VNIC_ID_INVALID &&
+	    vf_rep_bp->svif != BNXT_SVIF_INVALID) {
+		rep_info = &bp->rep_info[vf_rep_bp->vf_id];
+		rep_info->conduit_valid = true;
+	}
+
+	return rc;
+}
+
 int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
 {
 	struct bnxt_vf_representor *vf_rep_bp = eth_dev->data->dev_private;
@@ -142,7 +168,6 @@ int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
 				 (struct bnxt_vf_representor *)params;
 	struct rte_eth_link *link;
 	struct bnxt *parent_bp;
-	int rc = 0;
 
 	vf_rep_bp->vf_id = rep_params->vf_id;
 	vf_rep_bp->switch_domain_id = rep_params->switch_domain_id;
@@ -172,17 +197,6 @@ int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
 	eth_dev->data->dev_link.link_status = link->link_status;
 	eth_dev->data->dev_link.link_autoneg = link->link_autoneg;
 
-	vf_rep_bp->fw_fid = rep_params->vf_id + parent_bp->first_vf_id;
-	PMD_DRV_LOG(INFO, "vf_rep->fw_fid = %d\n", vf_rep_bp->fw_fid);
-	rc = bnxt_hwrm_get_dflt_vnic_svif(parent_bp, vf_rep_bp->fw_fid,
-					  &vf_rep_bp->dflt_vnic_id,
-					  &vf_rep_bp->svif);
-	if (rc)
-		PMD_DRV_LOG(ERR, "Failed to get default vnic id of VF\n");
-	else
-		PMD_DRV_LOG(INFO, "vf_rep->dflt_vnic_id = %d\n",
-			    vf_rep_bp->dflt_vnic_id);
-
 	PMD_DRV_LOG(INFO, "calling bnxt_print_link_info\n");
 	bnxt_print_link_info(eth_dev);
 
@@ -194,6 +208,9 @@ int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
 		    "Switch domain id %d: Representor Device %d init done\n",
 		    vf_rep_bp->switch_domain_id, vf_rep_bp->vf_id);
 
+	vf_rep_bp->fw_fid = rep_params->vf_id + parent_bp->first_vf_id;
+	PMD_DRV_LOG(INFO, "vf_rep->fw_fid = %d\n", vf_rep_bp->fw_fid);
+
 	return 0;
 }
 
@@ -369,21 +386,36 @@ static void bnxt_vf_rep_free_rx_mbufs(struct bnxt_vf_representor *rep_bp)
 int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 {
 	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_rep_info *rep_info;
+	struct bnxt *parent_bp;
 	int rc;
 
-	rc = bnxt_vfr_alloc(eth_dev);
+	parent_bp = rep_bp->parent_dev->data->dev_private;
+	rep_info = &parent_bp->rep_info[rep_bp->vf_id];
 
-	if (!rc) {
-		eth_dev->rx_pkt_burst = &bnxt_vf_rep_rx_burst;
-		eth_dev->tx_pkt_burst = &bnxt_vf_rep_tx_burst;
+	pthread_mutex_lock(&rep_info->vfr_start_lock);
+	if (rep_info->conduit_valid) {
+		pthread_mutex_unlock(&rep_info->vfr_start_lock);
+		return 0;
+	}
+	rc = bnxt_get_dflt_vnic_svif(parent_bp, rep_bp);
+	if (rc || !rep_info->conduit_valid) {
+		pthread_mutex_unlock(&rep_info->vfr_start_lock);
+		return rc;
+	}
+	pthread_mutex_unlock(&rep_info->vfr_start_lock);
 
-		bnxt_vf_rep_link_update_op(eth_dev, 1);
-	} else {
+	rc = bnxt_vfr_alloc(eth_dev);
+	if (rc) {
 		eth_dev->data->dev_link.link_status = 0;
 		bnxt_vf_rep_free_rx_mbufs(rep_bp);
+		return rc;
 	}
+	eth_dev->rx_pkt_burst = &bnxt_vf_rep_rx_burst;
+	eth_dev->tx_pkt_burst = &bnxt_vf_rep_tx_burst;
+	bnxt_vf_rep_link_update_op(eth_dev, 1);
 
-	return rc;
+	return 0;
 }
 
 static int bnxt_tf_vfr_free(struct bnxt_vf_representor *vfr)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2020-07-29 14:11 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-29 14:04 [dpdk-dev] [PATCH 0/4] bnxt patches Somnath Kotur
2020-07-29 14:04 ` [dpdk-dev] [PATCH 1/4] net/bnxt: configure loopback parif for full offload egress flows Somnath Kotur
2020-07-29 14:04 ` [dpdk-dev] [PATCH 2/4] net/bnxt: enable lookup default action record parif entry Somnath Kotur
2020-07-29 14:04 ` [dpdk-dev] [PATCH 3/4] net/bnxt: cleanups and checks for ulp context allocation Somnath Kotur
2020-07-29 14:04 ` [dpdk-dev] [PATCH 4/4] net/bnxt: fix vfrep port add when it's endpoint interface is down Somnath Kotur

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