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[204.195.22.127]) by smtp.gmail.com with ESMTPSA id a5sm13329789pfi.79.2020.08.07.09.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Aug 2020 09:19:24 -0700 (PDT) Date: Fri, 7 Aug 2020 09:19:17 -0700 From: Stephen Hemminger To: Ciara Power Cc: dev@dpdk.org, bruce.richardson@intel.com Message-ID: <20200807091917.0ae3a7f4@hermes.lan> In-Reply-To: <20200807155859.63888-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH 20.11 00/12] add max SIMD bitwidth to EAL X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, 7 Aug 2020 16:58:47 +0100 Ciara Power wrote: > A number of components in DPDK have optional AVX-512 or other vector > code paths which can be selected at runtime. Rather than having each > component provide its own mechanism to select a code path, this patchset > adds support for a single setting to control what code paths are used. > This can be used to enable some non-default code paths e.g. ones using > AVX-512, but also to limit the code paths to certain vector widths, or > to scalar code only, which is useful for testing. > > The max SIMD bitwidth setting can be set by the app itself through use of > the available API, or can be overriden by a commandline argument passed by > the user. > > Ciara Power (12): > eal: add max SIMD bitwidth > eal: add default SIMD bitwidth values > net/i40e: add checks for max SIMD bitwidth > net/axgbe: add checks for max SIMD bitwidth > net/bnxt: add checks for max SIMD bitwidth > net/enic: add checks for max SIMD bitwidth > net/fm10k: add checks for max SIMD bitwidth > net/iavf: add checks for max SIMD bitwidth > net/ice: add checks for max SIMD bitwidth > net/ixgbe: add checks for max SIMD bitwidth > net/mlx5: add checks for max SIMD bitwidth > net/virtio: add checks for max SIMD bitwidth > > drivers/net/axgbe/axgbe_rxtx.c | 3 +- > drivers/net/bnxt/bnxt_ethdev.c | 6 ++- > drivers/net/enic/enic_rxtx_vec_avx2.c | 3 +- > drivers/net/fm10k/fm10k_ethdev.c | 11 ++-- > drivers/net/i40e/i40e_rxtx.c | 19 ++++--- > drivers/net/iavf/iavf_rxtx.c | 16 +++--- > drivers/net/ice/ice_rxtx.c | 20 ++++--- > drivers/net/ixgbe/ixgbe_rxtx.c | 7 ++- > drivers/net/mlx5/mlx5_ethdev.c | 3 +- > drivers/net/virtio/virtio_ethdev.c | 12 +++-- > lib/librte_eal/arm/include/rte_vect.h | 2 + > lib/librte_eal/common/eal_common_options.c | 63 ++++++++++++++++++++++ > lib/librte_eal/common/eal_internal_cfg.h | 8 +++ > lib/librte_eal/common/eal_options.h | 2 + > lib/librte_eal/include/generic/rte_vect.h | 2 + > lib/librte_eal/include/rte_eal.h | 31 +++++++++++ > lib/librte_eal/ppc/include/rte_vect.h | 2 + > lib/librte_eal/rte_eal_version.map | 4 ++ > lib/librte_eal/x86/include/rte_vect.h | 2 + > 19 files changed, 184 insertions(+), 32 deletions(-) > This looks useful, could you add some documentation on rationale and how you expect application to set it.