From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 15454A04B0; Fri, 7 Aug 2020 14:05:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5A59B2BF1; Fri, 7 Aug 2020 14:05:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D742C2B87 for ; Fri, 7 Aug 2020 14:05:32 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 077BuE92015551; Fri, 7 Aug 2020 05:05:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=99qUIUpy1306dUM4g+rR4o6qsELAhujf2Rvx0eSuqIw=; b=X+FD812AlwzDCXTAHX7VHSpehGtF8zgT0kAI/fyKPtnCXFSZ3TXWu64DF55xzhpSg4lZ 58N9jg5D5FHVcq00nZrs68tODy94L6op5qKJusk1JftF85YDdtziv9sZt5zIDFYmFCSp Oqe3abYRkuDP66wi2NQvKVdBULNYHnkmolJw/Oriliw5FIe/uSXB2UZ3z/7abTrEnnZU xqbDcWg9WR/DqVByBs1Agwo3X7SZC8NjA6kVsTUegZRkBEzW1l/mh+Kxh9P6NVxx1b46 D2ZpPoGuXBjSLQ7sr/LMFoKAxEB/29CF2SREBW/noGgDd00NBredP/5KWPt9zhHNpKA0 kQ== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 32s3c98p85-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 07 Aug 2020 05:05:28 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 7 Aug 2020 05:05:26 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 7 Aug 2020 05:05:26 -0700 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 1EB6F3F7044; Fri, 7 Aug 2020 05:05:13 -0700 (PDT) From: To: Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Kiran Kumar K Date: Fri, 7 Aug 2020 17:34:32 +0530 Message-ID: <20200807120434.1701726-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-07_08:2020-08-06, 2020-08-07 signatures=0 Subject: [dpdk-dev] [PATCH 1/2] ethdev: add level support for RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K This patch reserves 2 bits as input selection to select Inner and outer layers for RSS computation. It is combined with existing ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4. This functionality already exists in rte_flow through level parameter in RSS action configuration rte_flow_action_rss. Signed-off-by: Kiran Kumar K --- lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h index d29930fd8..2164d2f8c 100644 --- a/lib/librte_ethdev/rte_ethdev.h +++ b/lib/librte_ethdev/rte_ethdev.h @@ -552,6 +552,33 @@ struct rte_eth_rss_conf { #define RTE_ETH_RSS_L3_PRE64 (1ULL << 53) #define RTE_ETH_RSS_L3_PRE96 (1ULL << 52) +/* + * We use the following macros to combine with the above layers to choose + * inner and outer layers or both for RSS computation. + * Note: Default is 0: inner layers, 1: outer layers, 2: both + * bit 56 and 57 are reserved for this. + */ + +/** + * Level 0, It basically stands for the innermost encapsulation level RSS + * can be performed on according to PMD and device capabilities. + */ +#define ETH_RSS_LEVEL_INNER (0ULL << 56) +/** + * Level 1, It basically stands for the outermost encapsulation level RSS + * can be performed on according to PMD and device capabilities. + */ +#define ETH_RSS_LEVEL_OUTER (1ULL << 56) +/** + * Level 2, It basically stands for the both inner and outermost + * encapsulation level RSS can be performed on according to PMD and + * device capabilities. + */ +#define ETH_RSS_LEVEL_INNER_OUTER (2ULL << 56) +#define ETH_RSS_LEVEL_MASK (3ULL << 56) + +#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 56) + /** * For input set change of hash filter, if SRC_ONLY and DST_ONLY of * the same level are used simultaneously, it is the same case as -- 2.25.1