From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9055AA04D7; Thu, 3 Sep 2020 06:56:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EB5421C12F; Thu, 3 Sep 2020 06:55:43 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 374B81C127 for ; Thu, 3 Sep 2020 06:55:42 +0200 (CEST) IronPort-SDR: DrvQMrSiq8otnO/mIXXW5Lu9iW4eS9bmNEMUeX1DPxcT2d7ITJVsaB690NNw3bTMM8o1dch8+Y MEaAxByePTgQ== X-IronPort-AV: E=McAfee;i="6000,8403,9732"; a="221732249" X-IronPort-AV: E=Sophos;i="5.76,385,1592895600"; d="scan'208";a="221732249" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2020 21:55:41 -0700 IronPort-SDR: zPmAxvTNbGmei0FbvXq8/kadLC4HclOlQ3ddW4cMPXUsin7VLIpMSdEoSlJQs/TkLnhHlmfTLY p82ILLIxTkKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,385,1592895600"; d="scan'208";a="315349304" Received: from dpdk.sh.intel.com ([10.239.255.12]) by orsmga002.jf.intel.com with ESMTP; 02 Sep 2020 21:55:40 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Beilei Xing , Jeff Guo , Guinan Sun , Jesse Brandeburg Date: Thu, 3 Sep 2020 04:48:50 +0000 Message-Id: <20200903044856.61961-10-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200903044856.61961-1-guinanx.sun@intel.com> References: <20200727053451.22214-1-guinanx.sun@intel.com> <20200903044856.61961-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH v3 09/15] net/i40e/base: enable pipe monitor thresholds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable several registers and defines for software controlled DCB, particularly around the receive pipe monitor configuration which is necessary to help ports achieve the right throughput under load in several different configurations. Signed-off-by: Jesse Brandeburg Signed-off-by: Guinan Sun --- drivers/net/i40e/base/i40e_register.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h index ee4f333f9..ee443e9c9 100644 --- a/drivers/net/i40e/base/i40e_register.h +++ b/drivers/net/i40e/base/i40e_register.h @@ -203,6 +203,9 @@ #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) +#define I40E_PRT_SWR_PM_THR 0x0026CD00 /* Reset: CORER */ +#define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0 +#define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT) #define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */ #define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 #define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT) -- 2.17.1