From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 04B30A04BF; Thu, 3 Sep 2020 16:50:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DB9F41C0C5; Thu, 3 Sep 2020 16:49:59 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 2F53F1C0C0 for <dev@dpdk.org>; Thu, 3 Sep 2020 16:49:57 +0200 (CEST) IronPort-SDR: iZUVSCkXJeiUipRSFAW4dec0DWgLR72LE1mt6D8EIpb0HKeIRjnVUuEXXNIwBmii1fBTNYP6JH y3jsPDjdwgkg== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="242403456" X-IronPort-AV: E=Sophos;i="5.76,387,1592895600"; d="scan'208";a="242403456" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2020 07:49:56 -0700 IronPort-SDR: d2wxgt3CN+Oiy9VhBeIb/8pALPqXAeOPMvHT9VDbPZkMYZ7Wob1hfujsRZQviIB4J0/Ez62DQL ah/BBKbpgZzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,387,1592895600"; d="scan'208";a="446930292" Received: from silpixa00399126.ir.intel.com ([10.237.222.27]) by orsmga004.jf.intel.com with ESMTP; 03 Sep 2020 07:49:55 -0700 From: Bruce Richardson <bruce.richardson@intel.com> To: dev@dpdk.org Cc: Ma Lihong <lihongx.ma@intel.com>, Hemant Agrawal <hemant.agrawal@nxp.com>, Bruce Richardson <bruce.richardson@intel.com> Date: Thu, 3 Sep 2020 15:49:41 +0100 Message-Id: <20200903144942.671870-3-bruce.richardson@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200903144942.671870-1-bruce.richardson@intel.com> References: <20200825114447.135030-1-bruce.richardson@intel.com> <20200903144942.671870-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v2 2/3] config: allow overriding some build defaults X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> In case a developer uses CFLAGS to set different default values for the defines in the rte_config.h file, use #ifndef / #endif guards around the setting of those values. For those lines just "defining" a macro without assigning it a value to be used by code, drop the value argument (where possible) to make it clearer that that is what is happening, since those don't need the #ifdef guard. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Tested-by: Lihong Ma <lihongx.ma@intel.com> --- config/rte_config.h | 110 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 99 insertions(+), 11 deletions(-) diff --git a/config/rte_config.h b/config/rte_config.h index 1c5a86d6a..f39da76c1 100644 --- a/config/rte_config.h +++ b/config/rte_config.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2017 Intel Corporation + * Copyright(c) 2017-2020 Intel Corporation */ /** @@ -20,10 +20,10 @@ /* legacy defines */ #ifdef RTE_EXEC_ENV_LINUX -#define RTE_EXEC_ENV_LINUXAPP 1 +#define RTE_EXEC_ENV_LINUXAPP #endif #ifdef RTE_EXEC_ENV_FREEBSD -#define RTE_EXEC_ENV_BSDAPP 1 +#define RTE_EXEC_ENV_BSDAPP #endif /* String that appears before the version number */ @@ -32,107 +32,195 @@ /****** library defines ********/ /* EAL defines */ +#define RTE_BACKTRACE +#ifndef RTE_MAX_HEAPS #define RTE_MAX_HEAPS 32 +#endif +#ifndef RTE_MAX_MEMSEG_LISTS #define RTE_MAX_MEMSEG_LISTS 128 +#endif +#ifndef RTE_MAX_MEMSEG_PER_LIST #define RTE_MAX_MEMSEG_PER_LIST 8192 +#endif +#ifndef RTE_MAX_MEM_MB_PER_LIST #define RTE_MAX_MEM_MB_PER_LIST 32768 +#endif +#ifndef RTE_MAX_MEMSEG_PER_TYPE #define RTE_MAX_MEMSEG_PER_TYPE 32768 +#endif +#ifndef RTE_MAX_MEM_MB_PER_TYPE #define RTE_MAX_MEM_MB_PER_TYPE 65536 +#endif +#ifndef RTE_MAX_MEMZONE #define RTE_MAX_MEMZONE 2560 +#endif +#ifndef RTE_MAX_TAILQ #define RTE_MAX_TAILQ 32 +#endif +#ifndef RTE_LOG_DP_LEVEL #define RTE_LOG_DP_LEVEL RTE_LOG_INFO -#define RTE_BACKTRACE 1 +#endif +#ifndef RTE_MAX_VFIO_CONTAINERS #define RTE_MAX_VFIO_CONTAINERS 64 +#endif /* bsd module defines */ +#ifndef RTE_CONTIGMEM_MAX_NUM_BUFS #define RTE_CONTIGMEM_MAX_NUM_BUFS 64 +#endif +#ifndef RTE_CONTIGMEM_DEFAULT_NUM_BUFS #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1 +#endif +#ifndef RTE_CONTIGMEM_DEFAULT_BUF_SIZE #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024) +#endif /* mempool defines */ +#ifndef RTE_MEMPOOL_CACHE_MAX_SIZE #define RTE_MEMPOOL_CACHE_MAX_SIZE 512 +#endif /* mbuf defines */ +#define RTE_MBUF_REFCNT_ATOMIC +#ifndef RTE_MBUF_DEFAULT_MEMPOOL_OPS #define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc" -#define RTE_MBUF_REFCNT_ATOMIC 1 +#endif +#ifndef RTE_PKTMBUF_HEADROOM #define RTE_PKTMBUF_HEADROOM 128 +#endif /* ether defines */ +#define RTE_ETHDEV_RXTX_CALLBACKS +#ifndef RTE_MAX_QUEUES_PER_PORT #define RTE_MAX_QUEUES_PER_PORT 1024 +#endif +#ifndef RTE_ETHDEV_QUEUE_STAT_CNTRS #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16 -#define RTE_ETHDEV_RXTX_CALLBACKS 1 +#endif /* cryptodev defines */ +#ifndef RTE_CRYPTO_MAX_DEVS #define RTE_CRYPTO_MAX_DEVS 64 +#endif +#ifndef RTE_CRYPTODEV_NAME_LEN #define RTE_CRYPTODEV_NAME_LEN 64 +#endif /* compressdev defines */ +#ifndef RTE_COMPRESS_MAX_DEVS #define RTE_COMPRESS_MAX_DEVS 64 +#endif /* regexdev defines */ +#ifndef RTE_MAX_REGEXDEV_DEVS #define RTE_MAX_REGEXDEV_DEVS 32 +#endif /* eventdev defines */ +#ifndef RTE_EVENT_MAX_DEVS #define RTE_EVENT_MAX_DEVS 16 +#endif +#ifndef RTE_EVENT_MAX_QUEUES_PER_DEV #define RTE_EVENT_MAX_QUEUES_PER_DEV 64 +#endif +#ifndef RTE_EVENT_TIMER_ADAPTER_NUM_MAX #define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32 +#endif +#ifndef RTE_EVENT_ETH_INTR_RING_SIZE #define RTE_EVENT_ETH_INTR_RING_SIZE 1024 +#endif +#ifndef RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE #define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32 +#endif +#ifndef RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE #define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32 +#endif /* rawdev defines */ +#ifndef RTE_RAWDEV_MAX_DEVS #define RTE_RAWDEV_MAX_DEVS 64 +#endif /* ip_fragmentation defines */ +#ifndef RTE_LIBRTE_IP_FRAG_MAX_FRAG #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4 +#endif // RTE_LIBRTE_IP_FRAG_TBL_STAT is not set /* rte_power defines */ +#ifndef RTE_MAX_LCORE_FREQS #define RTE_MAX_LCORE_FREQS 64 +#endif /* rte_sched defines */ // RTE_SCHED_RED is not set // RTE_SCHED_COLLECT_STATS is not set // RTE_SCHED_SUBPORT_TC_OV is not set +#ifndef RTE_SCHED_PORT_N_GRINDERS #define RTE_SCHED_PORT_N_GRINDERS 8 +#endif // RTE_SCHED_VECTOR is not set /* KNI defines */ -#define RTE_KNI_PREEMPT_DEFAULT 1 +#define RTE_KNI_PREEMPT_DEFAULT /* rte_graph defines */ -#define RTE_GRAPH_BURST_SIZE 256 #define RTE_LIBRTE_GRAPH_STATS 1 +#ifndef RTE_GRAPH_BURST_SIZE +#define RTE_GRAPH_BURST_SIZE 256 +#endif /****** driver defines ********/ /* QuickAssist device */ /* Max. number of QuickAssist devices which can be attached */ +#ifndef RTE_PMD_QAT_MAX_PCI_DEVICES #define RTE_PMD_QAT_MAX_PCI_DEVICES 48 +#endif +#ifndef RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16 +#endif +#ifndef RTE_PMD_QAT_COMP_IM_BUFFER_SIZE #define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536 +#endif /* virtio crypto defines */ +#ifndef RTE_MAX_VIRTIO_CRYPTO #define RTE_MAX_VIRTIO_CRYPTO 32 +#endif /* DPAA SEC max cryptodev devices*/ -#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 +#ifndef RTE_LIBRTE_DPAA_MAX_CRYPTODEV +#define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4 +#endif /* fm10k defines */ -#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1 +#define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE /* i40e defines */ -#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1 +#define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC // RTE_LIBRTE_I40E_16BYTE_RX_DESC is not set +#ifndef RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64 +#endif +#ifndef RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4 +#endif +#ifndef RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4 +#endif /* Ring net PMD settings */ +#ifndef RTE_PMD_RING_MAX_RX_RINGS #define RTE_PMD_RING_MAX_RX_RINGS 16 +#endif +#ifndef RTE_PMD_RING_MAX_TX_RINGS #define RTE_PMD_RING_MAX_TX_RINGS 16 +#endif /* QEDE PMD defines */ +#ifndef RTE_LIBRTE_QEDE_FW #define RTE_LIBRTE_QEDE_FW "" +#endif #endif /* _RTE_CONFIG_H_ */ -- 2.25.1