From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B2674A04AA; Tue, 8 Sep 2020 12:10:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 982AF1C0CE; Tue, 8 Sep 2020 12:10:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 463791C0CD for ; Tue, 8 Sep 2020 12:10:43 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 088A51Qu024501; Tue, 8 Sep 2020 03:10:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=IL9QhcwUTP2jiAq/x3C+yB4jbDToGunynREZzVTVHyk=; b=hMdIy8DjnyyM6akHoZtABF2SRra4svUkNq17YIZWNbt/l8GcXDjhQdGAdWzldyv7tqS/ 8l2I2ePN5z72Lg5YOfopW2MWD9KlIHURRyuj2B28Kd8Y2hiQYd4uq42zvTEDfHwWTfyq TXxcPkG7IH9HAKbazeOEuQaVxn+gHOUiZ7QRw0SLK1S+S24UBOkrDpRGg7z5Ekp0lWKa VuGdG8+2nF7kwp1DLFgFmNlf+Ou7RFndX5Y1rb2bmAvxMVuwPRPVgBMSS+Qmp6f/ySqS YOP3Au/442R4U6raTXjdqqGz8ScW6yg8Dz6U8idiMSDPIzkBa0Lp006DjNE4AWHy7sgs 3w== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 33ccvr1v13-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 08 Sep 2020 03:10:42 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Sep 2020 03:10:41 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Sep 2020 03:10:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Sep 2020 03:10:40 -0700 Received: from hyd1349.t110.caveonetworks.com (unknown [10.29.45.13]) by maili.marvell.com (Postfix) with ESMTP id 214733F703F; Tue, 8 Sep 2020 03:10:37 -0700 (PDT) From: Ankur Dwivedi To: CC: , , , , Ankur Dwivedi Date: Tue, 8 Sep 2020 15:39:55 +0530 Message-ID: <20200908100956.25868-3-adwivedi@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200908100956.25868-1-adwivedi@marvell.com> References: <20200908100956.25868-1-adwivedi@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-08_05:2020-09-08, 2020-09-08 signatures=0 Subject: [dpdk-dev] [PATCH 2/3] event/octeontx2: add crypto adapter framework X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The crypto adapter callback functions and associated data structures are added. Signed-off-by: Ankur Dwivedi --- drivers/crypto/octeontx2/meson.build | 4 +- .../crypto/octeontx2/otx2_crypto_adapter.c | 77 +++++++++++++++++++ .../crypto/octeontx2/otx2_crypto_adapter.h | 21 +++++ .../octeontx2/otx2_cryptodev_hw_access.h | 12 +++ drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 7 ++ .../rte_pmd_octeontx2_crypto_version.map | 10 +++ drivers/event/octeontx2/meson.build | 2 +- drivers/event/octeontx2/otx2_evdev.c | 5 ++ 8 files changed, 136 insertions(+), 2 deletions(-) create mode 100644 drivers/crypto/octeontx2/otx2_crypto_adapter.c create mode 100644 drivers/crypto/octeontx2/otx2_crypto_adapter.h diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index 148ec184a..063a553f2 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -10,6 +10,7 @@ deps += ['bus_pci'] deps += ['common_cpt'] deps += ['common_octeontx2'] deps += ['ethdev'] +deps += ['eventdev'] deps += ['security'] name = 'octeontx2_crypto' @@ -18,7 +19,8 @@ sources = files('otx2_cryptodev.c', 'otx2_cryptodev_hw_access.c', 'otx2_cryptodev_mbox.c', 'otx2_cryptodev_ops.c', - 'otx2_cryptodev_sec.c') + 'otx2_cryptodev_sec.c', + 'otx2_crypto_adapter.c') extra_flags = [] # This integrated controller runs only on a arm64 machine, remove 32bit warnings diff --git a/drivers/crypto/octeontx2/otx2_crypto_adapter.c b/drivers/crypto/octeontx2/otx2_crypto_adapter.c new file mode 100644 index 000000000..cfde7ec4f --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_crypto_adapter.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include + +#include "otx2_cryptodev_hw_access.h" +#include "otx2_cryptodev_qp.h" +#include "otx2_cryptodev_mbox.h" +#include "otx2_crypto_adapter.h" + +int +otx2_ca_caps_get(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, uint32_t *caps) +{ + RTE_SET_USED(dev); + RTE_SET_USED(cdev); + + *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | + RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW; + + return 0; +} + +int +otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, + int32_t queue_pair_id, const struct rte_event *event) +{ + union otx2_cpt_af_lf_ctl2 af_lf_ctl2; + struct otx2_cpt_qp *qp; + int ret; + + RTE_SET_USED(dev); + + qp = cdev->data->queue_pairs[queue_pair_id]; + + qp->ca_enable = 1; + rte_memcpy(&qp->ev, event, sizeof(struct rte_event)); + + ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + &af_lf_ctl2.u); + if (ret) + return ret; + + af_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get(); + ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + af_lf_ctl2.u); + + return ret; +} + +int +otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, + int32_t queue_pair_id) +{ + union otx2_cpt_af_lf_ctl2 af_lf_ctl2; + struct otx2_cpt_qp *qp; + int ret; + + RTE_SET_USED(dev); + + qp = cdev->data->queue_pairs[queue_pair_id]; + qp->ca_enable = 0; + memset(&qp->ev, 0, sizeof(struct rte_event)); + + ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + &af_lf_ctl2.u); + if (ret) + return ret; + + af_lf_ctl2.s.sso_pf_func = 0; + ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + af_lf_ctl2.u); + + return ret; +} diff --git a/drivers/crypto/octeontx2/otx2_crypto_adapter.h b/drivers/crypto/octeontx2/otx2_crypto_adapter.h new file mode 100644 index 000000000..c8f02c0af --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_crypto_adapter.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTO_ADAPTER_H_ +#define _OTX2_CRYPTO_ADAPTER_H_ + +__rte_internal +int otx2_ca_caps_get(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, uint32_t *caps); + +__rte_internal +int otx2_ca_qp_add(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, int32_t queue_pair_id, + const struct rte_event *event); + +__rte_internal +int otx2_ca_qp_del(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, int32_t queue_pair_id); + +#endif /* _OTX2_CRYPTO_ADAPTER_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h index 43db6a642..a435818e0 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -42,6 +42,7 @@ #define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3) #define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3) +#define OTX2_CPT_AF_LF_CTL2(a) (0x29000ull | (uint64_t)(a) << 3) #define OTX2_CPT_LF_BAR2(vf, q_id) \ ((vf)->otx2_dev.bar2 + \ @@ -110,6 +111,17 @@ union otx2_cpt_af_lf_ctl { } s; }; +union otx2_cpt_af_lf_ctl2 { + uint64_t u; + struct { + uint64_t exe_no_swap : 1; + uint64_t exe_ldwb : 1; + uint64_t reserved_2_31 : 30; + uint64_t sso_pf_func : 16; + uint64_t nix_pf_func : 16; + } s; +}; + union otx2_cpt_lf_q_grp_ptr { uint64_t u; struct { diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h index 9d48da45f..96ff4eb41 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h @@ -6,6 +6,7 @@ #define _OTX2_CRYPTODEV_QP_H_ #include +#include #include #include @@ -30,6 +31,12 @@ struct otx2_cpt_qp { /**< Metabuf info required to support operations on the queue pair */ rte_iova_t iq_dma_addr; /**< Instruction queue address */ + struct rte_event ev; + /**< Event information required for binding cryptodev queue to + * eventdev queue. Used by crypto adapter. + */ + uint8_t ca_enable; + /**< Set when queue pair is added to crypto adapter */ }; #endif /* _OTX2_CRYPTODEV_QP_H_ */ diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map index 4a76d1d52..b47a7ad3e 100644 --- a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map +++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map @@ -1,3 +1,13 @@ DPDK_21 { local: *; }; + +INTERNAL { + global: + + otx2_ca_caps_get; + otx2_ca_qp_add; + otx2_ca_qp_del; + + local: *; +}; diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build index 0ade51cec..8585c54e4 100644 --- a/drivers/event/octeontx2/meson.build +++ b/drivers/event/octeontx2/meson.build @@ -24,6 +24,6 @@ foreach flag: extra_flags endif endforeach -deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2'] +deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2', 'pmd_octeontx2_crypto'] includes += include_directories('../../crypto/octeontx2') diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index b8b57c388..fe21787b6 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -12,6 +12,7 @@ #include #include +#include "otx2_crypto_adapter.h" #include "otx2_evdev_stats.h" #include "otx2_evdev.h" #include "otx2_irq.h" @@ -1587,6 +1588,10 @@ static struct rte_eventdev_ops otx2_sso_ops = { .timer_adapter_caps_get = otx2_tim_caps_get, + .crypto_adapter_caps_get = otx2_ca_caps_get, + .crypto_adapter_queue_pair_add = otx2_ca_qp_add, + .crypto_adapter_queue_pair_del = otx2_ca_qp_del, + .xstats_get = otx2_sso_xstats_get, .xstats_reset = otx2_sso_xstats_reset, .xstats_get_names = otx2_sso_xstats_get_names, -- 2.28.0