From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from dpdk.org (dpdk.org [92.243.14.124])
by inbox.dpdk.org (Postfix) with ESMTP id 1B550A04B1;
Tue, 8 Sep 2020 22:22:28 +0200 (CEST)
Received: from [92.243.14.124] (localhost [127.0.0.1])
by dpdk.org (Postfix) with ESMTP id C2C921C1DD;
Tue, 8 Sep 2020 22:19:29 +0200 (CEST)
Received: from mga02.intel.com (mga02.intel.com [134.134.136.20])
by dpdk.org (Postfix) with ESMTP id 4A6491C0D9
for <dev@dpdk.org>; Tue, 8 Sep 2020 22:19:02 +0200 (CEST)
IronPort-SDR: 3dyjTf9bhFRKB2OP7VQTuN5Ll0D1LDPTQnzYNMKnLmsxq90RbpWuHiSYTIDotEaz4hqD15L4aX
vOAQYE612jbg==
X-IronPort-AV: E=McAfee;i="6000,8403,9738"; a="145939410"
X-IronPort-AV: E=Sophos;i="5.76,407,1592895600"; d="scan'208";a="145939410"
X-Amp-Result: SKIPPED(no attachment in message)
X-Amp-File-Uploaded: False
Received: from fmsmga006.fm.intel.com ([10.253.24.20])
by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
08 Sep 2020 13:18:50 -0700
IronPort-SDR: UTqY1ffw/fwQ4OF8o+UHM0aWOy1cb6CKPoHdfuu5iSjczyyyIbri2QRSuZtPH9Exd4qyKHLK2u
1XZgkixbOtFg==
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.76,406,1592895600"; d="scan'208";a="504493452"
Received: from silpixa00400573.ir.intel.com (HELO
silpixa00400573.ger.corp.intel.com) ([10.237.223.107])
by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:50 -0700
From: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
To: dev@dpdk.org
Date: Tue, 8 Sep 2020 21:18:08 +0100
Message-Id: <20200908201830.74206-20-cristian.dumitrescu@intel.com>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20200908201830.74206-1-cristian.dumitrescu@intel.com>
References: <20200907214032.95052-2-cristian.dumitrescu@intel.com>
<20200908201830.74206-1-cristian.dumitrescu@intel.com>
Subject: [dpdk-dev] [PATCH v3 19/41] pipeline: introduce SWX or instruction
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
The or (i.e. bitwise or) instruction source can be header field (H),
meta-data field (M), extern object (E) or function (F) mailbox field,
table entry action data field (T) or immediate value (I). The
destination is HMEF.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---
lib/librte_pipeline/rte_swx_pipeline.c | 114 +++++++++++++++++++++++++
1 file changed, 114 insertions(+)
diff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c
index fe44e520c..88d1b2d1a 100644
--- a/lib/librte_pipeline/rte_swx_pipeline.c
+++ b/lib/librte_pipeline/rte_swx_pipeline.c
@@ -311,6 +311,14 @@ enum instruction_type {
INSTR_ALU_AND, /* dst = MEF, src = MEFT */
INSTR_ALU_AND_S, /* (dst, src) = (MEF, H) or (dst, src) = (H, MEFT) */
INSTR_ALU_AND_I, /* dst = HMEF, src = I */
+
+ /* or dst src
+ * dst |= src
+ * dst = HMEF, src = HMEFTI
+ */
+ INSTR_ALU_OR, /* dst = MEF, src = MEFT */
+ INSTR_ALU_OR_S, /* (dst, src) = (MEF, H) or (dst, src) = (H, MEFT) */
+ INSTR_ALU_OR_I, /* dst = HMEF, src = I */
};
struct instr_operand {
@@ -3127,6 +3135,55 @@ instr_alu_and_translate(struct rte_swx_pipeline *p,
return 0;
}
+static int
+instr_alu_or_translate(struct rte_swx_pipeline *p,
+ struct action *action,
+ char **tokens,
+ int n_tokens,
+ struct instruction *instr,
+ struct instruction_data *data __rte_unused)
+{
+ char *dst = tokens[1], *src = tokens[2];
+ struct field *fdst, *fsrc;
+ uint32_t dst_struct_id, src_struct_id, src_val;
+
+ CHECK(n_tokens == 3, EINVAL);
+
+ fdst = struct_field_parse(p, NULL, dst, &dst_struct_id);
+ CHECK(fdst, EINVAL);
+
+ /* OR or OR_S. */
+ fsrc = struct_field_parse(p, action, src, &src_struct_id);
+ if (fsrc) {
+ instr->type = INSTR_ALU_OR;
+ if ((dst[0] == 'h' && src[0] != 'h') ||
+ (dst[0] != 'h' && src[0] == 'h'))
+ instr->type = INSTR_ALU_OR_S;
+
+ instr->alu.dst.struct_id = (uint8_t)dst_struct_id;
+ instr->alu.dst.n_bits = fdst->n_bits;
+ instr->alu.dst.offset = fdst->offset / 8;
+ instr->alu.src.struct_id = (uint8_t)src_struct_id;
+ instr->alu.src.n_bits = fsrc->n_bits;
+ instr->alu.src.offset = fsrc->offset / 8;
+ return 0;
+ }
+
+ /* OR_I. */
+ src_val = strtoul(src, &src, 0);
+ CHECK(!src[0], EINVAL);
+
+ if (dst[0] == 'h')
+ src_val = htonl(src_val);
+
+ instr->type = INSTR_ALU_OR_I;
+ instr->alu.dst.struct_id = (uint8_t)dst_struct_id;
+ instr->alu.dst.n_bits = fdst->n_bits;
+ instr->alu.dst.offset = fdst->offset / 8;
+ instr->alu.src_val = (uint32_t)src_val;
+ return 0;
+}
+
static inline void
instr_alu_add_exec(struct rte_swx_pipeline *p)
{
@@ -3352,6 +3409,51 @@ instr_alu_and_i_exec(struct rte_swx_pipeline *p)
thread_ip_inc(p);
}
+static inline void
+instr_alu_or_exec(struct rte_swx_pipeline *p)
+{
+ struct thread *t = &p->threads[p->thread_id];
+ struct instruction *ip = t->ip;
+
+ TRACE("[Thread %2u] or\n", p->thread_id);
+
+ /* Structs. */
+ ALU(t, ip, |);
+
+ /* Thread. */
+ thread_ip_inc(p);
+}
+
+static inline void
+instr_alu_or_s_exec(struct rte_swx_pipeline *p)
+{
+ struct thread *t = &p->threads[p->thread_id];
+ struct instruction *ip = t->ip;
+
+ TRACE("[Thread %2u] or (s)\n", p->thread_id);
+
+ /* Structs. */
+ ALU_S(t, ip, |);
+
+ /* Thread. */
+ thread_ip_inc(p);
+}
+
+static inline void
+instr_alu_or_i_exec(struct rte_swx_pipeline *p)
+{
+ struct thread *t = &p->threads[p->thread_id];
+ struct instruction *ip = t->ip;
+
+ TRACE("[Thread %2u] or (i)\n", p->thread_id);
+
+ /* Structs. */
+ ALU_I(t, ip, |);
+
+ /* Thread. */
+ thread_ip_inc(p);
+}
+
static inline void
instr_alu_ckadd_field_exec(struct rte_swx_pipeline *p)
{
@@ -3727,6 +3829,14 @@ instr_translate(struct rte_swx_pipeline *p,
instr,
data);
+ if (!strcmp(tokens[tpos], "or"))
+ return instr_alu_or_translate(p,
+ action,
+ &tokens[tpos],
+ n_tokens - tpos,
+ instr,
+ data);
+
CHECK(0, EINVAL);
}
@@ -3907,6 +4017,10 @@ static instr_exec_t instruction_table[] = {
[INSTR_ALU_AND] = instr_alu_and_exec,
[INSTR_ALU_AND_S] = instr_alu_and_s_exec,
[INSTR_ALU_AND_I] = instr_alu_and_i_exec,
+
+ [INSTR_ALU_OR] = instr_alu_or_exec,
+ [INSTR_ALU_OR_S] = instr_alu_or_s_exec,
+ [INSTR_ALU_OR_I] = instr_alu_or_i_exec,
};
static inline void
--
2.17.1