From: Somnath Kotur <somnath.kotur@broadcom.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com,
Kishore Padmanabha <kishore.padmanabha@broadcom.com>,
Michael Baucom <michael.baucom@broadcom.com>
Subject: [dpdk-dev] [PATCH 1/8] net/bnxt: add support for decap action for ipv6 VXLAN flows
Date: Tue, 22 Sep 2020 12:36:25 +0530 [thread overview]
Message-ID: <20200922070632.17706-2-somnath.kotur@broadcom.com> (raw)
In-Reply-To: <20200922070632.17706-1-somnath.kotur@broadcom.com>
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Add a template to support ipv6 VXLAN flows to enable support for
vxlan decap for those flows.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 1206 +++++++++++++++--------
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 40 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h | 118 +--
3 files changed, 852 insertions(+), 512 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index a6dd321..7f9ba96 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -109,84 +109,106 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_065d] = 98,
[BNXT_ULP_CLASS_HID_0623] = 99,
[BNXT_ULP_CLASS_HID_00eb] = 100,
- [BNXT_ULP_CLASS_HID_0768] = 101,
- [BNXT_ULP_CLASS_HID_073c] = 102,
- [BNXT_ULP_CLASS_HID_04bc] = 103,
- [BNXT_ULP_CLASS_HID_0442] = 104,
- [BNXT_ULP_CLASS_HID_050a] = 105,
- [BNXT_ULP_CLASS_HID_06ba] = 106,
- [BNXT_ULP_CLASS_HID_0472] = 107,
- [BNXT_ULP_CLASS_HID_0700] = 108,
- [BNXT_ULP_CLASS_HID_04c8] = 109,
- [BNXT_ULP_CLASS_HID_0678] = 110,
- [BNXT_ULP_CLASS_HID_064f] = 111,
- [BNXT_ULP_CLASS_HID_051d] = 112,
- [BNXT_ULP_CLASS_HID_06a5] = 113,
- [BNXT_ULP_CLASS_HID_0455] = 114,
- [BNXT_ULP_CLASS_HID_04bd] = 115,
- [BNXT_ULP_CLASS_HID_0443] = 116,
- [BNXT_ULP_CLASS_HID_050b] = 117,
- [BNXT_ULP_CLASS_HID_06bb] = 118,
- [BNXT_ULP_CLASS_HID_050d] = 119,
- [BNXT_ULP_CLASS_HID_04d3] = 120,
- [BNXT_ULP_CLASS_HID_059b] = 121,
- [BNXT_ULP_CLASS_HID_070b] = 122,
- [BNXT_ULP_CLASS_HID_0473] = 123,
- [BNXT_ULP_CLASS_HID_0701] = 124,
- [BNXT_ULP_CLASS_HID_04c9] = 125,
- [BNXT_ULP_CLASS_HID_0679] = 126,
- [BNXT_ULP_CLASS_HID_048b] = 127,
- [BNXT_ULP_CLASS_HID_0749] = 128,
- [BNXT_ULP_CLASS_HID_05f1] = 129,
- [BNXT_ULP_CLASS_HID_04b7] = 130,
- [BNXT_ULP_CLASS_HID_049b] = 131,
- [BNXT_ULP_CLASS_HID_0759] = 132,
- [BNXT_ULP_CLASS_HID_05e1] = 133,
- [BNXT_ULP_CLASS_HID_04a7] = 134,
- [BNXT_ULP_CLASS_HID_0301] = 135,
- [BNXT_ULP_CLASS_HID_07f9] = 136,
- [BNXT_ULP_CLASS_HID_0397] = 137,
- [BNXT_ULP_CLASS_HID_068f] = 138,
- [BNXT_ULP_CLASS_HID_02f1] = 139,
- [BNXT_ULP_CLASS_HID_0609] = 140,
- [BNXT_ULP_CLASS_HID_0267] = 141,
- [BNXT_ULP_CLASS_HID_077f] = 142,
- [BNXT_ULP_CLASS_HID_01e1] = 143,
- [BNXT_ULP_CLASS_HID_0329] = 144,
- [BNXT_ULP_CLASS_HID_01c1] = 145,
- [BNXT_ULP_CLASS_HID_0309] = 146,
- [BNXT_ULP_CLASS_HID_01d1] = 147,
- [BNXT_ULP_CLASS_HID_0319] = 148,
- [BNXT_ULP_CLASS_HID_01e2] = 149,
- [BNXT_ULP_CLASS_HID_032a] = 150,
- [BNXT_ULP_CLASS_HID_0650] = 151,
- [BNXT_ULP_CLASS_HID_0198] = 152,
- [BNXT_ULP_CLASS_HID_01c2] = 153,
- [BNXT_ULP_CLASS_HID_030a] = 154,
- [BNXT_ULP_CLASS_HID_0670] = 155,
- [BNXT_ULP_CLASS_HID_01b8] = 156,
- [BNXT_ULP_CLASS_HID_01d2] = 157,
- [BNXT_ULP_CLASS_HID_031a] = 158,
- [BNXT_ULP_CLASS_HID_0660] = 159,
- [BNXT_ULP_CLASS_HID_01a8] = 160,
- [BNXT_ULP_CLASS_HID_01dd] = 161,
- [BNXT_ULP_CLASS_HID_0315] = 162,
- [BNXT_ULP_CLASS_HID_003d] = 163,
- [BNXT_ULP_CLASS_HID_02f5] = 164,
- [BNXT_ULP_CLASS_HID_01cd] = 165,
- [BNXT_ULP_CLASS_HID_0305] = 166,
- [BNXT_ULP_CLASS_HID_01de] = 167,
- [BNXT_ULP_CLASS_HID_0316] = 168,
- [BNXT_ULP_CLASS_HID_066c] = 169,
- [BNXT_ULP_CLASS_HID_01a4] = 170,
- [BNXT_ULP_CLASS_HID_003e] = 171,
- [BNXT_ULP_CLASS_HID_02f6] = 172,
- [BNXT_ULP_CLASS_HID_078c] = 173,
- [BNXT_ULP_CLASS_HID_0044] = 174,
- [BNXT_ULP_CLASS_HID_01ce] = 175,
- [BNXT_ULP_CLASS_HID_0306] = 176,
- [BNXT_ULP_CLASS_HID_067c] = 177,
- [BNXT_ULP_CLASS_HID_01b4] = 178
+ [BNXT_ULP_CLASS_HID_04bc] = 101,
+ [BNXT_ULP_CLASS_HID_0442] = 102,
+ [BNXT_ULP_CLASS_HID_050a] = 103,
+ [BNXT_ULP_CLASS_HID_06ba] = 104,
+ [BNXT_ULP_CLASS_HID_0472] = 105,
+ [BNXT_ULP_CLASS_HID_0700] = 106,
+ [BNXT_ULP_CLASS_HID_04c8] = 107,
+ [BNXT_ULP_CLASS_HID_0678] = 108,
+ [BNXT_ULP_CLASS_HID_061f] = 109,
+ [BNXT_ULP_CLASS_HID_05ad] = 110,
+ [BNXT_ULP_CLASS_HID_06a5] = 111,
+ [BNXT_ULP_CLASS_HID_0455] = 112,
+ [BNXT_ULP_CLASS_HID_05dd] = 113,
+ [BNXT_ULP_CLASS_HID_0563] = 114,
+ [BNXT_ULP_CLASS_HID_059b] = 115,
+ [BNXT_ULP_CLASS_HID_070b] = 116,
+ [BNXT_ULP_CLASS_HID_04bd] = 117,
+ [BNXT_ULP_CLASS_HID_0443] = 118,
+ [BNXT_ULP_CLASS_HID_050b] = 119,
+ [BNXT_ULP_CLASS_HID_06bb] = 120,
+ [BNXT_ULP_CLASS_HID_0473] = 121,
+ [BNXT_ULP_CLASS_HID_0701] = 122,
+ [BNXT_ULP_CLASS_HID_04c9] = 123,
+ [BNXT_ULP_CLASS_HID_0679] = 124,
+ [BNXT_ULP_CLASS_HID_05e2] = 125,
+ [BNXT_ULP_CLASS_HID_00b0] = 126,
+ [BNXT_ULP_CLASS_HID_0648] = 127,
+ [BNXT_ULP_CLASS_HID_03f8] = 128,
+ [BNXT_ULP_CLASS_HID_02ea] = 129,
+ [BNXT_ULP_CLASS_HID_05b8] = 130,
+ [BNXT_ULP_CLASS_HID_0370] = 131,
+ [BNXT_ULP_CLASS_HID_00e0] = 132,
+ [BNXT_ULP_CLASS_HID_0745] = 133,
+ [BNXT_ULP_CLASS_HID_0213] = 134,
+ [BNXT_ULP_CLASS_HID_031b] = 135,
+ [BNXT_ULP_CLASS_HID_008b] = 136,
+ [BNXT_ULP_CLASS_HID_044d] = 137,
+ [BNXT_ULP_CLASS_HID_071b] = 138,
+ [BNXT_ULP_CLASS_HID_0003] = 139,
+ [BNXT_ULP_CLASS_HID_05b3] = 140,
+ [BNXT_ULP_CLASS_HID_05e3] = 141,
+ [BNXT_ULP_CLASS_HID_00b1] = 142,
+ [BNXT_ULP_CLASS_HID_0649] = 143,
+ [BNXT_ULP_CLASS_HID_03f9] = 144,
+ [BNXT_ULP_CLASS_HID_02eb] = 145,
+ [BNXT_ULP_CLASS_HID_05b9] = 146,
+ [BNXT_ULP_CLASS_HID_0371] = 147,
+ [BNXT_ULP_CLASS_HID_00e1] = 148,
+ [BNXT_ULP_CLASS_HID_048b] = 149,
+ [BNXT_ULP_CLASS_HID_0749] = 150,
+ [BNXT_ULP_CLASS_HID_05f1] = 151,
+ [BNXT_ULP_CLASS_HID_04b7] = 152,
+ [BNXT_ULP_CLASS_HID_049b] = 153,
+ [BNXT_ULP_CLASS_HID_0759] = 154,
+ [BNXT_ULP_CLASS_HID_05e1] = 155,
+ [BNXT_ULP_CLASS_HID_04a7] = 156,
+ [BNXT_ULP_CLASS_HID_0301] = 157,
+ [BNXT_ULP_CLASS_HID_07f9] = 158,
+ [BNXT_ULP_CLASS_HID_0397] = 159,
+ [BNXT_ULP_CLASS_HID_068f] = 160,
+ [BNXT_ULP_CLASS_HID_02f1] = 161,
+ [BNXT_ULP_CLASS_HID_0609] = 162,
+ [BNXT_ULP_CLASS_HID_0267] = 163,
+ [BNXT_ULP_CLASS_HID_077f] = 164,
+ [BNXT_ULP_CLASS_HID_01e1] = 165,
+ [BNXT_ULP_CLASS_HID_0329] = 166,
+ [BNXT_ULP_CLASS_HID_01c1] = 167,
+ [BNXT_ULP_CLASS_HID_0309] = 168,
+ [BNXT_ULP_CLASS_HID_01d1] = 169,
+ [BNXT_ULP_CLASS_HID_0319] = 170,
+ [BNXT_ULP_CLASS_HID_01e2] = 171,
+ [BNXT_ULP_CLASS_HID_032a] = 172,
+ [BNXT_ULP_CLASS_HID_0650] = 173,
+ [BNXT_ULP_CLASS_HID_0198] = 174,
+ [BNXT_ULP_CLASS_HID_01c2] = 175,
+ [BNXT_ULP_CLASS_HID_030a] = 176,
+ [BNXT_ULP_CLASS_HID_0670] = 177,
+ [BNXT_ULP_CLASS_HID_01b8] = 178,
+ [BNXT_ULP_CLASS_HID_01d2] = 179,
+ [BNXT_ULP_CLASS_HID_031a] = 180,
+ [BNXT_ULP_CLASS_HID_0660] = 181,
+ [BNXT_ULP_CLASS_HID_01a8] = 182,
+ [BNXT_ULP_CLASS_HID_01dd] = 183,
+ [BNXT_ULP_CLASS_HID_0315] = 184,
+ [BNXT_ULP_CLASS_HID_003d] = 185,
+ [BNXT_ULP_CLASS_HID_02f5] = 186,
+ [BNXT_ULP_CLASS_HID_01cd] = 187,
+ [BNXT_ULP_CLASS_HID_0305] = 188,
+ [BNXT_ULP_CLASS_HID_01de] = 189,
+ [BNXT_ULP_CLASS_HID_0316] = 190,
+ [BNXT_ULP_CLASS_HID_066c] = 191,
+ [BNXT_ULP_CLASS_HID_01a4] = 192,
+ [BNXT_ULP_CLASS_HID_003e] = 193,
+ [BNXT_ULP_CLASS_HID_02f6] = 194,
+ [BNXT_ULP_CLASS_HID_078c] = 195,
+ [BNXT_ULP_CLASS_HID_0044] = 196,
+ [BNXT_ULP_CLASS_HID_01ce] = 197,
+ [BNXT_ULP_CLASS_HID_0306] = 198,
+ [BNXT_ULP_CLASS_HID_067c] = 199,
+ [BNXT_ULP_CLASS_HID_01b4] = 200
};
struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
@@ -1921,134 +1943,526 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.wc_pri = 11
},
[101] = {
- .class_hid = BNXT_ULP_CLASS_HID_0768,
+ .class_hid = BNXT_ULP_CLASS_HID_04bc,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 0
+ },
+ [102] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0442,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 1
+ },
+ [103] = {
+ .class_hid = BNXT_ULP_CLASS_HID_050a,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 2
+ },
+ [104] = {
+ .class_hid = BNXT_ULP_CLASS_HID_06ba,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 3
+ },
+ [105] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0472,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 4
+ },
+ [106] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0700,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 5
+ },
+ [107] = {
+ .class_hid = BNXT_ULP_CLASS_HID_04c8,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 6
+ },
+ [108] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0678,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 7
+ },
+ [109] = {
+ .class_hid = BNXT_ULP_CLASS_HID_061f,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 8
+ },
+ [110] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05ad,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 9
+ },
+ [111] = {
+ .class_hid = BNXT_ULP_CLASS_HID_06a5,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 10
+ },
+ [112] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0455,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 11
+ },
+ [113] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05dd,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 12
+ },
+ [114] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0563,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 13
+ },
+ [115] = {
+ .class_hid = BNXT_ULP_CLASS_HID_059b,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 14
+ },
+ [116] = {
+ .class_hid = BNXT_ULP_CLASS_HID_070b,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 15
+ },
+ [117] = {
+ .class_hid = BNXT_ULP_CLASS_HID_04bd,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 16
+ },
+ [118] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0443,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 17
+ },
+ [119] = {
+ .class_hid = BNXT_ULP_CLASS_HID_050b,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF16_BITMASK_I_ETH_TYPE |
- BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
- BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 16,
- .wc_pri = 0
+ .wc_pri = 18
},
- [102] = {
- .class_hid = BNXT_ULP_CLASS_HID_073c,
+ [120] = {
+ .class_hid = BNXT_ULP_CLASS_HID_06bb,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
- BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
- BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
- BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 16,
- .wc_pri = 1
+ .wc_pri = 19
},
- [103] = {
- .class_hid = BNXT_ULP_CLASS_HID_04bc,
+ [121] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0473,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 20
+ },
+ [122] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0701,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 21
+ },
+ [123] = {
+ .class_hid = BNXT_ULP_CLASS_HID_04c9,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
+ BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 22
+ },
+ [124] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0679,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_OO_VLAN |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
+ BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+ BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+ .class_tid = 16,
+ .wc_pri = 23
+ },
+ [125] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05e2,
+ .hdr_sig = { .bits =
+ BNXT_ULP_HDR_BIT_O_ETH |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
+ BNXT_ULP_HDR_BIT_O_UDP |
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 0
},
- [104] = {
- .class_hid = BNXT_ULP_CLASS_HID_0442,
+ [126] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00b0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 1
},
- [105] = {
- .class_hid = BNXT_ULP_CLASS_HID_050a,
+ [127] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0648,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 2
},
- [106] = {
- .class_hid = BNXT_ULP_CLASS_HID_06ba,
+ [128] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03f8,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 3
},
- [107] = {
- .class_hid = BNXT_ULP_CLASS_HID_0472,
+ [129] = {
+ .class_hid = BNXT_ULP_CLASS_HID_02ea,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2056,109 +2470,109 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 4
},
- [108] = {
- .class_hid = BNXT_ULP_CLASS_HID_0700,
+ [130] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05b8,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 5
},
- [109] = {
- .class_hid = BNXT_ULP_CLASS_HID_04c8,
+ [131] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0370,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 6
},
- [110] = {
- .class_hid = BNXT_ULP_CLASS_HID_0678,
+ [132] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00e0,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 7
},
- [111] = {
- .class_hid = BNXT_ULP_CLASS_HID_064f,
+ [133] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0745,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 8
},
- [112] = {
- .class_hid = BNXT_ULP_CLASS_HID_051d,
+ [134] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0213,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 9
},
- [113] = {
- .class_hid = BNXT_ULP_CLASS_HID_06a5,
+ [135] = {
+ .class_hid = BNXT_ULP_CLASS_HID_031b,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2166,114 +2580,114 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 10
},
- [114] = {
- .class_hid = BNXT_ULP_CLASS_HID_0455,
+ [136] = {
+ .class_hid = BNXT_ULP_CLASS_HID_008b,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 11
},
- [115] = {
- .class_hid = BNXT_ULP_CLASS_HID_04bd,
+ [137] = {
+ .class_hid = BNXT_ULP_CLASS_HID_044d,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 12
},
- [116] = {
- .class_hid = BNXT_ULP_CLASS_HID_0443,
+ [138] = {
+ .class_hid = BNXT_ULP_CLASS_HID_071b,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 13
},
- [117] = {
- .class_hid = BNXT_ULP_CLASS_HID_050b,
+ [139] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0003,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 14
},
- [118] = {
- .class_hid = BNXT_ULP_CLASS_HID_06bb,
+ [140] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05b3,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 15
},
- [119] = {
- .class_hid = BNXT_ULP_CLASS_HID_050d,
+ [141] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05e3,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2281,75 +2695,75 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 16
},
- [120] = {
- .class_hid = BNXT_ULP_CLASS_HID_04d3,
+ [142] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00b1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 17
},
- [121] = {
- .class_hid = BNXT_ULP_CLASS_HID_059b,
+ [143] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0649,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 18
},
- [122] = {
- .class_hid = BNXT_ULP_CLASS_HID_070b,
+ [144] = {
+ .class_hid = BNXT_ULP_CLASS_HID_03f9,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 19
},
- [123] = {
- .class_hid = BNXT_ULP_CLASS_HID_0473,
+ [145] = {
+ .class_hid = BNXT_ULP_CLASS_HID_02eb,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2357,66 +2771,66 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 20
},
- [124] = {
- .class_hid = BNXT_ULP_CLASS_HID_0701,
+ [146] = {
+ .class_hid = BNXT_ULP_CLASS_HID_05b9,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 21
},
- [125] = {
- .class_hid = BNXT_ULP_CLASS_HID_04c9,
+ [147] = {
+ .class_hid = BNXT_ULP_CLASS_HID_0371,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 22
},
- [126] = {
- .class_hid = BNXT_ULP_CLASS_HID_0679,
+ [148] = {
+ .class_hid = BNXT_ULP_CLASS_HID_00e1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_OO_VLAN |
- BNXT_ULP_HDR_BIT_O_IPV4 |
+ BNXT_ULP_HDR_BIT_O_IPV6 |
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_HDR_BIT_T_VXLAN |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
.class_tid = 17,
.wc_pri = 23
},
- [127] = {
+ [149] = {
.class_hid = BNXT_ULP_CLASS_HID_048b,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2434,7 +2848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 18,
.wc_pri = 0
},
- [128] = {
+ [150] = {
.class_hid = BNXT_ULP_CLASS_HID_0749,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2451,7 +2865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 18,
.wc_pri = 1
},
- [129] = {
+ [151] = {
.class_hid = BNXT_ULP_CLASS_HID_05f1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2468,7 +2882,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 18,
.wc_pri = 2
},
- [130] = {
+ [152] = {
.class_hid = BNXT_ULP_CLASS_HID_04b7,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2484,7 +2898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 18,
.wc_pri = 3
},
- [131] = {
+ [153] = {
.class_hid = BNXT_ULP_CLASS_HID_049b,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2502,7 +2916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 19,
.wc_pri = 0
},
- [132] = {
+ [154] = {
.class_hid = BNXT_ULP_CLASS_HID_0759,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2519,7 +2933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 19,
.wc_pri = 1
},
- [133] = {
+ [155] = {
.class_hid = BNXT_ULP_CLASS_HID_05e1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2536,7 +2950,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 19,
.wc_pri = 2
},
- [134] = {
+ [156] = {
.class_hid = BNXT_ULP_CLASS_HID_04a7,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2552,7 +2966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 19,
.wc_pri = 3
},
- [135] = {
+ [157] = {
.class_hid = BNXT_ULP_CLASS_HID_0301,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2570,7 +2984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 20,
.wc_pri = 0
},
- [136] = {
+ [158] = {
.class_hid = BNXT_ULP_CLASS_HID_07f9,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2587,7 +3001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 20,
.wc_pri = 1
},
- [137] = {
+ [159] = {
.class_hid = BNXT_ULP_CLASS_HID_0397,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2604,7 +3018,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 20,
.wc_pri = 2
},
- [138] = {
+ [160] = {
.class_hid = BNXT_ULP_CLASS_HID_068f,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2620,7 +3034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 20,
.wc_pri = 3
},
- [139] = {
+ [161] = {
.class_hid = BNXT_ULP_CLASS_HID_02f1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2638,7 +3052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 21,
.wc_pri = 0
},
- [140] = {
+ [162] = {
.class_hid = BNXT_ULP_CLASS_HID_0609,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2655,7 +3069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 21,
.wc_pri = 1
},
- [141] = {
+ [163] = {
.class_hid = BNXT_ULP_CLASS_HID_0267,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2672,7 +3086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 21,
.wc_pri = 2
},
- [142] = {
+ [164] = {
.class_hid = BNXT_ULP_CLASS_HID_077f,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2688,7 +3102,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 21,
.wc_pri = 3
},
- [143] = {
+ [165] = {
.class_hid = BNXT_ULP_CLASS_HID_01e1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2702,7 +3116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 0
},
- [144] = {
+ [166] = {
.class_hid = BNXT_ULP_CLASS_HID_0329,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2715,7 +3129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 1
},
- [145] = {
+ [167] = {
.class_hid = BNXT_ULP_CLASS_HID_01c1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2730,7 +3144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 2
},
- [146] = {
+ [168] = {
.class_hid = BNXT_ULP_CLASS_HID_0309,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2744,7 +3158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 3
},
- [147] = {
+ [169] = {
.class_hid = BNXT_ULP_CLASS_HID_01d1,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2759,7 +3173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 4
},
- [148] = {
+ [170] = {
.class_hid = BNXT_ULP_CLASS_HID_0319,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2773,7 +3187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 5
},
- [149] = {
+ [171] = {
.class_hid = BNXT_ULP_CLASS_HID_01e2,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2788,7 +3202,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 6
},
- [150] = {
+ [172] = {
.class_hid = BNXT_ULP_CLASS_HID_032a,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2802,7 +3216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 7
},
- [151] = {
+ [173] = {
.class_hid = BNXT_ULP_CLASS_HID_0650,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2818,7 +3232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 8
},
- [152] = {
+ [174] = {
.class_hid = BNXT_ULP_CLASS_HID_0198,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2833,7 +3247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 9
},
- [153] = {
+ [175] = {
.class_hid = BNXT_ULP_CLASS_HID_01c2,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2849,7 +3263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 10
},
- [154] = {
+ [176] = {
.class_hid = BNXT_ULP_CLASS_HID_030a,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2864,7 +3278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 11
},
- [155] = {
+ [177] = {
.class_hid = BNXT_ULP_CLASS_HID_0670,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2881,7 +3295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 12
},
- [156] = {
+ [178] = {
.class_hid = BNXT_ULP_CLASS_HID_01b8,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2897,7 +3311,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 13
},
- [157] = {
+ [179] = {
.class_hid = BNXT_ULP_CLASS_HID_01d2,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2913,7 +3327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 14
},
- [158] = {
+ [180] = {
.class_hid = BNXT_ULP_CLASS_HID_031a,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2928,7 +3342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 15
},
- [159] = {
+ [181] = {
.class_hid = BNXT_ULP_CLASS_HID_0660,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2945,7 +3359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 16
},
- [160] = {
+ [182] = {
.class_hid = BNXT_ULP_CLASS_HID_01a8,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2961,7 +3375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 22,
.wc_pri = 17
},
- [161] = {
+ [183] = {
.class_hid = BNXT_ULP_CLASS_HID_01dd,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2975,7 +3389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 0
},
- [162] = {
+ [184] = {
.class_hid = BNXT_ULP_CLASS_HID_0315,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -2988,7 +3402,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 1
},
- [163] = {
+ [185] = {
.class_hid = BNXT_ULP_CLASS_HID_003d,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3003,7 +3417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 2
},
- [164] = {
+ [186] = {
.class_hid = BNXT_ULP_CLASS_HID_02f5,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3017,7 +3431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 3
},
- [165] = {
+ [187] = {
.class_hid = BNXT_ULP_CLASS_HID_01cd,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3032,7 +3446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 4
},
- [166] = {
+ [188] = {
.class_hid = BNXT_ULP_CLASS_HID_0305,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3046,7 +3460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 5
},
- [167] = {
+ [189] = {
.class_hid = BNXT_ULP_CLASS_HID_01de,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3061,7 +3475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 6
},
- [168] = {
+ [190] = {
.class_hid = BNXT_ULP_CLASS_HID_0316,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3075,7 +3489,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 7
},
- [169] = {
+ [191] = {
.class_hid = BNXT_ULP_CLASS_HID_066c,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3091,7 +3505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 8
},
- [170] = {
+ [192] = {
.class_hid = BNXT_ULP_CLASS_HID_01a4,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3106,7 +3520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 9
},
- [171] = {
+ [193] = {
.class_hid = BNXT_ULP_CLASS_HID_003e,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3122,7 +3536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 10
},
- [172] = {
+ [194] = {
.class_hid = BNXT_ULP_CLASS_HID_02f6,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3137,7 +3551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 11
},
- [173] = {
+ [195] = {
.class_hid = BNXT_ULP_CLASS_HID_078c,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3154,7 +3568,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 12
},
- [174] = {
+ [196] = {
.class_hid = BNXT_ULP_CLASS_HID_0044,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3170,7 +3584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 13
},
- [175] = {
+ [197] = {
.class_hid = BNXT_ULP_CLASS_HID_01ce,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3186,7 +3600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 14
},
- [176] = {
+ [198] = {
.class_hid = BNXT_ULP_CLASS_HID_0306,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3201,7 +3615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 15
},
- [177] = {
+ [199] = {
.class_hid = BNXT_ULP_CLASS_HID_067c,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -3218,7 +3632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
.class_tid = 23,
.wc_pri = 16
},
- [178] = {
+ [200] = {
.class_hid = BNXT_ULP_CLASS_HID_01b4,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
@@ -4528,8 +4942,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.key_start_idx = 722,
- .blob_key_bit_size = 200,
- .key_bit_size = 200,
+ .blob_key_bit_size = 392,
+ .key_bit_size = 392,
.key_num_fields = 11,
.result_start_idx = 558,
.result_bit_size = 64,
@@ -4600,8 +5014,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.key_start_idx = 791,
- .blob_key_bit_size = 200,
- .key_bit_size = 200,
+ .blob_key_bit_size = 392,
+ .key_bit_size = 392,
.key_num_fields = 11,
.result_start_idx = 589,
.result_bit_size = 64,
@@ -4617,7 +5031,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
.key_start_idx = 802,
.blob_key_bit_size = 167,
.key_bit_size = 167,
@@ -4744,8 +5158,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_RX,
.key_start_idx = 929,
- .blob_key_bit_size = 200,
- .key_bit_size = 200,
+ .blob_key_bit_size = 392,
+ .key_bit_size = 392,
.key_num_fields = 11,
.result_start_idx = 651,
.result_bit_size = 64,
@@ -5100,8 +5514,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
.resource_type = TF_MEM_INTERNAL,
.direction = TF_DIR_TX,
.key_start_idx = 1209,
- .blob_key_bit_size = 200,
- .key_bit_size = 200,
+ .blob_key_bit_size = 392,
+ .key_bit_size = 392,
.key_num_fields = 11,
.result_start_idx = 779,
.result_bit_size = 64,
@@ -10173,7 +10587,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
@@ -10183,7 +10597,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
@@ -10664,7 +11078,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
@@ -10674,7 +11088,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
@@ -10725,12 +11139,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .mask_operand = {
- (BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff,
- BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
(BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff,
@@ -10760,8 +11171,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff,
+ BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
@@ -10780,8 +11201,15 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
@@ -10792,9 +11220,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
@@ -10816,8 +11242,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -10838,32 +11264,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -10882,28 +11294,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
@@ -10912,42 +11314,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
@@ -11060,9 +11448,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
@@ -11107,8 +11493,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -11153,52 +11539,36 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 16,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF16_IDX_I_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_HF16_IDX_I_UDP_DST_PORT & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
- (BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID & 0xff,
+ BNXT_ULP_SYM_IP_PROTO_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 32,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
- (BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR & 0xff,
+ (BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 32,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 48,
@@ -11208,12 +11578,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 24,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF16_IDX_T_VXLAN_VNI >> 8) & 0xff,
- BNXT_ULP_HF16_IDX_T_VXLAN_VNI & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 10,
@@ -11279,11 +11644,6 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
- },
- {
- .field_bit_size = 12,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.mask_operand = {
(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
@@ -11298,6 +11658,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
.field_bit_size = 48,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
@@ -11529,7 +11894,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -11664,17 +12033,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
- (BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR & 0xff,
+ (BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
@@ -13056,12 +13425,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
{
.field_bit_size = 8,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.spec_operand = {
- (BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID >> 8) & 0xff,
- BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID & 0xff,
+ BNXT_ULP_SYM_IP_PROTO_UDP,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 128,
@@ -13532,7 +13900,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
@@ -13542,7 +13910,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
+ .field_bit_size = 128,
.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
.spec_operand = {
@@ -17381,7 +17749,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 5,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -17432,8 +17800,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
.field_bit_size = 9,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
- (0x00c5 >> 8) & 0xff,
- 0x00c5 & 0xff,
+ (0x0185 >> 8) & 0xff,
+ 0x0185 & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -17559,7 +17927,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 5,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -17610,8 +17978,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
.field_bit_size = 9,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
- (0x00c5 >> 8) & 0xff,
- 0x00c5 & 0xff,
+ (0x0185 >> 8) & 0xff,
+ 0x0185 & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -17648,8 +18016,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
.field_bit_size = 7,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
.result_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ (BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -17729,15 +18097,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
.field_bit_size = 10,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
- (0x00fb >> 8) & 0xff,
- 0x00fb & 0xff,
+ (0x0031 >> 8) & 0xff,
+ 0x0031 & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 5,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -17915,7 +18283,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 5,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -17966,8 +18334,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
.field_bit_size = 9,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
- (0x00c5 >> 8) & 0xff,
- 0x00c5 & 0xff,
+ (0x0185 >> 8) & 0xff,
+ 0x0185 & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
@@ -18723,7 +19091,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
{
.field_bit_size = 5,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
@@ -18774,8 +19142,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
.field_bit_size = 9,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
.result_operand = {
- (0x00c5 >> 8) & 0xff,
- 0x00c5 & 0xff,
+ (0x0185 >> 8) & 0xff,
+ 0x0185 & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 5175886..de56b7e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -11,7 +11,7 @@
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
#define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 179
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 201
#define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
#define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
#define BNXT_ULP_CLASS_HID_SHFTR 32
@@ -731,8 +731,6 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_065d = 0x065d,
BNXT_ULP_CLASS_HID_0623 = 0x0623,
BNXT_ULP_CLASS_HID_00eb = 0x00eb,
- BNXT_ULP_CLASS_HID_0768 = 0x0768,
- BNXT_ULP_CLASS_HID_073c = 0x073c,
BNXT_ULP_CLASS_HID_04bc = 0x04bc,
BNXT_ULP_CLASS_HID_0442 = 0x0442,
BNXT_ULP_CLASS_HID_050a = 0x050a,
@@ -741,22 +739,46 @@ enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_0700 = 0x0700,
BNXT_ULP_CLASS_HID_04c8 = 0x04c8,
BNXT_ULP_CLASS_HID_0678 = 0x0678,
- BNXT_ULP_CLASS_HID_064f = 0x064f,
- BNXT_ULP_CLASS_HID_051d = 0x051d,
+ BNXT_ULP_CLASS_HID_061f = 0x061f,
+ BNXT_ULP_CLASS_HID_05ad = 0x05ad,
BNXT_ULP_CLASS_HID_06a5 = 0x06a5,
BNXT_ULP_CLASS_HID_0455 = 0x0455,
+ BNXT_ULP_CLASS_HID_05dd = 0x05dd,
+ BNXT_ULP_CLASS_HID_0563 = 0x0563,
+ BNXT_ULP_CLASS_HID_059b = 0x059b,
+ BNXT_ULP_CLASS_HID_070b = 0x070b,
BNXT_ULP_CLASS_HID_04bd = 0x04bd,
BNXT_ULP_CLASS_HID_0443 = 0x0443,
BNXT_ULP_CLASS_HID_050b = 0x050b,
BNXT_ULP_CLASS_HID_06bb = 0x06bb,
- BNXT_ULP_CLASS_HID_050d = 0x050d,
- BNXT_ULP_CLASS_HID_04d3 = 0x04d3,
- BNXT_ULP_CLASS_HID_059b = 0x059b,
- BNXT_ULP_CLASS_HID_070b = 0x070b,
BNXT_ULP_CLASS_HID_0473 = 0x0473,
BNXT_ULP_CLASS_HID_0701 = 0x0701,
BNXT_ULP_CLASS_HID_04c9 = 0x04c9,
BNXT_ULP_CLASS_HID_0679 = 0x0679,
+ BNXT_ULP_CLASS_HID_05e2 = 0x05e2,
+ BNXT_ULP_CLASS_HID_00b0 = 0x00b0,
+ BNXT_ULP_CLASS_HID_0648 = 0x0648,
+ BNXT_ULP_CLASS_HID_03f8 = 0x03f8,
+ BNXT_ULP_CLASS_HID_02ea = 0x02ea,
+ BNXT_ULP_CLASS_HID_05b8 = 0x05b8,
+ BNXT_ULP_CLASS_HID_0370 = 0x0370,
+ BNXT_ULP_CLASS_HID_00e0 = 0x00e0,
+ BNXT_ULP_CLASS_HID_0745 = 0x0745,
+ BNXT_ULP_CLASS_HID_0213 = 0x0213,
+ BNXT_ULP_CLASS_HID_031b = 0x031b,
+ BNXT_ULP_CLASS_HID_008b = 0x008b,
+ BNXT_ULP_CLASS_HID_044d = 0x044d,
+ BNXT_ULP_CLASS_HID_071b = 0x071b,
+ BNXT_ULP_CLASS_HID_0003 = 0x0003,
+ BNXT_ULP_CLASS_HID_05b3 = 0x05b3,
+ BNXT_ULP_CLASS_HID_05e3 = 0x05e3,
+ BNXT_ULP_CLASS_HID_00b1 = 0x00b1,
+ BNXT_ULP_CLASS_HID_0649 = 0x0649,
+ BNXT_ULP_CLASS_HID_03f9 = 0x03f9,
+ BNXT_ULP_CLASS_HID_02eb = 0x02eb,
+ BNXT_ULP_CLASS_HID_05b9 = 0x05b9,
+ BNXT_ULP_CLASS_HID_0371 = 0x0371,
+ BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
BNXT_ULP_CLASS_HID_048b = 0x048b,
BNXT_ULP_CLASS_HID_0749 = 0x0749,
BNXT_ULP_CLASS_HID_05f1 = 0x05f1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index 79fcdee..137b7fd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -326,30 +326,7 @@ enum bnxt_ulp_hf16 {
BNXT_ULP_HF16_IDX_T_VXLAN_FLAGS = 24,
BNXT_ULP_HF16_IDX_T_VXLAN_RSVD0 = 25,
BNXT_ULP_HF16_IDX_T_VXLAN_VNI = 26,
- BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1 = 27,
- BNXT_ULP_HF16_IDX_I_ETH_DMAC = 28,
- BNXT_ULP_HF16_IDX_I_ETH_SMAC = 29,
- BNXT_ULP_HF16_IDX_I_ETH_TYPE = 30,
- BNXT_ULP_HF16_IDX_IO_VLAN_CFI_PRI = 31,
- BNXT_ULP_HF16_IDX_IO_VLAN_VID = 32,
- BNXT_ULP_HF16_IDX_IO_VLAN_TYPE = 33,
- BNXT_ULP_HF16_IDX_II_VLAN_CFI_PRI = 34,
- BNXT_ULP_HF16_IDX_II_VLAN_VID = 35,
- BNXT_ULP_HF16_IDX_II_VLAN_TYPE = 36,
- BNXT_ULP_HF16_IDX_I_IPV4_VER = 37,
- BNXT_ULP_HF16_IDX_I_IPV4_TOS = 38,
- BNXT_ULP_HF16_IDX_I_IPV4_LEN = 39,
- BNXT_ULP_HF16_IDX_I_IPV4_FRAG_ID = 40,
- BNXT_ULP_HF16_IDX_I_IPV4_FRAG_OFF = 41,
- BNXT_ULP_HF16_IDX_I_IPV4_TTL = 42,
- BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID = 43,
- BNXT_ULP_HF16_IDX_I_IPV4_CSUM = 44,
- BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR = 45,
- BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR = 46,
- BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT = 47,
- BNXT_ULP_HF16_IDX_I_UDP_DST_PORT = 48,
- BNXT_ULP_HF16_IDX_I_UDP_LENGTH = 49,
- BNXT_ULP_HF16_IDX_I_UDP_CSUM = 50
+ BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1 = 27
};
enum bnxt_ulp_hf17 {
@@ -363,24 +340,22 @@ enum bnxt_ulp_hf17 {
BNXT_ULP_HF17_IDX_OI_VLAN_CFI_PRI = 7,
BNXT_ULP_HF17_IDX_OI_VLAN_VID = 8,
BNXT_ULP_HF17_IDX_OI_VLAN_TYPE = 9,
- BNXT_ULP_HF17_IDX_O_IPV4_VER = 10,
- BNXT_ULP_HF17_IDX_O_IPV4_TOS = 11,
- BNXT_ULP_HF17_IDX_O_IPV4_LEN = 12,
- BNXT_ULP_HF17_IDX_O_IPV4_FRAG_ID = 13,
- BNXT_ULP_HF17_IDX_O_IPV4_FRAG_OFF = 14,
- BNXT_ULP_HF17_IDX_O_IPV4_TTL = 15,
- BNXT_ULP_HF17_IDX_O_IPV4_PROTO_ID = 16,
- BNXT_ULP_HF17_IDX_O_IPV4_CSUM = 17,
- BNXT_ULP_HF17_IDX_O_IPV4_SRC_ADDR = 18,
- BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR = 19,
- BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT = 20,
- BNXT_ULP_HF17_IDX_O_UDP_DST_PORT = 21,
- BNXT_ULP_HF17_IDX_O_UDP_LENGTH = 22,
- BNXT_ULP_HF17_IDX_O_UDP_CSUM = 23,
- BNXT_ULP_HF17_IDX_T_VXLAN_FLAGS = 24,
- BNXT_ULP_HF17_IDX_T_VXLAN_RSVD0 = 25,
- BNXT_ULP_HF17_IDX_T_VXLAN_VNI = 26,
- BNXT_ULP_HF17_IDX_T_VXLAN_RSVD1 = 27
+ BNXT_ULP_HF17_IDX_O_IPV6_VER = 10,
+ BNXT_ULP_HF17_IDX_O_IPV6_TC = 11,
+ BNXT_ULP_HF17_IDX_O_IPV6_FLOW_LABEL = 12,
+ BNXT_ULP_HF17_IDX_O_IPV6_PAYLOAD_LEN = 13,
+ BNXT_ULP_HF17_IDX_O_IPV6_PROTO_ID = 14,
+ BNXT_ULP_HF17_IDX_O_IPV6_TTL = 15,
+ BNXT_ULP_HF17_IDX_O_IPV6_SRC_ADDR = 16,
+ BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR = 17,
+ BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT = 18,
+ BNXT_ULP_HF17_IDX_O_UDP_DST_PORT = 19,
+ BNXT_ULP_HF17_IDX_O_UDP_LENGTH = 20,
+ BNXT_ULP_HF17_IDX_O_UDP_CSUM = 21,
+ BNXT_ULP_HF17_IDX_T_VXLAN_FLAGS = 22,
+ BNXT_ULP_HF17_IDX_T_VXLAN_RSVD0 = 23,
+ BNXT_ULP_HF17_IDX_T_VXLAN_VNI = 24,
+ BNXT_ULP_HF17_IDX_T_VXLAN_RSVD1 = 25
};
enum bnxt_ulp_hf18 {
@@ -861,30 +836,7 @@ enum bnxt_ulp_hf_bitmask16 {
BNXT_ULP_HF16_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
- BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
- BNXT_ULP_HF16_BITMASK_I_ETH_DMAC = 0x0000000800000000,
- BNXT_ULP_HF16_BITMASK_I_ETH_SMAC = 0x0000000400000000,
- BNXT_ULP_HF16_BITMASK_I_ETH_TYPE = 0x0000000200000000,
- BNXT_ULP_HF16_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
- BNXT_ULP_HF16_BITMASK_IO_VLAN_VID = 0x0000000080000000,
- BNXT_ULP_HF16_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
- BNXT_ULP_HF16_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
- BNXT_ULP_HF16_BITMASK_II_VLAN_VID = 0x0000000010000000,
- BNXT_ULP_HF16_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_VER = 0x0000000004000000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_TOS = 0x0000000002000000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_LEN = 0x0000000001000000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_TTL = 0x0000000000200000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID = 0x0000000000100000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
- BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
- BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
- BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
- BNXT_ULP_HF16_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
- BNXT_ULP_HF16_BITMASK_I_UDP_CSUM = 0x0000000000002000
+ BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000
};
enum bnxt_ulp_hf_bitmask17 {
@@ -898,24 +850,22 @@ enum bnxt_ulp_hf_bitmask17 {
BNXT_ULP_HF17_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
BNXT_ULP_HF17_BITMASK_OI_VLAN_VID = 0x0080000000000000,
BNXT_ULP_HF17_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_VER = 0x0020000000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_TOS = 0x0010000000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_LEN = 0x0008000000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_TTL = 0x0001000000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
- BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
- BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
- BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
- BNXT_ULP_HF17_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
- BNXT_ULP_HF17_BITMASK_O_UDP_CSUM = 0x0000010000000000,
- BNXT_ULP_HF17_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
- BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
- BNXT_ULP_HF17_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
- BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000
+ BNXT_ULP_HF17_BITMASK_O_IPV6_VER = 0x0020000000000000,
+ BNXT_ULP_HF17_BITMASK_O_IPV6_TC = 0x0010000000000000,
+ BNXT_ULP_HF17_BITMASK_O_IPV6_FLOW_LABEL = 0x0008000000000000,
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+ BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID = 0x0002000000000000,
+ BNXT_ULP_HF17_BITMASK_O_IPV6_TTL = 0x0001000000000000,
+ BNXT_ULP_HF17_BITMASK_O_IPV6_SRC_ADDR = 0x0000800000000000,
+ BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR = 0x0000400000000000,
+ BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
+ BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
+ BNXT_ULP_HF17_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
+ BNXT_ULP_HF17_BITMASK_O_UDP_CSUM = 0x0000040000000000,
+ BNXT_ULP_HF17_BITMASK_T_VXLAN_FLAGS = 0x0000020000000000,
+ BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD0 = 0x0000010000000000,
+ BNXT_ULP_HF17_BITMASK_T_VXLAN_VNI = 0x0000008000000000,
+ BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD1 = 0x0000004000000000
};
enum bnxt_ulp_hf_bitmask18 {
--
2.7.4
next prev parent reply other threads:[~2020-09-22 7:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-22 7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
2020-09-22 7:06 ` Somnath Kotur [this message]
2020-09-22 7:06 ` [dpdk-dev] [PATCH 2/8] net/bnxt: simplify representor Rx ring creation Somnath Kotur
2020-09-22 7:06 ` [dpdk-dev] [PATCH 3/8] net/bnxt: fix to correct bad shift operation Somnath Kotur
2020-09-22 7:06 ` [dpdk-dev] [PATCH 4/8] net/bnxt: fix to honor value passed for truflow devargs Somnath Kotur
2020-09-22 7:06 ` [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe Somnath Kotur
2020-09-24 14:47 ` Ferruh Yigit
2020-09-25 2:04 ` Somnath Kotur
2020-09-25 8:42 ` Ferruh Yigit
2020-09-25 10:46 ` Somnath Kotur
2020-09-25 10:49 ` Somnath Kotur
2020-09-25 10:40 ` [dpdk-dev] [PATCH v2] net/bnxt: add a " Somnath Kotur
2020-09-25 11:56 ` Ferruh Yigit
2020-09-22 7:06 ` [dpdk-dev] [PATCH 6/8] net/bnxt: support for representors on remote host domain Somnath Kotur
2020-09-22 7:06 ` [dpdk-dev] [PATCH 7/8] net/bnxt: fix flow match to ignore pkt type Somnath Kotur
2020-09-22 7:06 ` [dpdk-dev] [PATCH 8/8] net/bnxt: fix seg fault during NAT configuration Somnath Kotur
2020-09-23 23:50 ` [dpdk-dev] [PATCH 0/8] bnxt patches Ajit Khaparde
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