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* [dpdk-dev] [PATCH 0/8] bnxt patches
@ 2020-09-22  7:06 Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 1/8] net/bnxt: add support for decap action for ipv6 VXLAN flows Somnath Kotur
                   ` (8 more replies)
  0 siblings, 9 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Somnath Kotur

Fixes and enchancements in the bnxt PMD, mostly
in the TRUFLOW layer

Kishore Padmanabha (3):
  net/bnxt: add support for decap action for ipv6 VXLAN flows
  net/bnxt: fix flow match to ignore pkt type
  net/bnxt: fix seg fault during NAT configuration

Somnath Kotur (5):
  net/bnxt: simplify representor Rx ring creation
  net/bnxt: fix to correct bad shift operation
  net/bnxt: fix to honor value passed for truflow devargs
  net/bnxt: add a null ptr check in bnxt PCI probe
  net/bnxt: support for representors on remote host domain

 drivers/net/bnxt/bnxt.h                         |   21 +-
 drivers/net/bnxt/bnxt_cpr.c                     |    4 +-
 drivers/net/bnxt/bnxt_ethdev.c                  |  361 +++++-
 drivers/net/bnxt/bnxt_hwrm.c                    |   97 +-
 drivers/net/bnxt/bnxt_hwrm.h                    |    4 +
 drivers/net/bnxt/bnxt_reps.c                    |  223 ++--
 drivers/net/bnxt/bnxt_reps.h                    |   30 +-
 drivers/net/bnxt/hsi_struct_def_dpdk.h          |  248 ++++
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c              |    6 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c         |    4 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 1512 +++++++++++++++--------
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h  |   40 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h |  118 +-
 13 files changed, 1924 insertions(+), 744 deletions(-)

-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 1/8] net/bnxt: add support for decap action for ipv6 VXLAN flows
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 2/8] net/bnxt: simplify representor Rx ring creation Somnath Kotur
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Kishore Padmanabha, Michael Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Add a template to support ipv6 VXLAN flows to enable support for
vxlan decap for those flows.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 1206 +++++++++++++++--------
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h  |   40 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h |  118 +--
 3 files changed, 852 insertions(+), 512 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index a6dd321..7f9ba96 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -109,84 +109,106 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_CLASS_HID_065d] = 98,
 	[BNXT_ULP_CLASS_HID_0623] = 99,
 	[BNXT_ULP_CLASS_HID_00eb] = 100,
-	[BNXT_ULP_CLASS_HID_0768] = 101,
-	[BNXT_ULP_CLASS_HID_073c] = 102,
-	[BNXT_ULP_CLASS_HID_04bc] = 103,
-	[BNXT_ULP_CLASS_HID_0442] = 104,
-	[BNXT_ULP_CLASS_HID_050a] = 105,
-	[BNXT_ULP_CLASS_HID_06ba] = 106,
-	[BNXT_ULP_CLASS_HID_0472] = 107,
-	[BNXT_ULP_CLASS_HID_0700] = 108,
-	[BNXT_ULP_CLASS_HID_04c8] = 109,
-	[BNXT_ULP_CLASS_HID_0678] = 110,
-	[BNXT_ULP_CLASS_HID_064f] = 111,
-	[BNXT_ULP_CLASS_HID_051d] = 112,
-	[BNXT_ULP_CLASS_HID_06a5] = 113,
-	[BNXT_ULP_CLASS_HID_0455] = 114,
-	[BNXT_ULP_CLASS_HID_04bd] = 115,
-	[BNXT_ULP_CLASS_HID_0443] = 116,
-	[BNXT_ULP_CLASS_HID_050b] = 117,
-	[BNXT_ULP_CLASS_HID_06bb] = 118,
-	[BNXT_ULP_CLASS_HID_050d] = 119,
-	[BNXT_ULP_CLASS_HID_04d3] = 120,
-	[BNXT_ULP_CLASS_HID_059b] = 121,
-	[BNXT_ULP_CLASS_HID_070b] = 122,
-	[BNXT_ULP_CLASS_HID_0473] = 123,
-	[BNXT_ULP_CLASS_HID_0701] = 124,
-	[BNXT_ULP_CLASS_HID_04c9] = 125,
-	[BNXT_ULP_CLASS_HID_0679] = 126,
-	[BNXT_ULP_CLASS_HID_048b] = 127,
-	[BNXT_ULP_CLASS_HID_0749] = 128,
-	[BNXT_ULP_CLASS_HID_05f1] = 129,
-	[BNXT_ULP_CLASS_HID_04b7] = 130,
-	[BNXT_ULP_CLASS_HID_049b] = 131,
-	[BNXT_ULP_CLASS_HID_0759] = 132,
-	[BNXT_ULP_CLASS_HID_05e1] = 133,
-	[BNXT_ULP_CLASS_HID_04a7] = 134,
-	[BNXT_ULP_CLASS_HID_0301] = 135,
-	[BNXT_ULP_CLASS_HID_07f9] = 136,
-	[BNXT_ULP_CLASS_HID_0397] = 137,
-	[BNXT_ULP_CLASS_HID_068f] = 138,
-	[BNXT_ULP_CLASS_HID_02f1] = 139,
-	[BNXT_ULP_CLASS_HID_0609] = 140,
-	[BNXT_ULP_CLASS_HID_0267] = 141,
-	[BNXT_ULP_CLASS_HID_077f] = 142,
-	[BNXT_ULP_CLASS_HID_01e1] = 143,
-	[BNXT_ULP_CLASS_HID_0329] = 144,
-	[BNXT_ULP_CLASS_HID_01c1] = 145,
-	[BNXT_ULP_CLASS_HID_0309] = 146,
-	[BNXT_ULP_CLASS_HID_01d1] = 147,
-	[BNXT_ULP_CLASS_HID_0319] = 148,
-	[BNXT_ULP_CLASS_HID_01e2] = 149,
-	[BNXT_ULP_CLASS_HID_032a] = 150,
-	[BNXT_ULP_CLASS_HID_0650] = 151,
-	[BNXT_ULP_CLASS_HID_0198] = 152,
-	[BNXT_ULP_CLASS_HID_01c2] = 153,
-	[BNXT_ULP_CLASS_HID_030a] = 154,
-	[BNXT_ULP_CLASS_HID_0670] = 155,
-	[BNXT_ULP_CLASS_HID_01b8] = 156,
-	[BNXT_ULP_CLASS_HID_01d2] = 157,
-	[BNXT_ULP_CLASS_HID_031a] = 158,
-	[BNXT_ULP_CLASS_HID_0660] = 159,
-	[BNXT_ULP_CLASS_HID_01a8] = 160,
-	[BNXT_ULP_CLASS_HID_01dd] = 161,
-	[BNXT_ULP_CLASS_HID_0315] = 162,
-	[BNXT_ULP_CLASS_HID_003d] = 163,
-	[BNXT_ULP_CLASS_HID_02f5] = 164,
-	[BNXT_ULP_CLASS_HID_01cd] = 165,
-	[BNXT_ULP_CLASS_HID_0305] = 166,
-	[BNXT_ULP_CLASS_HID_01de] = 167,
-	[BNXT_ULP_CLASS_HID_0316] = 168,
-	[BNXT_ULP_CLASS_HID_066c] = 169,
-	[BNXT_ULP_CLASS_HID_01a4] = 170,
-	[BNXT_ULP_CLASS_HID_003e] = 171,
-	[BNXT_ULP_CLASS_HID_02f6] = 172,
-	[BNXT_ULP_CLASS_HID_078c] = 173,
-	[BNXT_ULP_CLASS_HID_0044] = 174,
-	[BNXT_ULP_CLASS_HID_01ce] = 175,
-	[BNXT_ULP_CLASS_HID_0306] = 176,
-	[BNXT_ULP_CLASS_HID_067c] = 177,
-	[BNXT_ULP_CLASS_HID_01b4] = 178
+	[BNXT_ULP_CLASS_HID_04bc] = 101,
+	[BNXT_ULP_CLASS_HID_0442] = 102,
+	[BNXT_ULP_CLASS_HID_050a] = 103,
+	[BNXT_ULP_CLASS_HID_06ba] = 104,
+	[BNXT_ULP_CLASS_HID_0472] = 105,
+	[BNXT_ULP_CLASS_HID_0700] = 106,
+	[BNXT_ULP_CLASS_HID_04c8] = 107,
+	[BNXT_ULP_CLASS_HID_0678] = 108,
+	[BNXT_ULP_CLASS_HID_061f] = 109,
+	[BNXT_ULP_CLASS_HID_05ad] = 110,
+	[BNXT_ULP_CLASS_HID_06a5] = 111,
+	[BNXT_ULP_CLASS_HID_0455] = 112,
+	[BNXT_ULP_CLASS_HID_05dd] = 113,
+	[BNXT_ULP_CLASS_HID_0563] = 114,
+	[BNXT_ULP_CLASS_HID_059b] = 115,
+	[BNXT_ULP_CLASS_HID_070b] = 116,
+	[BNXT_ULP_CLASS_HID_04bd] = 117,
+	[BNXT_ULP_CLASS_HID_0443] = 118,
+	[BNXT_ULP_CLASS_HID_050b] = 119,
+	[BNXT_ULP_CLASS_HID_06bb] = 120,
+	[BNXT_ULP_CLASS_HID_0473] = 121,
+	[BNXT_ULP_CLASS_HID_0701] = 122,
+	[BNXT_ULP_CLASS_HID_04c9] = 123,
+	[BNXT_ULP_CLASS_HID_0679] = 124,
+	[BNXT_ULP_CLASS_HID_05e2] = 125,
+	[BNXT_ULP_CLASS_HID_00b0] = 126,
+	[BNXT_ULP_CLASS_HID_0648] = 127,
+	[BNXT_ULP_CLASS_HID_03f8] = 128,
+	[BNXT_ULP_CLASS_HID_02ea] = 129,
+	[BNXT_ULP_CLASS_HID_05b8] = 130,
+	[BNXT_ULP_CLASS_HID_0370] = 131,
+	[BNXT_ULP_CLASS_HID_00e0] = 132,
+	[BNXT_ULP_CLASS_HID_0745] = 133,
+	[BNXT_ULP_CLASS_HID_0213] = 134,
+	[BNXT_ULP_CLASS_HID_031b] = 135,
+	[BNXT_ULP_CLASS_HID_008b] = 136,
+	[BNXT_ULP_CLASS_HID_044d] = 137,
+	[BNXT_ULP_CLASS_HID_071b] = 138,
+	[BNXT_ULP_CLASS_HID_0003] = 139,
+	[BNXT_ULP_CLASS_HID_05b3] = 140,
+	[BNXT_ULP_CLASS_HID_05e3] = 141,
+	[BNXT_ULP_CLASS_HID_00b1] = 142,
+	[BNXT_ULP_CLASS_HID_0649] = 143,
+	[BNXT_ULP_CLASS_HID_03f9] = 144,
+	[BNXT_ULP_CLASS_HID_02eb] = 145,
+	[BNXT_ULP_CLASS_HID_05b9] = 146,
+	[BNXT_ULP_CLASS_HID_0371] = 147,
+	[BNXT_ULP_CLASS_HID_00e1] = 148,
+	[BNXT_ULP_CLASS_HID_048b] = 149,
+	[BNXT_ULP_CLASS_HID_0749] = 150,
+	[BNXT_ULP_CLASS_HID_05f1] = 151,
+	[BNXT_ULP_CLASS_HID_04b7] = 152,
+	[BNXT_ULP_CLASS_HID_049b] = 153,
+	[BNXT_ULP_CLASS_HID_0759] = 154,
+	[BNXT_ULP_CLASS_HID_05e1] = 155,
+	[BNXT_ULP_CLASS_HID_04a7] = 156,
+	[BNXT_ULP_CLASS_HID_0301] = 157,
+	[BNXT_ULP_CLASS_HID_07f9] = 158,
+	[BNXT_ULP_CLASS_HID_0397] = 159,
+	[BNXT_ULP_CLASS_HID_068f] = 160,
+	[BNXT_ULP_CLASS_HID_02f1] = 161,
+	[BNXT_ULP_CLASS_HID_0609] = 162,
+	[BNXT_ULP_CLASS_HID_0267] = 163,
+	[BNXT_ULP_CLASS_HID_077f] = 164,
+	[BNXT_ULP_CLASS_HID_01e1] = 165,
+	[BNXT_ULP_CLASS_HID_0329] = 166,
+	[BNXT_ULP_CLASS_HID_01c1] = 167,
+	[BNXT_ULP_CLASS_HID_0309] = 168,
+	[BNXT_ULP_CLASS_HID_01d1] = 169,
+	[BNXT_ULP_CLASS_HID_0319] = 170,
+	[BNXT_ULP_CLASS_HID_01e2] = 171,
+	[BNXT_ULP_CLASS_HID_032a] = 172,
+	[BNXT_ULP_CLASS_HID_0650] = 173,
+	[BNXT_ULP_CLASS_HID_0198] = 174,
+	[BNXT_ULP_CLASS_HID_01c2] = 175,
+	[BNXT_ULP_CLASS_HID_030a] = 176,
+	[BNXT_ULP_CLASS_HID_0670] = 177,
+	[BNXT_ULP_CLASS_HID_01b8] = 178,
+	[BNXT_ULP_CLASS_HID_01d2] = 179,
+	[BNXT_ULP_CLASS_HID_031a] = 180,
+	[BNXT_ULP_CLASS_HID_0660] = 181,
+	[BNXT_ULP_CLASS_HID_01a8] = 182,
+	[BNXT_ULP_CLASS_HID_01dd] = 183,
+	[BNXT_ULP_CLASS_HID_0315] = 184,
+	[BNXT_ULP_CLASS_HID_003d] = 185,
+	[BNXT_ULP_CLASS_HID_02f5] = 186,
+	[BNXT_ULP_CLASS_HID_01cd] = 187,
+	[BNXT_ULP_CLASS_HID_0305] = 188,
+	[BNXT_ULP_CLASS_HID_01de] = 189,
+	[BNXT_ULP_CLASS_HID_0316] = 190,
+	[BNXT_ULP_CLASS_HID_066c] = 191,
+	[BNXT_ULP_CLASS_HID_01a4] = 192,
+	[BNXT_ULP_CLASS_HID_003e] = 193,
+	[BNXT_ULP_CLASS_HID_02f6] = 194,
+	[BNXT_ULP_CLASS_HID_078c] = 195,
+	[BNXT_ULP_CLASS_HID_0044] = 196,
+	[BNXT_ULP_CLASS_HID_01ce] = 197,
+	[BNXT_ULP_CLASS_HID_0306] = 198,
+	[BNXT_ULP_CLASS_HID_067c] = 199,
+	[BNXT_ULP_CLASS_HID_01b4] = 200
 };
 
 struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
@@ -1921,134 +1943,526 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 11
 	},
 	[101] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0768,
+	.class_hid = BNXT_ULP_CLASS_HID_04bc,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 0
+	},
+	[102] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0442,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 1
+	},
+	[103] = {
+	.class_hid = BNXT_ULP_CLASS_HID_050a,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 2
+	},
+	[104] = {
+	.class_hid = BNXT_ULP_CLASS_HID_06ba,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 3
+	},
+	[105] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0472,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 4
+	},
+	[106] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0700,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 5
+	},
+	[107] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04c8,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 6
+	},
+	[108] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0678,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 7
+	},
+	[109] = {
+	.class_hid = BNXT_ULP_CLASS_HID_061f,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 8
+	},
+	[110] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05ad,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 9
+	},
+	[111] = {
+	.class_hid = BNXT_ULP_CLASS_HID_06a5,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 10
+	},
+	[112] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0455,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 11
+	},
+	[113] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05dd,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 12
+	},
+	[114] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0563,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 13
+	},
+	[115] = {
+	.class_hid = BNXT_ULP_CLASS_HID_059b,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 14
+	},
+	[116] = {
+	.class_hid = BNXT_ULP_CLASS_HID_070b,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 15
+	},
+	[117] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04bd,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 16
+	},
+	[118] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0443,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 17
+	},
+	[119] = {
+	.class_hid = BNXT_ULP_CLASS_HID_050b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
-		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
-		BNXT_ULP_HDR_BIT_I_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF16_BITMASK_I_ETH_TYPE |
-		BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
-		BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 16,
-	.wc_pri = 0
+	.wc_pri = 18
 	},
-	[102] = {
-	.class_hid = BNXT_ULP_CLASS_HID_073c,
+	[120] = {
+	.class_hid = BNXT_ULP_CLASS_HID_06bb,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
-		BNXT_ULP_HDR_BIT_I_ETH |
-		BNXT_ULP_HDR_BIT_I_IPV4 |
-		BNXT_ULP_HDR_BIT_I_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF16_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
-		BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI |
-		BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR |
-		BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR |
-		BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID |
-		BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT |
-		BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 16,
-	.wc_pri = 1
+	.wc_pri = 19
 	},
-	[103] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04bc,
+	[121] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0473,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 20
+	},
+	[122] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0701,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 21
+	},
+	[123] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04c9,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 22
+	},
+	[124] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0679,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_OO_VLAN |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
+		BNXT_ULP_HF16_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF16_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF16_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 16,
+	.wc_pri = 23
+	},
+	[125] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05e2,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 0
 	},
-	[104] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0442,
+	[126] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00b0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 1
 	},
-	[105] = {
-	.class_hid = BNXT_ULP_CLASS_HID_050a,
+	[127] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0648,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 2
 	},
-	[106] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06ba,
+	[128] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03f8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 3
 	},
-	[107] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0472,
+	[129] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02ea,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2056,109 +2470,109 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 4
 	},
-	[108] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0700,
+	[130] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05b8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 5
 	},
-	[109] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04c8,
+	[131] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0370,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 6
 	},
-	[110] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0678,
+	[132] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00e0,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 7
 	},
-	[111] = {
-	.class_hid = BNXT_ULP_CLASS_HID_064f,
+	[133] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0745,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
 		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 8
 	},
-	[112] = {
-	.class_hid = BNXT_ULP_CLASS_HID_051d,
+	[134] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0213,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
 		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 9
 	},
-	[113] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06a5,
+	[135] = {
+	.class_hid = BNXT_ULP_CLASS_HID_031b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2166,114 +2580,114 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 10
 	},
-	[114] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0455,
+	[136] = {
+	.class_hid = BNXT_ULP_CLASS_HID_008b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 11
 	},
-	[115] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04bd,
+	[137] = {
+	.class_hid = BNXT_ULP_CLASS_HID_044d,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 12
 	},
-	[116] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0443,
+	[138] = {
+	.class_hid = BNXT_ULP_CLASS_HID_071b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_TYPE |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 13
 	},
-	[117] = {
-	.class_hid = BNXT_ULP_CLASS_HID_050b,
+	[139] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0003,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 14
 	},
-	[118] = {
-	.class_hid = BNXT_ULP_CLASS_HID_06bb,
+	[140] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05b3,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 15
 	},
-	[119] = {
-	.class_hid = BNXT_ULP_CLASS_HID_050d,
+	[141] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05e3,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2281,75 +2695,75 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 16
 	},
-	[120] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04d3,
+	[142] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00b1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 17
 	},
-	[121] = {
-	.class_hid = BNXT_ULP_CLASS_HID_059b,
+	[143] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0649,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 18
 	},
-	[122] = {
-	.class_hid = BNXT_ULP_CLASS_HID_070b,
+	[144] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03f9,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF17_BITMASK_OO_VLAN_VID |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 19
 	},
-	[123] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0473,
+	[145] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02eb,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
@@ -2357,66 +2771,66 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 20
 	},
-	[124] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0701,
+	[146] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05b9,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 21
 	},
-	[125] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04c9,
+	[147] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0371,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF17_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 22
 	},
-	[126] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0679,
+	[148] = {
+	.class_hid = BNXT_ULP_CLASS_HID_00e1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_OO_VLAN |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_HDR_BIT_T_VXLAN |
 		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF17_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR |
 		BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 17,
 	.wc_pri = 23
 	},
-	[127] = {
+	[149] = {
 	.class_hid = BNXT_ULP_CLASS_HID_048b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2434,7 +2848,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 18,
 	.wc_pri = 0
 	},
-	[128] = {
+	[150] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0749,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2451,7 +2865,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 18,
 	.wc_pri = 1
 	},
-	[129] = {
+	[151] = {
 	.class_hid = BNXT_ULP_CLASS_HID_05f1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2468,7 +2882,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 18,
 	.wc_pri = 2
 	},
-	[130] = {
+	[152] = {
 	.class_hid = BNXT_ULP_CLASS_HID_04b7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2484,7 +2898,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 18,
 	.wc_pri = 3
 	},
-	[131] = {
+	[153] = {
 	.class_hid = BNXT_ULP_CLASS_HID_049b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2502,7 +2916,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 19,
 	.wc_pri = 0
 	},
-	[132] = {
+	[154] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0759,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2519,7 +2933,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 19,
 	.wc_pri = 1
 	},
-	[133] = {
+	[155] = {
 	.class_hid = BNXT_ULP_CLASS_HID_05e1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2536,7 +2950,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 19,
 	.wc_pri = 2
 	},
-	[134] = {
+	[156] = {
 	.class_hid = BNXT_ULP_CLASS_HID_04a7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2552,7 +2966,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 19,
 	.wc_pri = 3
 	},
-	[135] = {
+	[157] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0301,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2570,7 +2984,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 20,
 	.wc_pri = 0
 	},
-	[136] = {
+	[158] = {
 	.class_hid = BNXT_ULP_CLASS_HID_07f9,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2587,7 +3001,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 20,
 	.wc_pri = 1
 	},
-	[137] = {
+	[159] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0397,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2604,7 +3018,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 20,
 	.wc_pri = 2
 	},
-	[138] = {
+	[160] = {
 	.class_hid = BNXT_ULP_CLASS_HID_068f,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2620,7 +3034,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 20,
 	.wc_pri = 3
 	},
-	[139] = {
+	[161] = {
 	.class_hid = BNXT_ULP_CLASS_HID_02f1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2638,7 +3052,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 21,
 	.wc_pri = 0
 	},
-	[140] = {
+	[162] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0609,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2655,7 +3069,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 21,
 	.wc_pri = 1
 	},
-	[141] = {
+	[163] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0267,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2672,7 +3086,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 21,
 	.wc_pri = 2
 	},
-	[142] = {
+	[164] = {
 	.class_hid = BNXT_ULP_CLASS_HID_077f,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2688,7 +3102,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 21,
 	.wc_pri = 3
 	},
-	[143] = {
+	[165] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01e1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2702,7 +3116,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 0
 	},
-	[144] = {
+	[166] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0329,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2715,7 +3129,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 1
 	},
-	[145] = {
+	[167] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01c1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2730,7 +3144,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 2
 	},
-	[146] = {
+	[168] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0309,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2744,7 +3158,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 3
 	},
-	[147] = {
+	[169] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01d1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2759,7 +3173,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 4
 	},
-	[148] = {
+	[170] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0319,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2773,7 +3187,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 5
 	},
-	[149] = {
+	[171] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01e2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2788,7 +3202,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 6
 	},
-	[150] = {
+	[172] = {
 	.class_hid = BNXT_ULP_CLASS_HID_032a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2802,7 +3216,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 7
 	},
-	[151] = {
+	[173] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0650,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2818,7 +3232,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 8
 	},
-	[152] = {
+	[174] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0198,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2833,7 +3247,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 9
 	},
-	[153] = {
+	[175] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01c2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2849,7 +3263,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 10
 	},
-	[154] = {
+	[176] = {
 	.class_hid = BNXT_ULP_CLASS_HID_030a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2864,7 +3278,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 11
 	},
-	[155] = {
+	[177] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0670,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2881,7 +3295,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 12
 	},
-	[156] = {
+	[178] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2897,7 +3311,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 13
 	},
-	[157] = {
+	[179] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01d2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2913,7 +3327,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 14
 	},
-	[158] = {
+	[180] = {
 	.class_hid = BNXT_ULP_CLASS_HID_031a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2928,7 +3342,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 15
 	},
-	[159] = {
+	[181] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0660,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2945,7 +3359,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 16
 	},
-	[160] = {
+	[182] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01a8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2961,7 +3375,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 22,
 	.wc_pri = 17
 	},
-	[161] = {
+	[183] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01dd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2975,7 +3389,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 0
 	},
-	[162] = {
+	[184] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0315,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -2988,7 +3402,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 1
 	},
-	[163] = {
+	[185] = {
 	.class_hid = BNXT_ULP_CLASS_HID_003d,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3003,7 +3417,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 2
 	},
-	[164] = {
+	[186] = {
 	.class_hid = BNXT_ULP_CLASS_HID_02f5,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3017,7 +3431,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 3
 	},
-	[165] = {
+	[187] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01cd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3032,7 +3446,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 4
 	},
-	[166] = {
+	[188] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0305,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3046,7 +3460,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 5
 	},
-	[167] = {
+	[189] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01de,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3061,7 +3475,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 6
 	},
-	[168] = {
+	[190] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0316,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3075,7 +3489,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 7
 	},
-	[169] = {
+	[191] = {
 	.class_hid = BNXT_ULP_CLASS_HID_066c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3091,7 +3505,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 8
 	},
-	[170] = {
+	[192] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01a4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3106,7 +3520,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 9
 	},
-	[171] = {
+	[193] = {
 	.class_hid = BNXT_ULP_CLASS_HID_003e,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3122,7 +3536,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 10
 	},
-	[172] = {
+	[194] = {
 	.class_hid = BNXT_ULP_CLASS_HID_02f6,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3137,7 +3551,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 11
 	},
-	[173] = {
+	[195] = {
 	.class_hid = BNXT_ULP_CLASS_HID_078c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3154,7 +3568,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 12
 	},
-	[174] = {
+	[196] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0044,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3170,7 +3584,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 13
 	},
-	[175] = {
+	[197] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01ce,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3186,7 +3600,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 14
 	},
-	[176] = {
+	[198] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0306,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3201,7 +3615,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 15
 	},
-	[177] = {
+	[199] = {
 	.class_hid = BNXT_ULP_CLASS_HID_067c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3218,7 +3632,7 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.class_tid = 23,
 	.wc_pri = 16
 	},
-	[178] = {
+	[200] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -4528,8 +4942,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 722,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 558,
 	.result_bit_size = 64,
@@ -4600,8 +5014,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 791,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 589,
 	.result_bit_size = 64,
@@ -4617,7 +5031,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.key_start_idx = 802,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -4744,8 +5158,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
 	.key_start_idx = 929,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 651,
 	.result_bit_size = 64,
@@ -5100,8 +5514,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
 	.key_start_idx = 1209,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
 	.key_num_fields = 11,
 	.result_start_idx = 779,
 	.result_bit_size = 64,
@@ -10173,7 +10587,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -10183,7 +10597,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -10664,7 +11078,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -10674,7 +11088,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -10725,12 +11139,9 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.mask_operand = {
-		(BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_O_ETH_DMAC & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
 		(BNXT_ULP_HF16_IDX_O_ETH_DMAC >> 8) & 0xff,
@@ -10760,8 +11171,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF16_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 12,
@@ -10780,8 +11201,15 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 4,
@@ -10792,9 +11220,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -10816,8 +11242,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10838,32 +11264,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L4_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -10882,28 +11294,18 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L3_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -10912,42 +11314,28 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 2,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_L2_HDR_VALID_YES,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 3,
@@ -11060,9 +11448,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 1,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
@@ -11107,8 +11493,8 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11153,52 +11539,36 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_I_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_I_UDP_DST_PORT & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 16,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID & 0xff,
+		BNXT_ULP_SYM_IP_PROTO_UDP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 32,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 48,
@@ -11208,12 +11578,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_T_VXLAN_VNI >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_T_VXLAN_VNI & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 10,
@@ -11279,11 +11644,6 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
 		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
@@ -11298,6 +11658,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
@@ -11529,7 +11894,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
@@ -11664,17 +12033,17 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -13056,12 +13425,11 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID & 0xff,
+		BNXT_ULP_SYM_IP_PROTO_UDP,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 128,
@@ -13532,7 +13900,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -13542,7 +13910,7 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
@@ -17381,7 +17749,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17432,8 +17800,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17559,7 +17927,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17610,8 +17978,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17648,8 +18016,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 7,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.result_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17729,15 +18097,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00fb >> 8) & 0xff,
-		0x00fb & 0xff,
+		(0x0031 >> 8) & 0xff,
+		0x0031 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17915,7 +18283,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17966,8 +18334,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -18723,7 +19091,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -18774,8 +19142,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 5175886..de56b7e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -11,7 +11,7 @@
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 179
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 201
 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
 #define BNXT_ULP_CLASS_HID_SHFTR 32
@@ -731,8 +731,6 @@ enum bnxt_ulp_class_hid {
 	BNXT_ULP_CLASS_HID_065d = 0x065d,
 	BNXT_ULP_CLASS_HID_0623 = 0x0623,
 	BNXT_ULP_CLASS_HID_00eb = 0x00eb,
-	BNXT_ULP_CLASS_HID_0768 = 0x0768,
-	BNXT_ULP_CLASS_HID_073c = 0x073c,
 	BNXT_ULP_CLASS_HID_04bc = 0x04bc,
 	BNXT_ULP_CLASS_HID_0442 = 0x0442,
 	BNXT_ULP_CLASS_HID_050a = 0x050a,
@@ -741,22 +739,46 @@ enum bnxt_ulp_class_hid {
 	BNXT_ULP_CLASS_HID_0700 = 0x0700,
 	BNXT_ULP_CLASS_HID_04c8 = 0x04c8,
 	BNXT_ULP_CLASS_HID_0678 = 0x0678,
-	BNXT_ULP_CLASS_HID_064f = 0x064f,
-	BNXT_ULP_CLASS_HID_051d = 0x051d,
+	BNXT_ULP_CLASS_HID_061f = 0x061f,
+	BNXT_ULP_CLASS_HID_05ad = 0x05ad,
 	BNXT_ULP_CLASS_HID_06a5 = 0x06a5,
 	BNXT_ULP_CLASS_HID_0455 = 0x0455,
+	BNXT_ULP_CLASS_HID_05dd = 0x05dd,
+	BNXT_ULP_CLASS_HID_0563 = 0x0563,
+	BNXT_ULP_CLASS_HID_059b = 0x059b,
+	BNXT_ULP_CLASS_HID_070b = 0x070b,
 	BNXT_ULP_CLASS_HID_04bd = 0x04bd,
 	BNXT_ULP_CLASS_HID_0443 = 0x0443,
 	BNXT_ULP_CLASS_HID_050b = 0x050b,
 	BNXT_ULP_CLASS_HID_06bb = 0x06bb,
-	BNXT_ULP_CLASS_HID_050d = 0x050d,
-	BNXT_ULP_CLASS_HID_04d3 = 0x04d3,
-	BNXT_ULP_CLASS_HID_059b = 0x059b,
-	BNXT_ULP_CLASS_HID_070b = 0x070b,
 	BNXT_ULP_CLASS_HID_0473 = 0x0473,
 	BNXT_ULP_CLASS_HID_0701 = 0x0701,
 	BNXT_ULP_CLASS_HID_04c9 = 0x04c9,
 	BNXT_ULP_CLASS_HID_0679 = 0x0679,
+	BNXT_ULP_CLASS_HID_05e2 = 0x05e2,
+	BNXT_ULP_CLASS_HID_00b0 = 0x00b0,
+	BNXT_ULP_CLASS_HID_0648 = 0x0648,
+	BNXT_ULP_CLASS_HID_03f8 = 0x03f8,
+	BNXT_ULP_CLASS_HID_02ea = 0x02ea,
+	BNXT_ULP_CLASS_HID_05b8 = 0x05b8,
+	BNXT_ULP_CLASS_HID_0370 = 0x0370,
+	BNXT_ULP_CLASS_HID_00e0 = 0x00e0,
+	BNXT_ULP_CLASS_HID_0745 = 0x0745,
+	BNXT_ULP_CLASS_HID_0213 = 0x0213,
+	BNXT_ULP_CLASS_HID_031b = 0x031b,
+	BNXT_ULP_CLASS_HID_008b = 0x008b,
+	BNXT_ULP_CLASS_HID_044d = 0x044d,
+	BNXT_ULP_CLASS_HID_071b = 0x071b,
+	BNXT_ULP_CLASS_HID_0003 = 0x0003,
+	BNXT_ULP_CLASS_HID_05b3 = 0x05b3,
+	BNXT_ULP_CLASS_HID_05e3 = 0x05e3,
+	BNXT_ULP_CLASS_HID_00b1 = 0x00b1,
+	BNXT_ULP_CLASS_HID_0649 = 0x0649,
+	BNXT_ULP_CLASS_HID_03f9 = 0x03f9,
+	BNXT_ULP_CLASS_HID_02eb = 0x02eb,
+	BNXT_ULP_CLASS_HID_05b9 = 0x05b9,
+	BNXT_ULP_CLASS_HID_0371 = 0x0371,
+	BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
 	BNXT_ULP_CLASS_HID_048b = 0x048b,
 	BNXT_ULP_CLASS_HID_0749 = 0x0749,
 	BNXT_ULP_CLASS_HID_05f1 = 0x05f1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index 79fcdee..137b7fd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -326,30 +326,7 @@ enum bnxt_ulp_hf16 {
 	BNXT_ULP_HF16_IDX_T_VXLAN_FLAGS          = 24,
 	BNXT_ULP_HF16_IDX_T_VXLAN_RSVD0          = 25,
 	BNXT_ULP_HF16_IDX_T_VXLAN_VNI            = 26,
-	BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1          = 27,
-	BNXT_ULP_HF16_IDX_I_ETH_DMAC             = 28,
-	BNXT_ULP_HF16_IDX_I_ETH_SMAC             = 29,
-	BNXT_ULP_HF16_IDX_I_ETH_TYPE             = 30,
-	BNXT_ULP_HF16_IDX_IO_VLAN_CFI_PRI        = 31,
-	BNXT_ULP_HF16_IDX_IO_VLAN_VID            = 32,
-	BNXT_ULP_HF16_IDX_IO_VLAN_TYPE           = 33,
-	BNXT_ULP_HF16_IDX_II_VLAN_CFI_PRI        = 34,
-	BNXT_ULP_HF16_IDX_II_VLAN_VID            = 35,
-	BNXT_ULP_HF16_IDX_II_VLAN_TYPE           = 36,
-	BNXT_ULP_HF16_IDX_I_IPV4_VER             = 37,
-	BNXT_ULP_HF16_IDX_I_IPV4_TOS             = 38,
-	BNXT_ULP_HF16_IDX_I_IPV4_LEN             = 39,
-	BNXT_ULP_HF16_IDX_I_IPV4_FRAG_ID         = 40,
-	BNXT_ULP_HF16_IDX_I_IPV4_FRAG_OFF        = 41,
-	BNXT_ULP_HF16_IDX_I_IPV4_TTL             = 42,
-	BNXT_ULP_HF16_IDX_I_IPV4_PROTO_ID        = 43,
-	BNXT_ULP_HF16_IDX_I_IPV4_CSUM            = 44,
-	BNXT_ULP_HF16_IDX_I_IPV4_SRC_ADDR        = 45,
-	BNXT_ULP_HF16_IDX_I_IPV4_DST_ADDR        = 46,
-	BNXT_ULP_HF16_IDX_I_UDP_SRC_PORT         = 47,
-	BNXT_ULP_HF16_IDX_I_UDP_DST_PORT         = 48,
-	BNXT_ULP_HF16_IDX_I_UDP_LENGTH           = 49,
-	BNXT_ULP_HF16_IDX_I_UDP_CSUM             = 50
+	BNXT_ULP_HF16_IDX_T_VXLAN_RSVD1          = 27
 };
 
 enum bnxt_ulp_hf17 {
@@ -363,24 +340,22 @@ enum bnxt_ulp_hf17 {
 	BNXT_ULP_HF17_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF17_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF17_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF17_IDX_O_IPV4_VER             = 10,
-	BNXT_ULP_HF17_IDX_O_IPV4_TOS             = 11,
-	BNXT_ULP_HF17_IDX_O_IPV4_LEN             = 12,
-	BNXT_ULP_HF17_IDX_O_IPV4_FRAG_ID         = 13,
-	BNXT_ULP_HF17_IDX_O_IPV4_FRAG_OFF        = 14,
-	BNXT_ULP_HF17_IDX_O_IPV4_TTL             = 15,
-	BNXT_ULP_HF17_IDX_O_IPV4_PROTO_ID        = 16,
-	BNXT_ULP_HF17_IDX_O_IPV4_CSUM            = 17,
-	BNXT_ULP_HF17_IDX_O_IPV4_SRC_ADDR        = 18,
-	BNXT_ULP_HF17_IDX_O_IPV4_DST_ADDR        = 19,
-	BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT         = 20,
-	BNXT_ULP_HF17_IDX_O_UDP_DST_PORT         = 21,
-	BNXT_ULP_HF17_IDX_O_UDP_LENGTH           = 22,
-	BNXT_ULP_HF17_IDX_O_UDP_CSUM             = 23,
-	BNXT_ULP_HF17_IDX_T_VXLAN_FLAGS          = 24,
-	BNXT_ULP_HF17_IDX_T_VXLAN_RSVD0          = 25,
-	BNXT_ULP_HF17_IDX_T_VXLAN_VNI            = 26,
-	BNXT_ULP_HF17_IDX_T_VXLAN_RSVD1          = 27
+	BNXT_ULP_HF17_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF17_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF17_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF17_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF17_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF17_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF17_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF17_IDX_O_UDP_SRC_PORT         = 18,
+	BNXT_ULP_HF17_IDX_O_UDP_DST_PORT         = 19,
+	BNXT_ULP_HF17_IDX_O_UDP_LENGTH           = 20,
+	BNXT_ULP_HF17_IDX_O_UDP_CSUM             = 21,
+	BNXT_ULP_HF17_IDX_T_VXLAN_FLAGS          = 22,
+	BNXT_ULP_HF17_IDX_T_VXLAN_RSVD0          = 23,
+	BNXT_ULP_HF17_IDX_T_VXLAN_VNI            = 24,
+	BNXT_ULP_HF17_IDX_T_VXLAN_RSVD1          = 25
 };
 
 enum bnxt_ulp_hf18 {
@@ -861,30 +836,7 @@ enum bnxt_ulp_hf_bitmask16 {
 	BNXT_ULP_HF16_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
 	BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
 	BNXT_ULP_HF16_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
-	BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000,
-	BNXT_ULP_HF16_BITMASK_I_ETH_DMAC         = 0x0000000800000000,
-	BNXT_ULP_HF16_BITMASK_I_ETH_SMAC         = 0x0000000400000000,
-	BNXT_ULP_HF16_BITMASK_I_ETH_TYPE         = 0x0000000200000000,
-	BNXT_ULP_HF16_BITMASK_IO_VLAN_CFI_PRI    = 0x0000000100000000,
-	BNXT_ULP_HF16_BITMASK_IO_VLAN_VID        = 0x0000000080000000,
-	BNXT_ULP_HF16_BITMASK_IO_VLAN_TYPE       = 0x0000000040000000,
-	BNXT_ULP_HF16_BITMASK_II_VLAN_CFI_PRI    = 0x0000000020000000,
-	BNXT_ULP_HF16_BITMASK_II_VLAN_VID        = 0x0000000010000000,
-	BNXT_ULP_HF16_BITMASK_II_VLAN_TYPE       = 0x0000000008000000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_VER         = 0x0000000004000000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_TOS         = 0x0000000002000000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_LEN         = 0x0000000001000000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_FRAG_ID     = 0x0000000000800000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_FRAG_OFF    = 0x0000000000400000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_TTL         = 0x0000000000200000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_PROTO_ID    = 0x0000000000100000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_CSUM        = 0x0000000000080000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_SRC_ADDR    = 0x0000000000040000,
-	BNXT_ULP_HF16_BITMASK_I_IPV4_DST_ADDR    = 0x0000000000020000,
-	BNXT_ULP_HF16_BITMASK_I_UDP_SRC_PORT     = 0x0000000000010000,
-	BNXT_ULP_HF16_BITMASK_I_UDP_DST_PORT     = 0x0000000000008000,
-	BNXT_ULP_HF16_BITMASK_I_UDP_LENGTH       = 0x0000000000004000,
-	BNXT_ULP_HF16_BITMASK_I_UDP_CSUM         = 0x0000000000002000
+	BNXT_ULP_HF16_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000
 };
 
 enum bnxt_ulp_hf_bitmask17 {
@@ -898,24 +850,22 @@ enum bnxt_ulp_hf_bitmask17 {
 	BNXT_ULP_HF17_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF17_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF17_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_VER         = 0x0020000000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
-	BNXT_ULP_HF17_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
-	BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
-	BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
-	BNXT_ULP_HF17_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
-	BNXT_ULP_HF17_BITMASK_O_UDP_CSUM         = 0x0000010000000000,
-	BNXT_ULP_HF17_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
-	BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
-	BNXT_ULP_HF17_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
-	BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000
+	BNXT_ULP_HF17_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF17_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF17_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF17_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF17_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF17_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF17_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF17_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF17_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF17_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF17_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF17_BITMASK_O_UDP_CSUM         = 0x0000040000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_FLAGS      = 0x0000020000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD0      = 0x0000010000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_VNI        = 0x0000008000000000,
+	BNXT_ULP_HF17_BITMASK_T_VXLAN_RSVD1      = 0x0000004000000000
 };
 
 enum bnxt_ulp_hf_bitmask18 {
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 2/8] net/bnxt: simplify representor Rx ring creation
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 1/8] net/bnxt: add support for decap action for ipv6 VXLAN flows Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 3/8] net/bnxt: fix to correct bad shift operation Somnath Kotur
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Somnath Kotur, Venkat Duvvuru

rx_queue_setup_op for representor was using a common function to
initialize the software data structures for the Rx ring. But that
routine has code to init other rings not needed for representors like
cp/agg ring etc.
Define and invoke a new function to setup structures just for the
representor Rx ring

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
 drivers/net/bnxt/bnxt_reps.c | 33 +++++++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 17010f1..d4d0a9e 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -522,6 +522,31 @@ int bnxt_vf_rep_dev_configure_op(__rte_unused struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
+static int bnxt_init_rep_rx_ring(struct bnxt_rx_queue *rxq,
+				 unsigned int socket_id)
+{
+	struct bnxt_rx_ring_info *rxr;
+	struct bnxt_ring *ring;
+
+	rxr = rte_zmalloc_socket("bnxt_rep_rx_ring",
+				 sizeof(struct bnxt_rx_ring_info),
+				 RTE_CACHE_LINE_SIZE, socket_id);
+	if (rxr == NULL)
+		return -ENOMEM;
+	rxq->rx_ring = rxr;
+
+	ring = rte_zmalloc_socket("bnxt_rep_rx_ring_struct",
+				  sizeof(struct bnxt_ring),
+				  RTE_CACHE_LINE_SIZE, socket_id);
+	if (ring == NULL)
+		return -ENOMEM;
+	rxr->rx_ring_struct = ring;
+	ring->ring_size = rte_align32pow2(rxq->nb_rx_desc);
+	ring->ring_mask = ring->ring_size - 1;
+
+	return 0;
+}
+
 int bnxt_vf_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
 			  uint16_t queue_idx,
 			  uint16_t nb_desc,
@@ -580,7 +605,7 @@ int bnxt_vf_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
 
 	rxq->nb_rx_desc = nb_desc;
 
-	rc = bnxt_init_rx_ring_struct(rxq, socket_id);
+	rc = bnxt_init_rep_rx_ring(rxq, socket_id);
 	if (rc)
 		goto out;
 
@@ -603,7 +628,7 @@ int bnxt_vf_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
 
 out:
 	if (rxq)
-		bnxt_rx_queue_release_op(rxq);
+		bnxt_vf_rep_rx_queue_release_op(rxq);
 
 	return rc;
 }
@@ -618,8 +643,8 @@ void bnxt_vf_rep_rx_queue_release_op(void *rx_queue)
 	bnxt_rx_queue_release_mbufs(rxq);
 
 	bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
-	bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
-	bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
+	rte_free(rxq->rx_ring->rx_ring_struct);
+	rte_free(rxq->rx_ring);
 
 	rte_free(rxq);
 }
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 3/8] net/bnxt: fix to correct bad shift operation
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 1/8] net/bnxt: add support for decap action for ipv6 VXLAN flows Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 2/8] net/bnxt: simplify representor Rx ring creation Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 4/8] net/bnxt: fix to honor value passed for truflow devargs Somnath Kotur
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev
  Cc: ferruh.yigit, Somnath Kotur, stable, Venkat Duvvuru, Ajit Kumar Khaparde

In page_roundup() left shifting by more than 31 bits could have
undefined behavior as the return value is int and in page_getenum()
it is possible to return a value as high as 63.
Fix that to cap the return value to less than 32.

Coverity issue: 343463
Fixes: b7778e8a1c00 ("net/bnxt: refactor to properly allocate resources for PF/VF")
Cc: stable@dpdk.org

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt_hwrm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 57d1026..04eb05e 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -52,7 +52,7 @@ static int page_getenum(size_t size)
 	if (size <= 1 << 30)
 		return 30;
 	PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
-	return sizeof(void *) * 8 - 1;
+	return sizeof(int) * 8 - 1;
 }
 
 static int page_roundup(size_t size)
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 4/8] net/bnxt: fix to honor value passed for truflow devargs
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
                   ` (2 preceding siblings ...)
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 3/8] net/bnxt: fix to correct bad shift operation Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe Somnath Kotur
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev
  Cc: ferruh.yigit, Somnath Kotur, Venkat Duvvuru, Michael Baucom,
	Ajit Kumar Khaparde

Set the TRUFLOW Enable bit in bp->flags only if the value passed in
devargs was 1.

Fixes: 313ac35ac701 ("net/bnxt: support ULP session manager init")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt_ethdev.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 05e9a6a..db2f0dd 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -5579,9 +5579,13 @@ bnxt_parse_devarg_truflow(__rte_unused const char *key,
 		return -EINVAL;
 	}
 
-	bp->flags |= BNXT_FLAG_TRUFLOW_EN;
-	if (BNXT_TRUFLOW_EN(bp))
+	if (truflow) {
+		bp->flags |= BNXT_FLAG_TRUFLOW_EN;
 		PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
+	} else {
+		bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
+		PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
+	}
 
 	return 0;
 }
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
                   ` (3 preceding siblings ...)
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 4/8] net/bnxt: fix to honor value passed for truflow devargs Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-24 14:47   ` Ferruh Yigit
  2020-09-25 10:40   ` [dpdk-dev] [PATCH v2] net/bnxt: add a " Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 6/8] net/bnxt: support for representors on remote host domain Somnath Kotur
                   ` (3 subsequent siblings)
  8 siblings, 2 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Somnath Kotur, Venkat Duvvuru

Check for devargs before invoking rep port probe.

Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
 drivers/net/bnxt/bnxt_ethdev.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index db2f0dd..84eba0b 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -6147,6 +6147,10 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	}
 	PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
 		    backing_eth_dev->data->port_id);
+
+	if (!pci_dev->device.devargs)
+		return ret;
+
 	/* probe representor ports now */
 	ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
 
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 6/8] net/bnxt: support for representors on remote host domain
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
                   ` (4 preceding siblings ...)
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 7/8] net/bnxt: fix flow match to ignore pkt type Somnath Kotur
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Somnath Kotur, Michael Baucom, Venkat Duvvuru

In the Stingray use case, Representors are conventionally run
inside the SoC domain representing functions that are on the
X86 domain. In order to support this mechanism of building
representors for endpoints that are not in the same host domain,
additional dev args have been in the PMD like so:
rep-based-pf=<physical index> rep-is-pf=<VF=0 or PF=1>
where `rep-based-pf` specifies the physical index of the base PF
that the Representor is derived off of.
Since representor(s) can be created for endpoint PFs as well,
rename struct bnxt_vf_representor to bnxt_representor and other such
dev_ops and function names.
devargs have also been extended to specify the exact CoS queue along
with flow control enablement to be used for the conduit between the
representor and the endpoint function.
This is how a sample devargs would look with all the extended devargs

-w 0000:06:02.0,host-based-truflow=1,representor=[1],rep-based-pf=8,
rep-is-pf=1,rep-q-r2f=1,rep-fc-r2f=0,rep-q-f2r=1,rep-fc-f2r=1

Also, Call CFA_PAIR_ALLOC only in case of Stingray instead of CFA_VFR_ALLOC

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
 drivers/net/bnxt/bnxt.h                 |  21 +-
 drivers/net/bnxt/bnxt_cpr.c             |   4 +-
 drivers/net/bnxt/bnxt_ethdev.c          | 349 ++++++++++++++++++++++++++++++--
 drivers/net/bnxt/bnxt_hwrm.c            |  95 +++++++++
 drivers/net/bnxt/bnxt_hwrm.h            |   4 +
 drivers/net/bnxt/bnxt_reps.c            | 192 +++++++++++-------
 drivers/net/bnxt/bnxt_reps.h            |  30 +--
 drivers/net/bnxt/hsi_struct_def_dpdk.h  | 248 +++++++++++++++++++++++
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c      |   4 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c |   4 +-
 10 files changed, 834 insertions(+), 117 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index bb26599..3dded37 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -815,15 +815,26 @@ struct bnxt {
 /**
  * Structure to store private data for each VF representor instance
  */
-struct bnxt_vf_representor {
+struct bnxt_representor {
 	uint16_t		switch_domain_id;
 	uint16_t		vf_id;
+#define BNXT_REP_IS_PF		BIT(0)
+#define BNXT_REP_Q_R2F_VALID		BIT(1)
+#define BNXT_REP_Q_F2R_VALID		BIT(2)
+#define BNXT_REP_FC_R2F_VALID		BIT(3)
+#define BNXT_REP_FC_F2R_VALID		BIT(4)
+	uint32_t		flags;
 	uint16_t		fw_fid;
 #define	BNXT_DFLT_VNIC_ID_INVALID	0xFFFF
 	uint16_t		dflt_vnic_id;
 	uint16_t		svif;
 	uint16_t		vfr_tx_cfa_action;
 	uint32_t		dpdk_port_id;
+	uint32_t		rep_based_pf;
+	uint8_t			rep_q_r2f;
+	uint8_t			rep_q_f2r;
+	uint8_t			rep_fc_r2f;
+	uint8_t			rep_fc_f2r;
 	/* Private data store of associated PF/Trusted VF */
 	struct rte_eth_dev	*parent_dev;
 	uint8_t			mac_addr[RTE_ETHER_ADDR_LEN];
@@ -839,9 +850,11 @@ struct bnxt_vf_representor {
 	uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 };
 
+#define BNXT_REP_PF(vfr_bp)	((vfr_bp)->flags & BNXT_REP_IS_PF)
+
 struct bnxt_vf_rep_tx_queue {
 	struct bnxt_tx_queue *txq;
-	struct bnxt_vf_representor *bp;
+	struct bnxt_representor *bp;
 };
 
 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
@@ -900,7 +913,7 @@ void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
 int32_t
 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
 int32_t
-bnxt_ulp_delete_vfr_default_rules(struct bnxt_vf_representor *vfr);
+bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr);
 uint16_t bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type);
 uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif,
 		       enum bnxt_ulp_intf_type type);
@@ -910,7 +923,7 @@ uint16_t bnxt_get_phy_port_id(uint16_t port);
 uint16_t bnxt_get_vport(uint16_t port);
 enum bnxt_ulp_intf_type
 bnxt_get_interface_type(uint16_t port);
-int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev);
+int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
 
 void bnxt_cancel_fc_thread(struct bnxt *bp);
 void bnxt_flow_cnt_alarm_cb(void *arg);
diff --git a/drivers/net/bnxt/bnxt_cpr.c b/drivers/net/bnxt/bnxt_cpr.c
index 464ca8b..8311e26 100644
--- a/drivers/net/bnxt/bnxt_cpr.c
+++ b/drivers/net/bnxt/bnxt_cpr.c
@@ -51,7 +51,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp,
 				 struct hwrm_async_event_cmpl *async_cmp)
 {
 	uint16_t fid, vnic_state, parent_id, vf_fid, vf_id;
-	struct bnxt_vf_representor *vf_rep_bp;
+	struct bnxt_representor *vf_rep_bp;
 	struct rte_eth_dev *eth_dev;
 	bool vfr_found = false;
 	uint32_t event_data;
@@ -91,7 +91,7 @@ bnxt_process_default_vnic_change(struct bnxt *bp,
 	if (!vfr_found)
 		return;
 
-	bnxt_vf_rep_dev_start_op(eth_dev);
+	bnxt_rep_dev_start_op(eth_dev);
 }
 
 /*
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 84eba0b..d7c8a3a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -99,12 +99,24 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
 #define BNXT_DEVARG_FLOW_XSTAT	"flow-xstat"
 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 #define BNXT_DEVARG_REPRESENTOR	"representor"
+#define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
+#define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
+#define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
+#define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
+#define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
+#define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 
 static const char *const bnxt_dev_args[] = {
 	BNXT_DEVARG_REPRESENTOR,
 	BNXT_DEVARG_TRUFLOW,
 	BNXT_DEVARG_FLOW_XSTAT,
 	BNXT_DEVARG_MAX_NUM_KFLOWS,
+	BNXT_DEVARG_REP_BASED_PF,
+	BNXT_DEVARG_REP_IS_PF,
+	BNXT_DEVARG_REP_Q_R2F,
+	BNXT_DEVARG_REP_Q_F2R,
+	BNXT_DEVARG_REP_FC_R2F,
+	BNXT_DEVARG_REP_FC_F2R,
 	NULL
 };
 
@@ -121,6 +133,36 @@ static const char *const bnxt_dev_args[] = {
 #define	BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)	((flow_xstat) > 1)
 
 /*
+ * rep_is_pf == false to indicate VF representor
+ * rep_is_pf == true to indicate PF representor
+ */
+#define	BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)	((rep_is_pf) > 1)
+
+/*
+ * rep_based_pf == Physical index of the PF
+ */
+#define	BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)	((rep_based_pf) > 15)
+/*
+ * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
+ */
+#define	BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)	((rep_q_r2f) > 3)
+
+/*
+ * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
+ */
+#define	BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)	((rep_q_f2r) > 3)
+
+/*
+ * rep_fc_r2f == Flow control for the representor to endpoint direction
+ */
+#define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)	((rep_fc_r2f) > 1)
+
+/*
+ * rep_fc_f2r == Flow control for the endpoint to representor direction
+ */
+#define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)	((rep_fc_f2r) > 1)
+
+/*
  * max_num_kflows must be >= 32
  * and must be a power-of-2 supported value
  * return: 1 -> invalid
@@ -1316,7 +1358,7 @@ static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 	rte_intr_disable(intr_handle);
 
 	/* Stop the child representors for this device */
-	bnxt_vf_rep_stop_all(bp);
+	bnxt_rep_stop_all(bp);
 
 	/* delete the bnxt ULP port details */
 	bnxt_ulp_port_deinit(bp);
@@ -3730,7 +3772,7 @@ bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
 		return -EIO;
 
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
-		struct bnxt_vf_representor *vfr = dev->data->dev_private;
+		struct bnxt_representor *vfr = dev->data->dev_private;
 		bp = vfr->parent_dev->data->dev_private;
 		/* parent is deleted while children are still valid */
 		if (!bp) {
@@ -5186,7 +5228,7 @@ bnxt_get_svif(uint16_t port_id, bool func_svif,
 
 	eth_dev = &rte_eth_devices[port_id];
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
-		struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
+		struct bnxt_representor *vfr = eth_dev->data->dev_private;
 		if (!vfr)
 			return 0;
 
@@ -5210,7 +5252,7 @@ bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
 
 	eth_dev = &rte_eth_devices[port];
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
-		struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
+		struct bnxt_representor *vfr = eth_dev->data->dev_private;
 		if (!vfr)
 			return 0;
 
@@ -5235,7 +5277,7 @@ bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
 
 	eth_dev = &rte_eth_devices[port];
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
-		struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
+		struct bnxt_representor *vfr = eth_dev->data->dev_private;
 		if (!vfr)
 			return 0;
 
@@ -5274,7 +5316,7 @@ bnxt_get_interface_type(uint16_t port)
 uint16_t
 bnxt_get_phy_port_id(uint16_t port_id)
 {
-	struct bnxt_vf_representor *vfr;
+	struct bnxt_representor *vfr;
 	struct rte_eth_dev *eth_dev;
 	struct bnxt *bp;
 
@@ -5300,7 +5342,7 @@ bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
 
 	eth_dev = &rte_eth_devices[port_id];
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
-		struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
+		struct bnxt_representor *vfr = eth_dev->data->dev_private;
 		if (!vfr)
 			return 0;
 
@@ -5661,6 +5703,227 @@ bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
 	return 0;
 }
 
+static int
+bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
+			    const char *value, void *opaque_arg)
+{
+	struct bnxt_representor *vfr_bp = opaque_arg;
+	unsigned long rep_is_pf;
+	char *end = NULL;
+
+	if (!value || !opaque_arg) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_is_pf devargs.\n");
+		return -EINVAL;
+	}
+
+	rep_is_pf = strtoul(value, &end, 10);
+	if (end == NULL || *end != '\0' ||
+	    (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_is_pf devargs.\n");
+		return -EINVAL;
+	}
+
+	if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid value passed to rep_is_pf devargs.\n");
+		return -EINVAL;
+	}
+
+	vfr_bp->flags |= rep_is_pf;
+	if (BNXT_REP_PF(vfr_bp))
+		PMD_DRV_LOG(INFO, "PF representor\n");
+	else
+		PMD_DRV_LOG(INFO, "VF representor\n");
+
+	return 0;
+}
+
+static int
+bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
+			       const char *value, void *opaque_arg)
+{
+	struct bnxt_representor *vfr_bp = opaque_arg;
+	unsigned long rep_based_pf;
+	char *end = NULL;
+
+	if (!value || !opaque_arg) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_based_pf "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	rep_based_pf = strtoul(value, &end, 10);
+	if (end == NULL || *end != '\0' ||
+	    (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_based_pf "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid value passed to rep_based_pf devargs.\n");
+		return -EINVAL;
+	}
+
+	vfr_bp->rep_based_pf = rep_based_pf;
+	PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
+
+	return 0;
+}
+
+static int
+bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
+			    const char *value, void *opaque_arg)
+{
+	struct bnxt_representor *vfr_bp = opaque_arg;
+	unsigned long rep_q_r2f;
+	char *end = NULL;
+
+	if (!value || !opaque_arg) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_q_r2f "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	rep_q_r2f = strtoul(value, &end, 10);
+	if (end == NULL || *end != '\0' ||
+	    (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_q_r2f "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid value passed to rep_q_r2f devargs.\n");
+		return -EINVAL;
+	}
+
+	vfr_bp->rep_q_r2f = rep_q_r2f;
+	vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
+	PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
+
+	return 0;
+}
+
+static int
+bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
+			    const char *value, void *opaque_arg)
+{
+	struct bnxt_representor *vfr_bp = opaque_arg;
+	unsigned long rep_q_f2r;
+	char *end = NULL;
+
+	if (!value || !opaque_arg) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_q_f2r "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	rep_q_f2r = strtoul(value, &end, 10);
+	if (end == NULL || *end != '\0' ||
+	    (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_q_f2r "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid value passed to rep_q_f2r devargs.\n");
+		return -EINVAL;
+	}
+
+	vfr_bp->rep_q_f2r = rep_q_f2r;
+	vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
+	PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
+
+	return 0;
+}
+
+static int
+bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
+			     const char *value, void *opaque_arg)
+{
+	struct bnxt_representor *vfr_bp = opaque_arg;
+	unsigned long rep_fc_r2f;
+	char *end = NULL;
+
+	if (!value || !opaque_arg) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_fc_r2f "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	rep_fc_r2f = strtoul(value, &end, 10);
+	if (end == NULL || *end != '\0' ||
+	    (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_fc_r2f "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid value passed to rep_fc_r2f devargs.\n");
+		return -EINVAL;
+	}
+
+	vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
+	vfr_bp->rep_fc_r2f = rep_fc_r2f;
+	PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
+
+	return 0;
+}
+
+static int
+bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
+			     const char *value, void *opaque_arg)
+{
+	struct bnxt_representor *vfr_bp = opaque_arg;
+	unsigned long rep_fc_f2r;
+	char *end = NULL;
+
+	if (!value || !opaque_arg) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_fc_f2r "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	rep_fc_f2r = strtoul(value, &end, 10);
+	if (end == NULL || *end != '\0' ||
+	    (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid parameter passed to rep_fc_f2r "
+			    "devargs.\n");
+		return -EINVAL;
+	}
+
+	if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
+		PMD_DRV_LOG(ERR,
+			    "Invalid value passed to rep_fc_f2r devargs.\n");
+		return -EINVAL;
+	}
+
+	vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
+	vfr_bp->rep_fc_f2r = rep_fc_f2r;
+	PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
+
+	return 0;
+}
+
 static void
 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
 {
@@ -5957,7 +6220,7 @@ static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
 			continue;
 		PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
 			    vf_rep_eth_dev->data->port_id);
-		rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
+		rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
 	}
 	PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
 		    eth_dev->data->port_id);
@@ -6019,13 +6282,15 @@ static int bnxt_init_rep_info(struct bnxt *bp)
 
 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 			       struct rte_eth_devargs eth_da,
-			       struct rte_eth_dev *backing_eth_dev)
+			       struct rte_eth_dev *backing_eth_dev,
+			       const char *dev_args)
 {
 	struct rte_eth_dev *vf_rep_eth_dev;
 	char name[RTE_ETH_NAME_MAX_LEN];
 	struct bnxt *backing_bp;
 	uint16_t num_rep;
 	int i, ret = 0;
+	struct rte_kvargs *kvlist;
 
 	num_rep = eth_da.nb_representor_ports;
 	if (num_rep > BNXT_MAX_VF_REPS) {
@@ -6056,7 +6321,7 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 		return 0;
 
 	for (i = 0; i < num_rep; i++) {
-		struct bnxt_vf_representor representor = {
+		struct bnxt_representor representor = {
 			.vf_id = eth_da.representor_ports[i],
 			.switch_domain_id = backing_bp->switch_domain_id,
 			.parent_dev = backing_eth_dev
@@ -6072,10 +6337,62 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 		snprintf(name, sizeof(name), "net_%s_representor_%d",
 			 pci_dev->device.name, eth_da.representor_ports[i]);
 
+		kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
+		if (kvlist) {
+			/*
+			 * Handler for "rep_is_pf" devarg.
+			 * Invoked as for ex: "-w 000:00:0d.0,
+			 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
+			 */
+			rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
+					   bnxt_parse_devarg_rep_is_pf,
+					   (void *)&representor);
+			/*
+			 * Handler for "rep_based_pf" devarg.
+			 * Invoked as for ex: "-w 000:00:0d.0,
+			 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
+			 */
+			rte_kvargs_process(kvlist, BNXT_DEVARG_REP_BASED_PF,
+					   bnxt_parse_devarg_rep_based_pf,
+					   (void *)&representor);
+			/*
+			 * Handler for "rep_based_pf" devarg.
+			 * Invoked as for ex: "-w 000:00:0d.0,
+			 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
+			 */
+			rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
+					   bnxt_parse_devarg_rep_q_r2f,
+					   (void *)&representor);
+			/*
+			 * Handler for "rep_based_pf" devarg.
+			 * Invoked as for ex: "-w 000:00:0d.0,
+			 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
+			 */
+			rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
+					   bnxt_parse_devarg_rep_q_f2r,
+					   (void *)&representor);
+			/*
+			 * Handler for "rep_based_pf" devarg.
+			 * Invoked as for ex: "-w 000:00:0d.0,
+			 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
+			 */
+			rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
+					   bnxt_parse_devarg_rep_fc_r2f,
+					   (void *)&representor);
+			/*
+			 * Handler for "rep_based_pf" devarg.
+			 * Invoked as for ex: "-w 000:00:0d.0,
+			 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
+			 */
+			rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
+					   bnxt_parse_devarg_rep_fc_f2r,
+					   (void *)&representor);
+		}
+
 		ret = rte_eth_dev_create(&pci_dev->device, name,
-					 sizeof(struct bnxt_vf_representor),
+					 sizeof(struct bnxt_representor),
 					 NULL, NULL,
-					 bnxt_vf_representor_init,
+					 bnxt_representor_init,
 					 &representor);
 		if (ret) {
 			PMD_DRV_LOG(ERR, "failed to create bnxt vf "
@@ -6092,10 +6409,11 @@ static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
 		}
 
 		PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
-				backing_eth_dev->data->port_id);
+			    backing_eth_dev->data->port_id);
 		backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
 							 vf_rep_eth_dev;
 		backing_bp->num_reps++;
+
 	}
 
 	return 0;
@@ -6152,7 +6470,8 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 		return ret;
 
 	/* probe representor ports now */
-	ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
+	ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev,
+				  pci_dev->device.devargs->args);
 
 	return ret;
 }
@@ -6173,7 +6492,7 @@ static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 		if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 			return rte_eth_dev_destroy(eth_dev,
-						   bnxt_vf_representor_uninit);
+						   bnxt_representor_uninit);
 		else
 			return rte_eth_dev_destroy(eth_dev,
 						   bnxt_dev_uninit);
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 04eb05e..f25cdf0 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -5556,3 +5556,98 @@ int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
 	PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
 	return rc;
 }
+
+int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
+				uint16_t *first_vf_id)
+{
+	int rc = 0;
+	struct hwrm_func_qcaps_input req = {.req_type = 0 };
+	struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
+
+	HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
+
+	req.fid = rte_cpu_to_le_16(fid);
+
+	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+
+	HWRM_CHECK_RESULT();
+
+	if (first_vf_id)
+		*first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
+
+	HWRM_UNLOCK();
+
+	return rc;
+}
+
+int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
+{
+	struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
+	struct hwrm_cfa_pair_alloc_input req = {0};
+	int rc;
+
+	if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
+		PMD_DRV_LOG(DEBUG,
+			    "Not a PF or trusted VF. Command not supported\n");
+		return 0;
+	}
+
+	HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
+	req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
+	snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
+		 bp->eth_dev->data->name, rep_bp->vf_id);
+
+	req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
+	req.vf_b_id = rte_cpu_to_le_16(rep_bp->vf_id);
+	req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
+	req.host_b_id = 1; /* TBD - Confirm if this is OK */
+
+	req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
+			HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
+	req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
+			HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
+	req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
+			HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
+	req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
+			HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
+
+	req.q_ab = rep_bp->rep_q_r2f;
+	req.q_ba = rep_bp->rep_q_f2r;
+	req.fc_ab = rep_bp->rep_fc_r2f;
+	req.fc_ba = rep_bp->rep_fc_f2r;
+
+	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+	HWRM_CHECK_RESULT();
+
+	HWRM_UNLOCK();
+	PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
+		    BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
+	return rc;
+}
+
+int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
+{
+	struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
+	struct hwrm_cfa_pair_free_input req = {0};
+	int rc;
+
+	if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
+		PMD_DRV_LOG(DEBUG,
+			    "Not a PF or trusted VF. Command not supported\n");
+		return 0;
+	}
+
+	HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
+	snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
+		 bp->eth_dev->data->name, rep_bp->vf_id);
+	req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
+	req.vf_id = rte_cpu_to_le_16(rep_bp->vf_id);
+	req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
+
+	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
+	HWRM_CHECK_RESULT();
+	HWRM_UNLOCK();
+	PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
+		    rep_bp->vf_id);
+	return rc;
+}
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index b5ec23a..77ae0b7 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -283,4 +283,8 @@ int bnxt_clear_one_vnic_filter(struct bnxt *bp,
 int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx);
 int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx);
 void bnxt_hwrm_free_vf_info(struct bnxt *bp);
+int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
+				uint16_t *first_vf_id);
+int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep);
+int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep);
 #endif
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index d4d0a9e..b76487f 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -16,19 +16,19 @@
 #include "ulp_port_db.h"
 #include "ulp_flow_db.h"
 
-static const struct eth_dev_ops bnxt_vf_rep_dev_ops = {
-	.dev_infos_get = bnxt_vf_rep_dev_info_get_op,
-	.dev_configure = bnxt_vf_rep_dev_configure_op,
-	.dev_start = bnxt_vf_rep_dev_start_op,
-	.rx_queue_setup = bnxt_vf_rep_rx_queue_setup_op,
-	.rx_queue_release = bnxt_vf_rep_rx_queue_release_op,
-	.tx_queue_setup = bnxt_vf_rep_tx_queue_setup_op,
-	.tx_queue_release = bnxt_vf_rep_tx_queue_release_op,
-	.link_update = bnxt_vf_rep_link_update_op,
-	.dev_close = bnxt_vf_rep_dev_close_op,
-	.dev_stop = bnxt_vf_rep_dev_stop_op,
-	.stats_get = bnxt_vf_rep_stats_get_op,
-	.stats_reset = bnxt_vf_rep_stats_reset_op,
+static const struct eth_dev_ops bnxt_rep_dev_ops = {
+	.dev_infos_get = bnxt_rep_dev_info_get_op,
+	.dev_configure = bnxt_rep_dev_configure_op,
+	.dev_start = bnxt_rep_dev_start_op,
+	.rx_queue_setup = bnxt_rep_rx_queue_setup_op,
+	.rx_queue_release = bnxt_rep_rx_queue_release_op,
+	.tx_queue_setup = bnxt_rep_tx_queue_setup_op,
+	.tx_queue_release = bnxt_rep_tx_queue_release_op,
+	.link_update = bnxt_rep_link_update_op,
+	.dev_close = bnxt_rep_dev_close_op,
+	.dev_stop = bnxt_rep_dev_stop_op,
+	.stats_get = bnxt_rep_stats_get_op,
+	.stats_reset = bnxt_rep_stats_reset_op,
 	.filter_ctrl = bnxt_filter_ctrl_op
 };
 
@@ -39,7 +39,7 @@ bnxt_vfr_recv(uint16_t port_id, uint16_t queue_id, struct rte_mbuf *mbuf)
 	struct bnxt_rx_ring_info *rep_rxr;
 	struct bnxt_rx_queue *rep_rxq;
 	struct rte_eth_dev *vfr_eth_dev;
-	struct bnxt_vf_representor *vfr_bp;
+	struct bnxt_representor *vfr_bp;
 	uint16_t mask;
 	uint8_t que;
 
@@ -72,7 +72,7 @@ bnxt_vfr_recv(uint16_t port_id, uint16_t queue_id, struct rte_mbuf *mbuf)
 }
 
 static uint16_t
-bnxt_vf_rep_rx_burst(void *rx_queue,
+bnxt_rep_rx_burst(void *rx_queue,
 		     struct rte_mbuf **rx_pkts,
 		     uint16_t nb_pkts)
 {
@@ -102,14 +102,14 @@ bnxt_vf_rep_rx_burst(void *rx_queue,
 }
 
 static uint16_t
-bnxt_vf_rep_tx_burst(void *tx_queue,
+bnxt_rep_tx_burst(void *tx_queue,
 		     struct rte_mbuf **tx_pkts,
 		     __rte_unused uint16_t nb_pkts)
 {
 	struct bnxt_vf_rep_tx_queue *vfr_txq = tx_queue;
 	struct bnxt_tx_queue *ptxq;
 	struct bnxt *parent;
-	struct  bnxt_vf_representor *vf_rep_bp;
+	struct  bnxt_representor *vf_rep_bp;
 	int qid;
 	int rc;
 	int i;
@@ -138,7 +138,7 @@ bnxt_vf_rep_tx_burst(void *tx_queue,
 }
 
 static int
-bnxt_get_dflt_vnic_svif(struct bnxt *bp, struct bnxt_vf_representor *vf_rep_bp)
+bnxt_get_dflt_vnic_svif(struct bnxt *bp, struct bnxt_representor *vf_rep_bp)
 {
 	struct bnxt_rep_info *rep_info;
 	int rc;
@@ -163,18 +163,26 @@ bnxt_get_dflt_vnic_svif(struct bnxt *bp, struct bnxt_vf_representor *vf_rep_bp)
 	return rc;
 }
 
-int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
+int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params)
 {
-	struct bnxt_vf_representor *vf_rep_bp = eth_dev->data->dev_private;
-	struct bnxt_vf_representor *rep_params =
-				 (struct bnxt_vf_representor *)params;
+	struct bnxt_representor *vf_rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_params =
+				 (struct bnxt_representor *)params;
 	struct rte_eth_link *link;
 	struct bnxt *parent_bp;
+	uint16_t first_vf_id;
+	int rc = 0;
 
 	PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR init\n", eth_dev->data->port_id);
 	vf_rep_bp->vf_id = rep_params->vf_id;
 	vf_rep_bp->switch_domain_id = rep_params->switch_domain_id;
 	vf_rep_bp->parent_dev = rep_params->parent_dev;
+	vf_rep_bp->rep_based_pf = rep_params->rep_based_pf;
+	vf_rep_bp->flags = rep_params->flags;
+	vf_rep_bp->rep_q_r2f = rep_params->rep_q_r2f;
+	vf_rep_bp->rep_q_f2r = rep_params->rep_q_f2r;
+	vf_rep_bp->rep_fc_r2f = rep_params->rep_fc_r2f;
+	vf_rep_bp->rep_fc_f2r = rep_params->rep_fc_f2r;
 
 	eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
 	eth_dev->data->representor_id = rep_params->vf_id;
@@ -184,13 +192,13 @@ int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
 	       sizeof(vf_rep_bp->mac_addr));
 	eth_dev->data->mac_addrs =
 		(struct rte_ether_addr *)&vf_rep_bp->mac_addr;
-	eth_dev->dev_ops = &bnxt_vf_rep_dev_ops;
+	eth_dev->dev_ops = &bnxt_rep_dev_ops;
 
 	/* No data-path, but need stub Rx/Tx functions to avoid crash
 	 * when testing with ovs-dpdk
 	 */
-	eth_dev->rx_pkt_burst = bnxt_vf_rep_rx_burst;
-	eth_dev->tx_pkt_burst = bnxt_vf_rep_tx_burst;
+	eth_dev->rx_pkt_burst = bnxt_rep_rx_burst;
+	eth_dev->tx_pkt_burst = bnxt_rep_tx_burst;
 	/* Link state. Inherited from PF or trusted VF */
 	parent_bp = vf_rep_bp->parent_dev->data->dev_private;
 	link = &parent_bp->eth_dev->data->dev_link;
@@ -211,17 +219,39 @@ int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params)
 		    "Switch domain id %d: Representor Device %d init done\n",
 		    vf_rep_bp->switch_domain_id, vf_rep_bp->vf_id);
 
-	vf_rep_bp->fw_fid = rep_params->vf_id + parent_bp->first_vf_id;
+	if (vf_rep_bp->rep_based_pf) {
+		vf_rep_bp->fw_fid = vf_rep_bp->rep_based_pf + 1;
+		if (!(BNXT_REP_PF(vf_rep_bp))) {
+			/* VF representor for the remote PF,get first_vf_id */
+			rc = bnxt_hwrm_first_vf_id_query(parent_bp,
+							 vf_rep_bp->fw_fid,
+							 &first_vf_id);
+			if (rc)
+				return rc;
+			if (first_vf_id == 0xffff) {
+				PMD_DRV_LOG(ERR,
+					    "Invalid first_vf_id fid:%x\n",
+					    vf_rep_bp->fw_fid);
+				return -EINVAL;
+			}
+			PMD_DRV_LOG(INFO, "first_vf_id = %x parent_fid:%x\n",
+				    first_vf_id, vf_rep_bp->fw_fid);
+			vf_rep_bp->fw_fid = rep_params->vf_id + first_vf_id;
+		}
+	}  else {
+		vf_rep_bp->fw_fid = rep_params->vf_id + parent_bp->first_vf_id;
+	}
+
 	PMD_DRV_LOG(INFO, "vf_rep->fw_fid = %d\n", vf_rep_bp->fw_fid);
 
 	return 0;
 }
 
-int bnxt_vf_representor_uninit(struct rte_eth_dev *eth_dev)
+int bnxt_representor_uninit(struct rte_eth_dev *eth_dev)
 {
 	struct bnxt *parent_bp;
-	struct bnxt_vf_representor *rep =
-		(struct bnxt_vf_representor *)eth_dev->data->dev_private;
+	struct bnxt_representor *rep =
+		(struct bnxt_representor *)eth_dev->data->dev_private;
 	uint16_t vf_id;
 
 	PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR uninit\n", eth_dev->data->port_id);
@@ -244,11 +274,11 @@ int bnxt_vf_representor_uninit(struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
-int bnxt_vf_rep_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_compl)
+int bnxt_rep_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_compl)
 {
 	struct bnxt *parent_bp;
-	struct bnxt_vf_representor *rep =
-		(struct bnxt_vf_representor *)eth_dev->data->dev_private;
+	struct bnxt_representor *rep =
+		(struct bnxt_representor *)eth_dev->data->dev_private;
 	struct rte_eth_link *link;
 	int rc;
 
@@ -273,7 +303,7 @@ int bnxt_vf_rep_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_compl)
 static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 {
 	int rc;
-	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
+	struct bnxt_representor *vfr = vfr_ethdev->data->dev_private;
 	struct rte_eth_dev *parent_dev = vfr->parent_dev;
 	struct bnxt *parent_bp = parent_dev->data->dev_private;
 
@@ -299,7 +329,12 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 	}
 	/* update the port id so you can backtrack to ethdev */
 	vfr->dpdk_port_id = vfr_ethdev->data->port_id;
-	rc = bnxt_hwrm_cfa_vfr_alloc(parent_bp, vfr->vf_id);
+
+	if (BNXT_STINGRAY(parent_bp)) {
+		rc = bnxt_hwrm_cfa_pair_alloc(parent_bp, vfr);
+	} else {
+		rc = bnxt_hwrm_cfa_vfr_alloc(parent_bp, vfr->vf_id);
+	}
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed in hwrm vfr alloc vfr:%u rc=%d\n",
 			    vfr->vf_id, rc);
@@ -313,7 +348,7 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 {
 	int rc = 0;
-	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
+	struct bnxt_representor *vfr = vfr_ethdev->data->dev_private;
 	struct bnxt *parent_bp;
 
 	if (!vfr || !vfr->parent_dev) {
@@ -350,7 +385,7 @@ static int bnxt_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 	return rc;
 }
 
-static void bnxt_vf_rep_free_rx_mbufs(struct bnxt_vf_representor *rep_bp)
+static void bnxt_rep_free_rx_mbufs(struct bnxt_representor *rep_bp)
 {
 	struct bnxt_rx_queue *rxq;
 	unsigned int i;
@@ -361,9 +396,9 @@ static void bnxt_vf_rep_free_rx_mbufs(struct bnxt_vf_representor *rep_bp)
 	}
 }
 
-int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
+int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 {
-	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_bp = eth_dev->data->dev_private;
 	struct bnxt_rep_info *rep_info;
 	struct bnxt *parent_bp;
 	int rc;
@@ -385,23 +420,23 @@ int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev)
 	rc = bnxt_vfr_alloc(eth_dev);
 	if (rc) {
 		eth_dev->data->dev_link.link_status = 0;
-		bnxt_vf_rep_free_rx_mbufs(rep_bp);
+		bnxt_rep_free_rx_mbufs(rep_bp);
 		return rc;
 	}
-	eth_dev->rx_pkt_burst = &bnxt_vf_rep_rx_burst;
-	eth_dev->tx_pkt_burst = &bnxt_vf_rep_tx_burst;
-	bnxt_vf_rep_link_update_op(eth_dev, 1);
+	eth_dev->rx_pkt_burst = &bnxt_rep_rx_burst;
+	eth_dev->tx_pkt_burst = &bnxt_rep_tx_burst;
+	bnxt_rep_link_update_op(eth_dev, 1);
 
 	return 0;
 }
 
-static int bnxt_tf_vfr_free(struct bnxt_vf_representor *vfr)
+static int bnxt_tf_vfr_free(struct bnxt_representor *vfr)
 {
 	BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR ulp free\n", vfr->dpdk_port_id);
 	return bnxt_ulp_delete_vfr_default_rules(vfr);
 }
 
-static int bnxt_vfr_free(struct bnxt_vf_representor *vfr)
+static int bnxt_vfr_free(struct bnxt_representor *vfr)
 {
 	int rc = 0;
 	struct bnxt *parent_bp;
@@ -434,14 +469,17 @@ static int bnxt_vfr_free(struct bnxt_vf_representor *vfr)
 		    vfr->vf_id);
 	vfr->vfr_tx_cfa_action = 0;
 
-	rc = bnxt_hwrm_cfa_vfr_free(parent_bp, vfr->vf_id);
+	if (BNXT_STINGRAY(parent_bp))
+		rc = bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
+	else
+		rc = bnxt_hwrm_cfa_vfr_free(parent_bp, vfr->vf_id);
 
 	return rc;
 }
 
-void bnxt_vf_rep_dev_stop_op(struct rte_eth_dev *eth_dev)
+void bnxt_rep_dev_stop_op(struct rte_eth_dev *eth_dev)
 {
-	struct bnxt_vf_representor *vfr_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *vfr_bp = eth_dev->data->dev_private;
 
 	/* Avoid crashes as we are about to free queues */
 	eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
@@ -454,19 +492,19 @@ void bnxt_vf_rep_dev_stop_op(struct rte_eth_dev *eth_dev)
 	if (eth_dev->data->dev_started)
 		eth_dev->data->dev_link.link_status = 0;
 
-	bnxt_vf_rep_free_rx_mbufs(vfr_bp);
+	bnxt_rep_free_rx_mbufs(vfr_bp);
 }
 
-void bnxt_vf_rep_dev_close_op(struct rte_eth_dev *eth_dev)
+void bnxt_rep_dev_close_op(struct rte_eth_dev *eth_dev)
 {
 	BNXT_TF_DBG(DEBUG, "BNXT Port:%d VFR close\n", eth_dev->data->port_id);
-	bnxt_vf_representor_uninit(eth_dev);
+	bnxt_representor_uninit(eth_dev);
 }
 
-int bnxt_vf_rep_dev_info_get_op(struct rte_eth_dev *eth_dev,
+int bnxt_rep_dev_info_get_op(struct rte_eth_dev *eth_dev,
 				struct rte_eth_dev_info *dev_info)
 {
-	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_bp = eth_dev->data->dev_private;
 	struct bnxt *parent_bp;
 	unsigned int max_rx_rings;
 	int rc = 0;
@@ -510,9 +548,9 @@ int bnxt_vf_rep_dev_info_get_op(struct rte_eth_dev *eth_dev,
 	return 0;
 }
 
-int bnxt_vf_rep_dev_configure_op(__rte_unused struct rte_eth_dev *eth_dev)
+int bnxt_rep_dev_configure_op(__rte_unused struct rte_eth_dev *eth_dev)
 {
-	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_bp = eth_dev->data->dev_private;
 
 	PMD_DRV_LOG(DEBUG, "Representor dev_configure_op\n");
 	rep_bp->rx_queues = (void *)eth_dev->data->rx_queues;
@@ -547,14 +585,14 @@ static int bnxt_init_rep_rx_ring(struct bnxt_rx_queue *rxq,
 	return 0;
 }
 
-int bnxt_vf_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
-			  uint16_t queue_idx,
-			  uint16_t nb_desc,
-			  unsigned int socket_id,
-			  __rte_unused const struct rte_eth_rxconf *rx_conf,
-			  __rte_unused struct rte_mempool *mp)
+int bnxt_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
+			       uint16_t queue_idx,
+			       uint16_t nb_desc,
+			       unsigned int socket_id,
+			       __rte_unused const struct rte_eth_rxconf *rx_conf,
+			       __rte_unused struct rte_mempool *mp)
 {
-	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_bp = eth_dev->data->dev_private;
 	struct bnxt *parent_bp = rep_bp->parent_dev->data->dev_private;
 	struct bnxt_rx_queue *parent_rxq;
 	struct bnxt_rx_queue *rxq;
@@ -628,12 +666,12 @@ int bnxt_vf_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
 
 out:
 	if (rxq)
-		bnxt_vf_rep_rx_queue_release_op(rxq);
+		bnxt_rep_rx_queue_release_op(rxq);
 
 	return rc;
 }
 
-void bnxt_vf_rep_rx_queue_release_op(void *rx_queue)
+void bnxt_rep_rx_queue_release_op(void *rx_queue)
 {
 	struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
 
@@ -649,13 +687,13 @@ void bnxt_vf_rep_rx_queue_release_op(void *rx_queue)
 	rte_free(rxq);
 }
 
-int bnxt_vf_rep_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
-			  uint16_t queue_idx,
-			  uint16_t nb_desc,
-			  unsigned int socket_id,
-			  __rte_unused const struct rte_eth_txconf *tx_conf)
+int bnxt_rep_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
+			       uint16_t queue_idx,
+			       uint16_t nb_desc,
+			       unsigned int socket_id,
+			       __rte_unused const struct rte_eth_txconf *tx_conf)
 {
-	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_bp = eth_dev->data->dev_private;
 	struct bnxt *parent_bp = rep_bp->parent_dev->data->dev_private;
 	struct bnxt_tx_queue *parent_txq, *txq;
 	struct bnxt_vf_rep_tx_queue *vfr_txq;
@@ -690,7 +728,7 @@ int bnxt_vf_rep_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
 
 	if (eth_dev->data->tx_queues) {
 		vfr_txq = eth_dev->data->tx_queues[queue_idx];
-		bnxt_vf_rep_tx_queue_release_op(vfr_txq);
+		bnxt_rep_tx_queue_release_op(vfr_txq);
 		vfr_txq = NULL;
 	}
 
@@ -720,7 +758,7 @@ int bnxt_vf_rep_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
 	return 0;
 }
 
-void bnxt_vf_rep_tx_queue_release_op(void *tx_queue)
+void bnxt_rep_tx_queue_release_op(void *tx_queue)
 {
 	struct bnxt_vf_rep_tx_queue *vfr_txq = tx_queue;
 
@@ -731,10 +769,10 @@ void bnxt_vf_rep_tx_queue_release_op(void *tx_queue)
 	rte_free(vfr_txq);
 }
 
-int bnxt_vf_rep_stats_get_op(struct rte_eth_dev *eth_dev,
+int bnxt_rep_stats_get_op(struct rte_eth_dev *eth_dev,
 			     struct rte_eth_stats *stats)
 {
-	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_bp = eth_dev->data->dev_private;
 	int i;
 
 	memset(stats, 0, sizeof(*stats));
@@ -755,9 +793,9 @@ int bnxt_vf_rep_stats_get_op(struct rte_eth_dev *eth_dev,
 	return 0;
 }
 
-int bnxt_vf_rep_stats_reset_op(struct rte_eth_dev *eth_dev)
+int bnxt_rep_stats_reset_op(struct rte_eth_dev *eth_dev)
 {
-	struct bnxt_vf_representor *rep_bp = eth_dev->data->dev_private;
+	struct bnxt_representor *rep_bp = eth_dev->data->dev_private;
 	int i;
 
 	for (i = 0; i < BNXT_MAX_VF_REP_RINGS; i++) {
@@ -770,7 +808,7 @@ int bnxt_vf_rep_stats_reset_op(struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
-void bnxt_vf_rep_stop_all(struct bnxt *bp)
+void bnxt_rep_stop_all(struct bnxt *bp)
 {
 	uint16_t vf_id;
 	struct rte_eth_dev *rep_eth_dev;
@@ -783,6 +821,6 @@ void bnxt_vf_rep_stop_all(struct bnxt *bp)
 		rep_eth_dev = bp->rep_info[vf_id].vfr_eth_dev;
 		if (!rep_eth_dev)
 			continue;
-		bnxt_vf_rep_dev_stop_op(rep_eth_dev);
+		bnxt_rep_dev_stop_op(rep_eth_dev);
 	}
 }
diff --git a/drivers/net/bnxt/bnxt_reps.h b/drivers/net/bnxt/bnxt_reps.h
index 3239e03..3159f68 100644
--- a/drivers/net/bnxt/bnxt_reps.h
+++ b/drivers/net/bnxt/bnxt_reps.h
@@ -21,33 +21,33 @@
 
 uint16_t
 bnxt_vfr_recv(uint16_t port_id, uint16_t queue_id, struct rte_mbuf *mbuf);
-int bnxt_vf_representor_init(struct rte_eth_dev *eth_dev, void *params);
-int bnxt_vf_representor_uninit(struct rte_eth_dev *eth_dev);
-int bnxt_vf_rep_dev_info_get_op(struct rte_eth_dev *eth_dev,
+int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params);
+int bnxt_representor_uninit(struct rte_eth_dev *eth_dev);
+int bnxt_rep_dev_info_get_op(struct rte_eth_dev *eth_dev,
 				struct rte_eth_dev_info *dev_info);
-int bnxt_vf_rep_dev_configure_op(struct rte_eth_dev *eth_dev);
+int bnxt_rep_dev_configure_op(struct rte_eth_dev *eth_dev);
 
-int bnxt_vf_rep_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_compl);
-int bnxt_vf_rep_dev_start_op(struct rte_eth_dev *eth_dev);
-int bnxt_vf_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
+int bnxt_rep_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_compl);
+int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
+int bnxt_rep_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
 				  __rte_unused uint16_t queue_idx,
 				  __rte_unused uint16_t nb_desc,
 				  __rte_unused unsigned int socket_id,
 				  __rte_unused const struct rte_eth_rxconf *
 				  rx_conf,
 				  __rte_unused struct rte_mempool *mp);
-int bnxt_vf_rep_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
+int bnxt_rep_tx_queue_setup_op(struct rte_eth_dev *eth_dev,
 				  __rte_unused uint16_t queue_idx,
 				  __rte_unused uint16_t nb_desc,
 				  __rte_unused unsigned int socket_id,
 				  __rte_unused const struct rte_eth_txconf *
 				  tx_conf);
-void bnxt_vf_rep_rx_queue_release_op(void *rx_queue);
-void bnxt_vf_rep_tx_queue_release_op(void *tx_queue);
-void bnxt_vf_rep_dev_stop_op(struct rte_eth_dev *eth_dev);
-void bnxt_vf_rep_dev_close_op(struct rte_eth_dev *eth_dev);
-int bnxt_vf_rep_stats_get_op(struct rte_eth_dev *eth_dev,
+void bnxt_rep_rx_queue_release_op(void *rx_queue);
+void bnxt_rep_tx_queue_release_op(void *tx_queue);
+void bnxt_rep_dev_stop_op(struct rte_eth_dev *eth_dev);
+void bnxt_rep_dev_close_op(struct rte_eth_dev *eth_dev);
+int bnxt_rep_stats_get_op(struct rte_eth_dev *eth_dev,
 			     struct rte_eth_stats *stats);
-int bnxt_vf_rep_stats_reset_op(struct rte_eth_dev *eth_dev);
-void bnxt_vf_rep_stop_all(struct bnxt *bp);
+int bnxt_rep_stats_reset_op(struct rte_eth_dev *eth_dev);
+void bnxt_rep_stop_all(struct bnxt *bp);
 #endif /* _BNXT_REPS_H_ */
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 7cb93b7..6ac49ee 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -42895,4 +42895,252 @@ struct hwrm_cfa_counter_qstats_output {
 	uint8_t	valid;
 } __rte_packed;
 
+/***********************
+ * hwrm_cfa_pair_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_pair_alloc_input (size:576b/72B) */
+struct hwrm_cfa_pair_alloc_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/*
+	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
+	 *            5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
+	 */
+	uint16_t	pair_mode;
+	/* Pair between VF on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
+		UINT32_C(0x0)
+	/* Pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
+		UINT32_C(0x1)
+	/* Pair between REP on local host with REP on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
+		UINT32_C(0x2)
+	/* Pair for the proxy interface. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
+		UINT32_C(0x3)
+	/* Pair for the PF interface. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
+		UINT32_C(0x4)
+	/* Modify existing rep2fn pair and move pair to new PF. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
+		UINT32_C(0x5)
+	/* Modify exsiting rep2fn pairs paired with same PF and move pairs to new PF. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
+		UINT32_C(0x6)
+	/* Truflow pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
+		UINT32_C(0x7)
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
+		HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_a_id;
+	/* Logical Host (0xff-local host). */
+	uint8_t	host_b_id;
+	/* Logical PF (0xff-PF for command channel). */
+	uint8_t	pf_b_id;
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_b_id;
+	/* Loopback port (0xff-internal loopback), valid for mode-3. */
+	uint8_t	port_id;
+	/* Priority used for encap of loopback packets valid for mode-3. */
+	uint8_t	pri;
+	/* New PF for rep2fn modify, valid for mode 5. */
+	uint16_t	new_pf_fid;
+	uint32_t	enables;
+	/*
+	 * This bit must be '1' for the q_ab field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID      UINT32_C(0x1)
+	/*
+	 * This bit must be '1' for the q_ba field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID      UINT32_C(0x2)
+	/*
+	 * This bit must be '1' for the fc_ab field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID     UINT32_C(0x4)
+	/*
+	 * This bit must be '1' for the fc_ba field to be
+	 * configured.
+	 */
+	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID     UINT32_C(0x8)
+	/* VF Pair name (32 byte string). */
+	char	pair_name[32];
+	/*
+	 * The q_ab value specifies the logical index of the TX/RX CoS
+	 * queue to be assigned for traffic in the A to B direction of
+	 * the interface pair. The default value is 0.
+	 */
+	uint8_t	q_ab;
+	/*
+	 * The q_ba value specifies the logical index of the TX/RX CoS
+	 * queue to be assigned for traffic in the B to A direction of
+	 * the interface pair. The default value is 1.
+	 */
+	uint8_t	q_ba;
+	/*
+	 * Specifies whether RX ring flow control is disabled (0) or enabled
+	 * (1) in the A to B direction. The default value is 0, meaning that
+	 * packets will be dropped when the B-side RX rings are full.
+	 */
+	uint8_t	fc_ab;
+	/*
+	 * Specifies whether RX ring flow control is disabled (0) or enabled
+	 * (1) in the B to A direction. The default value is 1, meaning that
+	 * the RX CoS queue will be flow controlled when the A-side RX rings
+	 * are full.
+	 */
+	uint8_t	fc_ba;
+	uint8_t	unused_1[4];
+} __rte_packed;
+
+/* hwrm_cfa_pair_alloc_output (size:192b/24B) */
+struct hwrm_cfa_pair_alloc_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	/* Only valid for modes 1 and 2. */
+	uint16_t	rx_cfa_code_a;
+	/* Only valid for modes 1 and 2. */
+	uint16_t	tx_cfa_action_a;
+	/* Only valid for mode 2. */
+	uint16_t	rx_cfa_code_b;
+	/* Only valid for mode 2. */
+	uint16_t	tx_cfa_action_b;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
+/**********************
+ * hwrm_cfa_pair_free *
+ **********************/
+
+
+/* hwrm_cfa_pair_free_input (size:448b/56B) */
+struct hwrm_cfa_pair_free_input {
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/*
+	 * The completion ring to send the completion event on. This should
+	 * be the NQ ID returned from the `nq_alloc` HWRM command.
+	 */
+	uint16_t	cmpl_ring;
+	/*
+	 * The sequence ID is used by the driver for tracking multiple
+	 * commands. This ID is treated as opaque data by the firmware and
+	 * the value is returned in the `hwrm_resp_hdr` upon completion.
+	 */
+	uint16_t	seq_id;
+	/*
+	 * The target ID of the command:
+	 * * 0x0-0xFFF8 - The function ID
+	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+	 * * 0xFFFD - Reserved for user-space HWRM interface
+	 * * 0xFFFF - HWRM
+	 */
+	uint16_t	target_id;
+	/*
+	 * A physical address pointer pointing to a host buffer that the
+	 * command's response data will be written. This can be either a host
+	 * physical address (HPA) or a guest physical address (GPA) and must
+	 * point to a physically contiguous block of memory.
+	 */
+	uint64_t	resp_addr;
+	/* VF Pair name (32 byte string). */
+	char	pair_name[32];
+	/* Logical PF (0xff-PF for command channel). */
+	uint8_t	pf_b_id;
+	uint8_t	unused_0[3];
+	/* Logical VF number (range: 0 -> MAX_VFS -1). */
+	uint16_t	vf_id;
+	/*
+	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
+	 *            5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
+	 */
+	uint16_t	pair_mode;
+	/* Pair between VF on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN          UINT32_C(0x0)
+	/* Pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN         UINT32_C(0x1)
+	/* Pair between REP on local host with REP on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP        UINT32_C(0x2)
+	/* Pair for the proxy interface. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY          UINT32_C(0x3)
+	/* Pair for the PF interface. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR         UINT32_C(0x4)
+	/* Modify existing rep2fn pair and move pair to new PF. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD     UINT32_C(0x5)
+	/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL  UINT32_C(0x6)
+	/* Truflow pair between REP on local host with PF or VF on specified host. */
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
+	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
+		HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
+} __rte_packed;
+
+/* hwrm_cfa_pair_free_output (size:128b/16B) */
+struct hwrm_cfa_pair_free_output {
+	/* The specific error status for the command. */
+	uint16_t	error_code;
+	/* The HWRM command request type. */
+	uint16_t	req_type;
+	/* The sequence ID from the original command. */
+	uint16_t	seq_id;
+	/* The length of the response data in number of bytes. */
+	uint16_t	resp_len;
+	uint8_t	unused_0[7];
+	/*
+	 * This field is used in Output records to indicate that the output
+	 * is completely written to RAM. This field should be read as '1'
+	 * to indicate that the output has been completely written.
+	 * When writing a command completion or response to an internal processor,
+	 * the order of writes has to be such that this field is written last.
+	 */
+	uint8_t	valid;
+} __rte_packed;
+
 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index e8927f6..762fc0c 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -648,7 +648,7 @@ bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global)
 	struct bnxt_ulp_vfr_rule_info *info;
 	uint8_t port_id;
 	struct rte_eth_dev *vfr_eth_dev;
-	struct bnxt_vf_representor *vfr_bp;
+	struct bnxt_representor *vfr_bp;
 
 	if (!BNXT_TRUFLOW_EN(bp) || BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev))
 		return;
@@ -1139,7 +1139,7 @@ bnxt_ulp_eth_dev_ptr2_cntxt_get(struct rte_eth_dev	*dev)
 	struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 
 	if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
-		struct bnxt_vf_representor *vfr = dev->data->dev_private;
+		struct bnxt_representor *vfr = dev->data->dev_private;
 
 		bp = vfr->parent_dev->data->dev_private;
 	}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index 2d0c3bc..f421e2e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -536,7 +536,7 @@ int32_t
 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
 {
 	struct bnxt_ulp_vfr_rule_info *info;
-	struct bnxt_vf_representor *vfr = vfr_ethdev->data->dev_private;
+	struct bnxt_representor *vfr = vfr_ethdev->data->dev_private;
 	struct rte_eth_dev *parent_dev = vfr->parent_dev;
 	struct bnxt *bp = parent_dev->data->dev_private;
 	uint16_t vfr_port_id = vfr_ethdev->data->port_id;
@@ -596,7 +596,7 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
 }
 
 int32_t
-bnxt_ulp_delete_vfr_default_rules(struct bnxt_vf_representor *vfr)
+bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr)
 {
 	struct bnxt_ulp_vfr_rule_info *info;
 	struct rte_eth_dev *parent_dev = vfr->parent_dev;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 7/8] net/bnxt: fix flow match to ignore pkt type
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
                   ` (5 preceding siblings ...)
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 6/8] net/bnxt: support for representors on remote host domain Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 8/8] net/bnxt: fix seg fault during NAT configuration Somnath Kotur
  2020-09-23 23:50 ` [dpdk-dev] [PATCH 0/8] bnxt patches Ajit Khaparde
  8 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Kishore Padmanabha, Michael Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The pkt_type field in the profile tcam table needs to be ignored
and should not be set to normal packet type. The pkt_type for the packets
that are segmented due to transmit segment offload feature in the
driver are not marked as normal pkt_type and this shall result in
profile tcam table miss and flow not being offloaded hence resulting in
the reduction of the throughput.

Fixes: fe82f3e02701 ("net/bnxt: support exact match templates")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 316 +++++++++++++++---------
 1 file changed, 203 insertions(+), 113 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index 7f9ba96..3ca2801 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -4283,7 +4283,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.key_start_idx = 124,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 298,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4297,7 +4297,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 166,
+	.key_start_idx = 167,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -4316,7 +4316,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
-	.key_start_idx = 177,
+	.key_start_idx = 178,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4335,7 +4335,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 190,
+	.key_start_idx = 191,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4352,10 +4352,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 193,
+	.key_start_idx = 194,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 329,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4369,7 +4369,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 235,
+	.key_start_idx = 237,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -4388,7 +4388,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 246,
+	.key_start_idx = 248,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -4405,7 +4405,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 247,
+	.key_start_idx = 249,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4424,7 +4424,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 260,
+	.key_start_idx = 262,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4441,10 +4441,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 263,
+	.key_start_idx = 265,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 361,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4458,7 +4458,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 305,
+	.key_start_idx = 308,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -4477,7 +4477,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 316,
+	.key_start_idx = 319,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -4494,7 +4494,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 317,
+	.key_start_idx = 320,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4513,7 +4513,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 330,
+	.key_start_idx = 333,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4530,10 +4530,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 333,
+	.key_start_idx = 336,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 393,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4547,7 +4547,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 375,
+	.key_start_idx = 379,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -4566,7 +4566,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 386,
+	.key_start_idx = 390,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -4583,7 +4583,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 387,
+	.key_start_idx = 391,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4602,7 +4602,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 400,
+	.key_start_idx = 404,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4619,10 +4619,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 403,
+	.key_start_idx = 407,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 425,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4636,7 +4636,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 445,
+	.key_start_idx = 450,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
@@ -4655,7 +4655,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 456,
+	.key_start_idx = 461,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -4672,7 +4672,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 457,
+	.key_start_idx = 462,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4691,7 +4691,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 470,
+	.key_start_idx = 475,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4708,10 +4708,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 473,
+	.key_start_idx = 478,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 457,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4725,7 +4725,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 515,
+	.key_start_idx = 521,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
@@ -4744,7 +4744,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
-	.key_start_idx = 526,
+	.key_start_idx = 532,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4763,7 +4763,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 539,
+	.key_start_idx = 545,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4780,10 +4780,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 542,
+	.key_start_idx = 548,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 488,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4797,7 +4797,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 584,
+	.key_start_idx = 591,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -4816,7 +4816,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
-	.key_start_idx = 595,
+	.key_start_idx = 602,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4835,7 +4835,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 608,
+	.key_start_idx = 615,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4852,10 +4852,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 611,
+	.key_start_idx = 618,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 519,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4869,7 +4869,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 653,
+	.key_start_idx = 661,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -4888,7 +4888,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
-	.key_start_idx = 664,
+	.key_start_idx = 672,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4907,7 +4907,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 677,
+	.key_start_idx = 685,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4924,10 +4924,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 680,
+	.key_start_idx = 688,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 550,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -4941,7 +4941,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 722,
+	.key_start_idx = 731,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
@@ -4960,7 +4960,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
-	.key_start_idx = 733,
+	.key_start_idx = 742,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -4979,7 +4979,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 746,
+	.key_start_idx = 755,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -4996,10 +4996,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 749,
+	.key_start_idx = 758,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 581,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5013,7 +5013,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 791,
+	.key_start_idx = 801,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
@@ -5032,7 +5032,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
-	.key_start_idx = 802,
+	.key_start_idx = 812,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5051,7 +5051,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 815,
+	.key_start_idx = 825,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5068,10 +5068,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 818,
+	.key_start_idx = 828,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 612,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5085,7 +5085,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 860,
+	.key_start_idx = 871,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -5104,7 +5104,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
-	.key_start_idx = 871,
+	.key_start_idx = 882,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5123,7 +5123,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 884,
+	.key_start_idx = 895,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5140,10 +5140,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_RX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 887,
+	.key_start_idx = 898,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 643,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5157,7 +5157,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_RX,
-	.key_start_idx = 929,
+	.key_start_idx = 941,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
@@ -5176,7 +5176,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 940,
+	.key_start_idx = 952,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -5193,7 +5193,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 941,
+	.key_start_idx = 953,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5212,7 +5212,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 954,
+	.key_start_idx = 966,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5229,10 +5229,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 957,
+	.key_start_idx = 969,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 675,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5246,7 +5246,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 999,
+	.key_start_idx = 1012,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -5265,7 +5265,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1010,
+	.key_start_idx = 1023,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -5282,7 +5282,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1011,
+	.key_start_idx = 1024,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5301,7 +5301,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1024,
+	.key_start_idx = 1037,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5318,10 +5318,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1027,
+	.key_start_idx = 1040,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 707,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5335,7 +5335,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1069,
+	.key_start_idx = 1083,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
@@ -5354,7 +5354,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1080,
+	.key_start_idx = 1094,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -5371,7 +5371,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1081,
+	.key_start_idx = 1095,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5390,7 +5390,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1094,
+	.key_start_idx = 1108,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5407,10 +5407,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1097,
+	.key_start_idx = 1111,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 739,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5424,7 +5424,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1139,
+	.key_start_idx = 1154,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
@@ -5443,7 +5443,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1150,
+	.key_start_idx = 1165,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
@@ -5460,7 +5460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1151,
+	.key_start_idx = 1166,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5479,7 +5479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1164,
+	.key_start_idx = 1179,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5496,10 +5496,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1167,
+	.key_start_idx = 1182,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 771,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5513,7 +5513,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1209,
+	.key_start_idx = 1225,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
@@ -5532,7 +5532,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1220,
+	.key_start_idx = 1236,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5551,7 +5551,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1233,
+	.key_start_idx = 1249,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5568,10 +5568,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1236,
+	.key_start_idx = 1252,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 802,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5585,7 +5585,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1278,
+	.key_start_idx = 1295,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
@@ -5604,7 +5604,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1285,
+	.key_start_idx = 1302,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -5623,7 +5623,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1298,
+	.key_start_idx = 1315,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
@@ -5640,10 +5640,10 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.direction = TF_DIR_TX,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1301,
+	.key_start_idx = 1318,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
-	.key_num_fields = 42,
+	.key_num_fields = 43,
 	.result_start_idx = 833,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
@@ -5657,7 +5657,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1343,
+	.key_start_idx = 1361,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
@@ -6728,7 +6728,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -7190,7 +7195,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -7643,7 +7653,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -8111,7 +8126,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -8587,7 +8607,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -9059,7 +9084,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -9550,7 +9580,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -10037,7 +10072,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -10532,7 +10572,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -11023,7 +11068,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -11511,7 +11561,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -11988,7 +12043,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -12441,7 +12501,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -12905,7 +12970,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -13377,7 +13447,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -13845,7 +13920,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -14330,7 +14410,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
@@ -14780,7 +14865,12 @@ struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH 8/8] net/bnxt: fix seg fault during NAT configuration
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
                   ` (6 preceding siblings ...)
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 7/8] net/bnxt: fix flow match to ignore pkt type Somnath Kotur
@ 2020-09-22  7:06 ` Somnath Kotur
  2020-09-23 23:50 ` [dpdk-dev] [PATCH 0/8] bnxt patches Ajit Khaparde
  8 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-22  7:06 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Kishore Padmanabha, Michael Baucom, Ajit Kumar Khaparde

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Initialize the global parms structure to avoid seg fault
in the truflow global configuration set api.

Fixes: 0a58be6f7c1e ("net/bnxt: add access to NAT global register")

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 762fc0c..93a7959 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -594,7 +594,7 @@ bnxt_ulp_global_cfg_update(struct bnxt *bp,
 {
 	uint32_t global_cfg = 0;
 	int rc;
-	struct tf_global_cfg_parms parms;
+	struct tf_global_cfg_parms parms = { 0 };
 
 	/* Initialize the params */
 	parms.dir = dir,
-- 
2.7.4


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 0/8] bnxt patches
  2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
                   ` (7 preceding siblings ...)
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 8/8] net/bnxt: fix seg fault during NAT configuration Somnath Kotur
@ 2020-09-23 23:50 ` Ajit Khaparde
  8 siblings, 0 replies; 17+ messages in thread
From: Ajit Khaparde @ 2020-09-23 23:50 UTC (permalink / raw)
  To: Somnath Kotur; +Cc: dpdk-dev, Ferruh Yigit

On Tue, Sep 22, 2020 at 12:13 AM Somnath Kotur
<somnath.kotur@broadcom.com> wrote:
>
> Fixes and enchancements in the bnxt PMD, mostly
> in the TRUFLOW layer

Patchset applied to dpdk-next-net-brcm.

>
> Kishore Padmanabha (3):
>   net/bnxt: add support for decap action for ipv6 VXLAN flows
>   net/bnxt: fix flow match to ignore pkt type
>   net/bnxt: fix seg fault during NAT configuration
>
> Somnath Kotur (5):
>   net/bnxt: simplify representor Rx ring creation
>   net/bnxt: fix to correct bad shift operation
>   net/bnxt: fix to honor value passed for truflow devargs
>   net/bnxt: add a null ptr check in bnxt PCI probe
>   net/bnxt: support for representors on remote host domain
>
>  drivers/net/bnxt/bnxt.h                         |   21 +-
>  drivers/net/bnxt/bnxt_cpr.c                     |    4 +-
>  drivers/net/bnxt/bnxt_ethdev.c                  |  361 +++++-
>  drivers/net/bnxt/bnxt_hwrm.c                    |   97 +-
>  drivers/net/bnxt/bnxt_hwrm.h                    |    4 +
>  drivers/net/bnxt/bnxt_reps.c                    |  223 ++--
>  drivers/net/bnxt/bnxt_reps.h                    |   30 +-
>  drivers/net/bnxt/hsi_struct_def_dpdk.h          |  248 ++++
>  drivers/net/bnxt/tf_ulp/bnxt_ulp.c              |    6 +-
>  drivers/net/bnxt/tf_ulp/ulp_def_rules.c         |    4 +-
>  drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 1512 +++++++++++++++--------
>  drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h  |   40 +-
>  drivers/net/bnxt/tf_ulp/ulp_template_db_field.h |  118 +-
>  13 files changed, 1924 insertions(+), 744 deletions(-)
>
> --
> 2.7.4
>

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe Somnath Kotur
@ 2020-09-24 14:47   ` Ferruh Yigit
  2020-09-25  2:04     ` Somnath Kotur
  2020-09-25 10:40   ` [dpdk-dev] [PATCH v2] net/bnxt: add a " Somnath Kotur
  1 sibling, 1 reply; 17+ messages in thread
From: Ferruh Yigit @ 2020-09-24 14:47 UTC (permalink / raw)
  To: Somnath Kotur, dev; +Cc: Venkat Duvvuru

On 9/22/2020 8:06 AM, Somnath Kotur wrote:
> Check for devargs before invoking rep port probe.
> 
> Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
> 
> Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
> Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> ---
>   drivers/net/bnxt/bnxt_ethdev.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> index db2f0dd..84eba0b 100644
> --- a/drivers/net/bnxt/bnxt_ethdev.c
> +++ b/drivers/net/bnxt/bnxt_ethdev.c
> @@ -6147,6 +6147,10 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
>   	}
>   	PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
>   		    backing_eth_dev->data->port_id);
> +
> +	if (!pci_dev->device.devargs)
> +		return ret;
> +

There is already a null check at the beginning of the function because 
of the same thing (port representors), should they be combined?

And devargs being not NULL does not really mean it has arguments related 
to the port representors, it may have other device devargs. Perhaps 
'eth_da' can  be used to check?

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe
  2020-09-24 14:47   ` Ferruh Yigit
@ 2020-09-25  2:04     ` Somnath Kotur
  2020-09-25  8:42       ` Ferruh Yigit
  0 siblings, 1 reply; 17+ messages in thread
From: Somnath Kotur @ 2020-09-25  2:04 UTC (permalink / raw)
  To: Ferruh Yigit; +Cc: dev, Venkat Duvvuru

On Thu, Sep 24, 2020 at 8:17 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/22/2020 8:06 AM, Somnath Kotur wrote:
> > Check for devargs before invoking rep port probe.
> >
> > Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
> >
> > Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
> > Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> > ---
> >   drivers/net/bnxt/bnxt_ethdev.c | 4 ++++
> >   1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> > index db2f0dd..84eba0b 100644
> > --- a/drivers/net/bnxt/bnxt_ethdev.c
> > +++ b/drivers/net/bnxt/bnxt_ethdev.c
> > @@ -6147,6 +6147,10 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
> >       }
> >       PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
> >                   backing_eth_dev->data->port_id);
> > +
> > +     if (!pci_dev->device.devargs)
> > +             return ret;
> > +
>
> There is already a null check at the beginning of the function because
> of the same thing (port representors), should they be combined?
>
No, this is to catch the corner case if/when 'backing_eth_dev' is
already allocated , so code would unconditionally call
bnxt_rep_port_probe()
irrespective of devargs being there or not, the check at this point
helps prevent that
> And devargs being not NULL does not really mean it has arguments related
> to the port representors, it may have other device devargs. Perhaps
> 'eth_da' can  be used to check?
eth_da is a local var in this function, so perhaps 'num_rep' i.e
invoke bnxt_rep_port_probe only if num_rep > 0 ?
Please let me know if you want me to do a respin of this patch alone
or will you be doing this minor change while merging it in?

Thanks
Som

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe
  2020-09-25  2:04     ` Somnath Kotur
@ 2020-09-25  8:42       ` Ferruh Yigit
  2020-09-25 10:46         ` Somnath Kotur
  0 siblings, 1 reply; 17+ messages in thread
From: Ferruh Yigit @ 2020-09-25  8:42 UTC (permalink / raw)
  To: Somnath Kotur; +Cc: dev, Venkat Duvvuru

On 9/25/2020 3:04 AM, Somnath Kotur wrote:
> On Thu, Sep 24, 2020 at 8:17 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>>
>> On 9/22/2020 8:06 AM, Somnath Kotur wrote:
>>> Check for devargs before invoking rep port probe.
>>>
>>> Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
>>>
>>> Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
>>> Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
>>> ---
>>>    drivers/net/bnxt/bnxt_ethdev.c | 4 ++++
>>>    1 file changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
>>> index db2f0dd..84eba0b 100644
>>> --- a/drivers/net/bnxt/bnxt_ethdev.c
>>> +++ b/drivers/net/bnxt/bnxt_ethdev.c
>>> @@ -6147,6 +6147,10 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
>>>        }
>>>        PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
>>>                    backing_eth_dev->data->port_id);
>>> +
>>> +     if (!pci_dev->device.devargs)
>>> +             return ret;
>>> +
>>
>> There is already a null check at the beginning of the function because
>> of the same thing (port representors), should they be combined?
>>
> No, this is to catch the corner case if/when 'backing_eth_dev' is
> already allocated , so code would unconditionally call
> bnxt_rep_port_probe()
> irrespective of devargs being there or not, the check at this point
> helps prevent that
>> And devargs being not NULL does not really mean it has arguments related
>> to the port representors, it may have other device devargs. Perhaps
>> 'eth_da' can  be used to check?
> eth_da is a local var in this function, so perhaps 'num_rep' i.e
> invoke bnxt_rep_port_probe only if num_rep > 0 ?

+1

> Please let me know if you want me to do a respin of this patch alone
> or will you be doing this minor change while merging it in?

Please send a new version of this patch alone. Thanks.

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH v2] net/bnxt: add a check in bnxt PCI probe
  2020-09-22  7:06 ` [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe Somnath Kotur
  2020-09-24 14:47   ` Ferruh Yigit
@ 2020-09-25 10:40   ` Somnath Kotur
  2020-09-25 11:56     ` Ferruh Yigit
  1 sibling, 1 reply; 17+ messages in thread
From: Somnath Kotur @ 2020-09-25 10:40 UTC (permalink / raw)
  To: dev; +Cc: ferruh.yigit, Somnath Kotur, Venkat Duvvuru

Check for num_rep before invoking rep port probe.

Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
---
v2: Check against num_rep instead of devargs ptr
 drivers/net/bnxt/bnxt_ethdev.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index db2f0dde4..ab25dd1b1 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -6147,6 +6147,10 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 	}
 	PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
 		    backing_eth_dev->data->port_id);
+
+	if (!num_rep)
+		return ret;
+
 	/* probe representor ports now */
 	ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
 
-- 
2.28.0.497.g54e85e7


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe
  2020-09-25  8:42       ` Ferruh Yigit
@ 2020-09-25 10:46         ` Somnath Kotur
  2020-09-25 10:49           ` Somnath Kotur
  0 siblings, 1 reply; 17+ messages in thread
From: Somnath Kotur @ 2020-09-25 10:46 UTC (permalink / raw)
  To: Ferruh Yigit; +Cc: dev, Venkat Duvvuru

On Fri, Sep 25, 2020 at 2:12 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 9/25/2020 3:04 AM, Somnath Kotur wrote:
> > On Thu, Sep 24, 2020 at 8:17 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
> >>
> >> On 9/22/2020 8:06 AM, Somnath Kotur wrote:
> >>> Check for devargs before invoking rep port probe.
> >>>
> >>> Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
> >>>
> >>> Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
> >>> Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> >>> ---
> >>>    drivers/net/bnxt/bnxt_ethdev.c | 4 ++++
> >>>    1 file changed, 4 insertions(+)
> >>>
> >>> diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> >>> index db2f0dd..84eba0b 100644
> >>> --- a/drivers/net/bnxt/bnxt_ethdev.c
> >>> +++ b/drivers/net/bnxt/bnxt_ethdev.c
> >>> @@ -6147,6 +6147,10 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
> >>>        }
> >>>        PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
> >>>                    backing_eth_dev->data->port_id);
> >>> +
> >>> +     if (!pci_dev->device.devargs)
> >>> +             return ret;
> >>> +
> >>
> >> There is already a null check at the beginning of the function because
> >> of the same thing (port representors), should they be combined?
> >>
> > No, this is to catch the corner case if/when 'backing_eth_dev' is
> > already allocated , so code would unconditionally call
> > bnxt_rep_port_probe()
> > irrespective of devargs being there or not, the check at this point
> > helps prevent that
> >> And devargs being not NULL does not really mean it has arguments related
> >> to the port representors, it may have other device devargs. Perhaps
> >> 'eth_da' can  be used to check?
> > eth_da is a local var in this function, so perhaps 'num_rep' i.e
> > invoke bnxt_rep_port_probe only if num_rep > 0 ?
>
> +1
>
> > Please let me know if you want me to do a respin of this patch alone
> > or will you be doing this minor change while merging it in?
>
> Please send a new version of this patch alone. Thanks.
Thanks Ferruh, Done

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe
  2020-09-25 10:46         ` Somnath Kotur
@ 2020-09-25 10:49           ` Somnath Kotur
  0 siblings, 0 replies; 17+ messages in thread
From: Somnath Kotur @ 2020-09-25 10:49 UTC (permalink / raw)
  To: Ferruh Yigit; +Cc: dev, Venkat Duvvuru

On Fri, Sep 25, 2020 at 4:16 PM Somnath Kotur
<somnath.kotur@broadcom.com> wrote:
>
> On Fri, Sep 25, 2020 at 2:12 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
> >
> > On 9/25/2020 3:04 AM, Somnath Kotur wrote:
> > > On Thu, Sep 24, 2020 at 8:17 PM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
> > >>
> > >> On 9/22/2020 8:06 AM, Somnath Kotur wrote:
> > >>> Check for devargs before invoking rep port probe.
> > >>>
> > >>> Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
> > >>>
> > >>> Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
> > >>> Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
> > >>> ---
> > >>>    drivers/net/bnxt/bnxt_ethdev.c | 4 ++++
> > >>>    1 file changed, 4 insertions(+)
> > >>>
> > >>> diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> > >>> index db2f0dd..84eba0b 100644
> > >>> --- a/drivers/net/bnxt/bnxt_ethdev.c
> > >>> +++ b/drivers/net/bnxt/bnxt_ethdev.c
> > >>> @@ -6147,6 +6147,10 @@ static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
> > >>>        }
> > >>>        PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
> > >>>                    backing_eth_dev->data->port_id);
> > >>> +
> > >>> +     if (!pci_dev->device.devargs)
> > >>> +             return ret;
> > >>> +
> > >>
> > >> There is already a null check at the beginning of the function because
> > >> of the same thing (port representors), should they be combined?
> > >>
> > > No, this is to catch the corner case if/when 'backing_eth_dev' is
> > > already allocated , so code would unconditionally call
> > > bnxt_rep_port_probe()
> > > irrespective of devargs being there or not, the check at this point
> > > helps prevent that
> > >> And devargs being not NULL does not really mean it has arguments related
> > >> to the port representors, it may have other device devargs. Perhaps
> > >> 'eth_da' can  be used to check?
> > > eth_da is a local var in this function, so perhaps 'num_rep' i.e
> > > invoke bnxt_rep_port_probe only if num_rep > 0 ?
> >
> > +1
> >
> > > Please let me know if you want me to do a respin of this patch alone
> > > or will you be doing this minor change while merging it in?
> >
> > Please send a new version of this patch alone. Thanks.
> Thanks Ferruh, Done
Sorry Ferruh, the first one i sent did not have the in-reply-to,
re-sent it with the correct in-reply-to format again, so please pick
that up
Thanks a lot

-Som

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH v2] net/bnxt: add a check in bnxt PCI probe
  2020-09-25 10:40   ` [dpdk-dev] [PATCH v2] net/bnxt: add a " Somnath Kotur
@ 2020-09-25 11:56     ` Ferruh Yigit
  0 siblings, 0 replies; 17+ messages in thread
From: Ferruh Yigit @ 2020-09-25 11:56 UTC (permalink / raw)
  To: Somnath Kotur, dev; +Cc: Venkat Duvvuru

On 9/25/2020 11:40 AM, Somnath Kotur wrote:
> Check for num_rep before invoking rep port probe.
> 
> Fixes: 6dc83230b43b ("net/bnxt: support port representor data path")
> 
> Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
> Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>

Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

Applied to dpdk-next-net/main, thanks.

^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2020-09-25 11:56 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-22  7:06 [dpdk-dev] [PATCH 0/8] bnxt patches Somnath Kotur
2020-09-22  7:06 ` [dpdk-dev] [PATCH 1/8] net/bnxt: add support for decap action for ipv6 VXLAN flows Somnath Kotur
2020-09-22  7:06 ` [dpdk-dev] [PATCH 2/8] net/bnxt: simplify representor Rx ring creation Somnath Kotur
2020-09-22  7:06 ` [dpdk-dev] [PATCH 3/8] net/bnxt: fix to correct bad shift operation Somnath Kotur
2020-09-22  7:06 ` [dpdk-dev] [PATCH 4/8] net/bnxt: fix to honor value passed for truflow devargs Somnath Kotur
2020-09-22  7:06 ` [dpdk-dev] [PATCH 5/8] net/bnxt: add a null ptr check in bnxt PCI probe Somnath Kotur
2020-09-24 14:47   ` Ferruh Yigit
2020-09-25  2:04     ` Somnath Kotur
2020-09-25  8:42       ` Ferruh Yigit
2020-09-25 10:46         ` Somnath Kotur
2020-09-25 10:49           ` Somnath Kotur
2020-09-25 10:40   ` [dpdk-dev] [PATCH v2] net/bnxt: add a " Somnath Kotur
2020-09-25 11:56     ` Ferruh Yigit
2020-09-22  7:06 ` [dpdk-dev] [PATCH 6/8] net/bnxt: support for representors on remote host domain Somnath Kotur
2020-09-22  7:06 ` [dpdk-dev] [PATCH 7/8] net/bnxt: fix flow match to ignore pkt type Somnath Kotur
2020-09-22  7:06 ` [dpdk-dev] [PATCH 8/8] net/bnxt: fix seg fault during NAT configuration Somnath Kotur
2020-09-23 23:50 ` [dpdk-dev] [PATCH 0/8] bnxt patches Ajit Khaparde

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