From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2678EA04B1; Wed, 23 Sep 2020 16:24:10 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BFB841DB92; Wed, 23 Sep 2020 16:23:50 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id D39861DCA5 for ; Wed, 23 Sep 2020 16:23:47 +0200 (CEST) IronPort-SDR: 5JgJLfDqj6/wGZDM8WRzZozsftuwV/Z9Sg0bIlciSHz3NjPa9Uu0fUcFkfSVSDjX++Mqrk2p0M Tj+nuwPREsgQ== X-IronPort-AV: E=McAfee;i="6000,8403,9752"; a="245732155" X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="245732155" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2020 07:23:47 -0700 IronPort-SDR: cU2dUqksQe19ROxXUBxB0iCW4r2aoOLlWH4+kBm8U3gOV8FKWePbAPg+UgZ7+wSVAowOkjqWIL qkPumpaiEP0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,293,1596524400"; d="scan'208";a="511663518" Received: from silpixa00399477.ir.intel.com ([10.237.214.232]) by fmsmga005.fm.intel.com with ESMTP; 23 Sep 2020 07:23:44 -0700 From: Radu Nicolau To: dev@dpdk.org Cc: beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, jerinjacobk@gmail.com, david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com, ruifeng.wang@arm.com, qiming.yang@intel.com, qi.z.zhang@intel.com, Radu Nicolau Date: Wed, 23 Sep 2020 14:22:51 +0000 Message-Id: <20200923142253.18853-4-radu.nicolau@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200923142253.18853-1-radu.nicolau@intel.com> References: <1591870283-7776-1-git-send-email-radu.nicolau@intel.com> <20200923142253.18853-1-radu.nicolau@intel.com> Subject: [dpdk-dev] [PATCH v12 3/5] common/qat: use WC store to update queue tail registers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Performance improvement: use a write combining store instead of a regular mmio write to update queue tail registers. Signed-off-by: Radu Nicolau Acked-by: Fiona Trahe --- doc/guides/rel_notes/release_20_11.rst | 4 ++++ drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index c0307893e..3d310572c 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -89,6 +89,10 @@ New Features Updated the Intel i40e driver to use write combining stores. +* **Updated Intel qat driver.** + + Updated the Intel qat driver to use write combining stores. + Removed Items ------------- diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h index 1eef5513f..504ffb723 100644 --- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h +++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h @@ -9,6 +9,8 @@ /* CSR write macro */ #define ADF_CSR_WR(csrAddr, csrOffset, val) \ rte_write32(val, (((uint8_t *)csrAddr) + csrOffset)) +#define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \ + rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset)) /* CSR read macro */ #define ADF_CSR_RD(csrAddr, csrOffset) \ @@ -110,10 +112,10 @@ do { \ ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \ } while (0) #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ - ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ + ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ ADF_RING_CSR_RING_HEAD + (ring << 2), value) #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ - ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ + ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ ADF_RING_CSR_RING_TAIL + (ring << 2), value) #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ do { \ -- 2.17.1