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From: Radu Nicolau <radu.nicolau@intel.com>
To: dev@dpdk.org
Cc: beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com,
konstantin.ananyev@intel.com, jerinjacobk@gmail.com,
david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com,
ruifeng.wang@arm.com, qiming.yang@intel.com, qi.z.zhang@intel.com,
Radu Nicolau <radu.nicolau@intel.com>
Date: Wed, 23 Sep 2020 14:22:51 +0000
Message-Id: <20200923142253.18853-4-radu.nicolau@intel.com>
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<20200923142253.18853-1-radu.nicolau@intel.com>
Subject: [dpdk-dev] [PATCH v12 3/5] common/qat: use WC store to update queue
tail registers
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Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
---
doc/guides/rel_notes/release_20_11.rst | 4 ++++
drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index c0307893e..3d310572c 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -89,6 +89,10 @@ New Features
Updated the Intel i40e driver to use write combining stores.
+* **Updated Intel qat driver.**
+
+ Updated the Intel qat driver to use write combining stores.
+
Removed Items
-------------
diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
index 1eef5513f..504ffb723 100644
--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
@@ -9,6 +9,8 @@
/* CSR write macro */
#define ADF_CSR_WR(csrAddr, csrOffset, val) \
rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
+#define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \
+ rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset))
/* CSR read macro */
#define ADF_CSR_RD(csrAddr, csrOffset) \
@@ -110,10 +112,10 @@ do { \
ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
} while (0)
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
- ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+ ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_RING_CSR_RING_HEAD + (ring << 2), value)
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
- ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+ ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_RING_CSR_RING_TAIL + (ring << 2), value)
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
do { \
--
2.17.1