From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8C245A04B5; Wed, 30 Sep 2020 15:13:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 79A801DB91; Wed, 30 Sep 2020 15:08:43 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 6D76C1DB5A for ; Wed, 30 Sep 2020 15:08:27 +0200 (CEST) IronPort-SDR: uaXUrAra+4yR7IEoYf2FA2Typ5KvhhC0rq6ighfMdo+NrhampghoWJvt3EhIEh4SnhxvcedETM DyGReW23TOxw== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223496" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223496" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:26 -0700 IronPort-SDR: pV5ZUDvGaHX51RcUMH6Y8IKTRzHdtfERbAishvFVTpAWySMYVNiQnEBScB7hO95flVKDqghAEB zjaWZWb/xocw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603268" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:24 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Yipeng Wang , Sameh Gobriel Date: Wed, 30 Sep 2020 14:04:11 +0100 Message-Id: <20200930130415.11211-16-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 15/18] member: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Yipeng Wang Cc: Sameh Gobriel Signed-off-by: Ciara Power --- lib/librte_member/rte_member_ht.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/librte_member/rte_member_ht.c b/lib/librte_member/rte_member_ht.c index cbcd0d4407..71e3cf7b52 100644 --- a/lib/librte_member/rte_member_ht.c +++ b/lib/librte_member/rte_member_ht.c @@ -113,7 +113,8 @@ rte_member_create_ht(struct rte_member_setsum *ss, } #if defined(RTE_ARCH_X86) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && - RTE_MEMBER_BUCKET_ENTRIES == 16) + RTE_MEMBER_BUCKET_ENTRIES == 16 && + rte_get_max_simd_bitwidth() >= RTE_MAX_256_SIMD) ss->sig_cmp_fn = RTE_MEMBER_COMPARE_AVX2; else #endif -- 2.17.1