From: Jiawen Wu <jiawenwu@trustnetic.com>
To: dev@dpdk.org
Cc: jiawenwu <jiawenwu@trustnetic.com>
Subject: [dpdk-dev] [PATCH v2 13/56] net/txgbe: add interrupt operation
Date: Mon, 5 Oct 2020 20:08:27 +0800 [thread overview]
Message-ID: <20201005120910.189343-14-jiawenwu@trustnetic.com> (raw)
In-Reply-To: <20201005120910.189343-1-jiawenwu@trustnetic.com>
From: jiawenwu <jiawenwu@trustnetic.com>
Add device interrupt handler and setup misx interrupt.
Signed-off-by: jiawenwu <jiawenwu@trustnetic.com>
---
doc/guides/nics/features/txgbe.ini | 2 +
doc/guides/nics/txgbe.rst | 5 +
drivers/net/txgbe/base/txgbe_type.h | 8 +
drivers/net/txgbe/txgbe_ethdev.c | 466 ++++++++++++++++++++++++++++
drivers/net/txgbe/txgbe_ethdev.h | 30 ++
5 files changed, 511 insertions(+)
diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini
index 2fc202c3a..d7c3bbfb6 100644
--- a/doc/guides/nics/features/txgbe.ini
+++ b/doc/guides/nics/features/txgbe.ini
@@ -5,6 +5,8 @@
;
[Features]
Speed capabilities = Y
+Link status = Y
+Link status event = Y
Linux UIO = Y
Linux VFIO = Y
ARMv8 = Y
diff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst
index e3b9f1858..994ea0583 100644
--- a/doc/guides/nics/txgbe.rst
+++ b/doc/guides/nics/txgbe.rst
@@ -7,6 +7,11 @@ TXGBE Poll Mode Driver
The TXGBE PMD (librte_pmd_txgbe) provides poll mode driver support
for Wangxun 10 Gigabit Ethernet NICs.
+Features
+--------
+
+- Link state information
+
Prerequisites
-------------
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index c0bf7cc23..499603c61 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -382,6 +382,14 @@ struct txgbe_mbx_info {
s32 (*check_for_rst)(struct txgbe_hw *, u16);
};
+enum txgbe_isb_idx {
+ TXGBE_ISB_HEADER,
+ TXGBE_ISB_MISC,
+ TXGBE_ISB_VEC0,
+ TXGBE_ISB_VEC1,
+ TXGBE_ISB_MAX
+};
+
struct txgbe_hw {
void IOMEM *hw_addr;
void *back;
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 7ad1eae2a..ea184316d 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -8,8 +8,12 @@
#include <string.h>
#include <rte_common.h>
#include <rte_ethdev_pci.h>
+
+#include <rte_interrupts.h>
#include <rte_pci.h>
#include <rte_memory.h>
+#include <rte_eal.h>
+#include <rte_alarm.h>
#include "txgbe_logs.h"
#include "base/txgbe.h"
@@ -18,6 +22,17 @@
static void txgbe_dev_close(struct rte_eth_dev *dev);
+static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
+static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
+static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
+static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
+static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
+static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
+ struct rte_intr_handle *handle);
+static void txgbe_dev_interrupt_handler(void *param);
+static void txgbe_dev_interrupt_delayed_handler(void *param);
+static void txgbe_configure_msix(struct rte_eth_dev *dev);
+
/*
* The set of PCI devices this driver supports
*/
@@ -59,6 +74,29 @@ txgbe_is_sfp(struct txgbe_hw *hw)
}
}
+static inline void
+txgbe_enable_intr(struct rte_eth_dev *dev)
+{
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+
+ wr32(hw, TXGBE_IENMISC, intr->mask_misc);
+ wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
+ wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
+ txgbe_flush(hw);
+}
+
+static void
+txgbe_disable_intr(struct txgbe_hw *hw)
+{
+ PMD_INIT_FUNC_TRACE();
+
+ wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
+ wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
+ wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
+ txgbe_flush(hw);
+}
+
static int
eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
{
@@ -144,6 +182,9 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
return -EIO;
}
+ /* disable interrupt */
+ txgbe_disable_intr(hw);
+
/* Allocate memory for storing MAC addresses */
eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
hw->mac.num_rar_entries, 0);
@@ -186,9 +227,15 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
eth_dev->data->port_id, pci_dev->id.vendor_id,
pci_dev->id.device_id);
+ rte_intr_callback_register(intr_handle,
+ txgbe_dev_interrupt_handler, eth_dev);
+
/* enable uio/vfio intr/eventfd mapping */
rte_intr_enable(intr_handle);
+ /* enable support intr */
+ txgbe_enable_intr(eth_dev);
+
return 0;
}
@@ -255,6 +302,20 @@ static struct rte_pci_driver rte_txgbe_pmd = {
.remove = eth_txgbe_pci_remove,
};
+
+static void
+txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
+{
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+ uint32_t gpie;
+
+ gpie = rd32(hw, TXGBE_GPIOINTEN);
+ gpie |= TXGBE_GPIOBIT_6;
+ wr32(hw, TXGBE_GPIOINTEN, gpie);
+ intr->mask_misc |= TXGBE_ICRMISC_GPIO;
+}
+
/*
* Reset and stop device.
*/
@@ -263,6 +324,8 @@ txgbe_dev_close(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ int retries = 0;
+ int ret;
PMD_INIT_FUNC_TRACE();
@@ -271,6 +334,22 @@ txgbe_dev_close(struct rte_eth_dev *dev)
/* disable uio intr before callback unregister */
rte_intr_disable(intr_handle);
+ do {
+ ret = rte_intr_callback_unregister(intr_handle,
+ txgbe_dev_interrupt_handler, dev);
+ if (ret >= 0 || ret == -ENOENT) {
+ break;
+ } else if (ret != -EAGAIN) {
+ PMD_INIT_LOG(ERR,
+ "intr callback unregister failed: %d",
+ ret);
+ }
+ rte_delay_ms(100);
+ } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
+
+ /* cancel the delay handler before remove dev */
+ rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
+
rte_free(dev->data->mac_addrs);
dev->data->mac_addrs = NULL;
@@ -341,6 +420,393 @@ txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
return 0;
}
+static int
+txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(wait_to_complete);
+ return 0;
+}
+
+/**
+ * It clears the interrupt causes and enables the interrupt.
+ * It will be called once only during nic initialized.
+ *
+ * @param dev
+ * Pointer to struct rte_eth_dev.
+ * @param on
+ * Enable or Disable.
+ *
+ * @return
+ * - On success, zero.
+ * - On failure, a negative value.
+ */
+static int
+txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
+{
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+
+ txgbe_dev_link_status_print(dev);
+ if (on)
+ intr->mask_misc |= TXGBE_ICRMISC_LSC;
+ else
+ intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
+
+ return 0;
+}
+
+/**
+ * It clears the interrupt causes and enables the interrupt.
+ * It will be called once only during nic initialized.
+ *
+ * @param dev
+ * Pointer to struct rte_eth_dev.
+ *
+ * @return
+ * - On success, zero.
+ * - On failure, a negative value.
+ */
+static int
+txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
+{
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+
+ intr->mask[0] |= TXGBE_ICR_MASK;
+ intr->mask[1] |= TXGBE_ICR_MASK;
+
+ return 0;
+}
+
+/**
+ * It clears the interrupt causes and enables the interrupt.
+ * It will be called once only during nic initialized.
+ *
+ * @param dev
+ * Pointer to struct rte_eth_dev.
+ *
+ * @return
+ * - On success, zero.
+ * - On failure, a negative value.
+ */
+static int
+txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
+{
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+
+ intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
+
+ return 0;
+}
+
+/*
+ * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
+ *
+ * @param dev
+ * Pointer to struct rte_eth_dev.
+ *
+ * @return
+ * - On success, zero.
+ * - On failure, a negative value.
+ */
+static int
+txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
+{
+ uint32_t eicr;
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+
+ /* clear all cause mask */
+ txgbe_disable_intr(hw);
+
+ /* read-on-clear nic registers here */
+ eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
+ PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
+
+ intr->flags = 0;
+
+ /* set flag for async link update */
+ if (eicr & TXGBE_ICRMISC_LSC)
+ intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
+
+ if (eicr & TXGBE_ICRMISC_VFMBX)
+ intr->flags |= TXGBE_FLAG_MAILBOX;
+
+ if (eicr & TXGBE_ICRMISC_LNKSEC)
+ intr->flags |= TXGBE_FLAG_MACSEC;
+
+ if (eicr & TXGBE_ICRMISC_GPIO)
+ intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
+
+ return 0;
+}
+
+/**
+ * It gets and then prints the link status.
+ *
+ * @param dev
+ * Pointer to struct rte_eth_dev.
+ *
+ * @return
+ * - On success, zero.
+ * - On failure, a negative value.
+ */
+static void
+txgbe_dev_link_status_print(struct rte_eth_dev *dev)
+{
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+ struct rte_eth_link link;
+
+ rte_eth_linkstatus_get(dev, &link);
+
+ if (link.link_status) {
+ PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
+ (int)(dev->data->port_id),
+ (unsigned)link.link_speed,
+ link.link_duplex == ETH_LINK_FULL_DUPLEX ?
+ "full-duplex" : "half-duplex");
+ } else {
+ PMD_INIT_LOG(INFO, " Port %d: Link Down",
+ (int)(dev->data->port_id));
+ }
+ PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
+ pci_dev->addr.domain,
+ pci_dev->addr.bus,
+ pci_dev->addr.devid,
+ pci_dev->addr.function);
+}
+
+/*
+ * It executes link_update after knowing an interrupt occurred.
+ *
+ * @param dev
+ * Pointer to struct rte_eth_dev.
+ *
+ * @return
+ * - On success, zero.
+ * - On failure, a negative value.
+ */
+static int
+txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
+ struct rte_intr_handle *intr_handle)
+{
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+ int64_t timeout;
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+
+ PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
+
+ if (intr->flags & TXGBE_FLAG_MAILBOX) {
+ intr->flags &= ~TXGBE_FLAG_MAILBOX;
+ }
+
+ if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
+ hw->phy.handle_lasi(hw);
+ intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
+ }
+
+ if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
+ struct rte_eth_link link;
+
+ /* get the link status before link update, for predicting later */
+ rte_eth_linkstatus_get(dev, &link);
+
+ txgbe_dev_link_update(dev, 0);
+
+ /* likely to up */
+ if (!link.link_status)
+ /* handle it 1 sec later, wait it being stable */
+ timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
+ /* likely to down */
+ else
+ /* handle it 4 sec later, wait it being stable */
+ timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
+
+ txgbe_dev_link_status_print(dev);
+ if (rte_eal_alarm_set(timeout * 1000,
+ txgbe_dev_interrupt_delayed_handler,
+ (void *)dev) < 0)
+ PMD_DRV_LOG(ERR, "Error setting alarm");
+ else {
+ /* remember original mask */
+ intr->mask_misc_orig = intr->mask_misc;
+ /* only disable lsc interrupt */
+ intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
+ }
+ }
+
+ PMD_DRV_LOG(DEBUG, "enable intr immediately");
+ txgbe_enable_intr(dev);
+ rte_intr_enable(intr_handle);
+
+ return 0;
+}
+
+/**
+ * Interrupt handler which shall be registered for alarm callback for delayed
+ * handling specific interrupt to wait for the stable nic state. As the
+ * NIC interrupt state is not stable for txgbe after link is just down,
+ * it needs to wait 4 seconds to get the stable status.
+ *
+ * @param handle
+ * Pointer to interrupt handle.
+ * @param param
+ * The address of parameter (struct rte_eth_dev *) regsitered before.
+ *
+ * @return
+ * void
+ */
+static void
+txgbe_dev_interrupt_delayed_handler(void *param)
+{
+ struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ uint32_t eicr;
+
+ txgbe_disable_intr(hw);
+
+ eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
+
+ if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
+ hw->phy.handle_lasi(hw);
+ intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
+ }
+
+ if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
+ txgbe_dev_link_update(dev, 0);
+ intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
+ txgbe_dev_link_status_print(dev);
+ _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
+ NULL);
+ }
+
+ if (intr->flags & TXGBE_FLAG_MACSEC) {
+ _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
+ NULL);
+ intr->flags &= ~TXGBE_FLAG_MACSEC;
+ }
+
+ /* restore original mask */
+ intr->mask_misc = intr->mask_misc_orig;
+ intr->mask_misc_orig = 0;
+
+ PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
+ txgbe_enable_intr(dev);
+ rte_intr_enable(intr_handle);
+}
+
+/**
+ * Interrupt handler triggered by NIC for handling
+ * specific interrupt.
+ *
+ * @param handle
+ * Pointer to interrupt handle.
+ * @param param
+ * The address of parameter (struct rte_eth_dev *) regsitered before.
+ *
+ * @return
+ * void
+ */
+static void
+txgbe_dev_interrupt_handler(void *param)
+{
+ struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
+
+ txgbe_dev_interrupt_get_status(dev);
+ txgbe_dev_interrupt_action(dev, dev->intr_handle);
+}
+
+/**
+ * set the IVAR registers, mapping interrupt causes to vectors
+ * @param hw
+ * pointer to txgbe_hw struct
+ * @direction
+ * 0 for Rx, 1 for Tx, -1 for other causes
+ * @queue
+ * queue to map the corresponding interrupt to
+ * @msix_vector
+ * the vector to map to the corresponding queue
+ */
+void
+txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
+ uint8_t queue, uint8_t msix_vector)
+{
+ uint32_t tmp, idx;
+
+ if (direction == -1) {
+ /* other causes */
+ msix_vector |= TXGBE_IVARMISC_VLD;
+ idx = 0;
+ tmp = rd32(hw, TXGBE_IVARMISC);
+ tmp &= ~(0xFF << idx);
+ tmp |= (msix_vector << idx);
+ wr32(hw, TXGBE_IVARMISC, tmp);
+ } else {
+ /* rx or tx causes */
+ /* Workround for ICR lost */
+ idx = ((16 * (queue & 1)) + (8 * direction));
+ tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
+ tmp &= ~(0xFF << idx);
+ tmp |= (msix_vector << idx);
+ wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
+ }
+}
+
+/**
+ * Sets up the hardware to properly generate MSI-X interrupts
+ * @hw
+ * board private structure
+ */
+static void
+txgbe_configure_msix(struct rte_eth_dev *dev)
+{
+ struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
+ struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
+ uint32_t vec = TXGBE_MISC_VEC_ID;
+ uint32_t gpie;
+
+ /* won't configure msix register if no mapping is done
+ * between intr vector and event fd
+ * but if misx has been enabled already, need to configure
+ * auto clean, auto mask and throttling.
+ */
+ gpie = rd32(hw, TXGBE_GPIE);
+ if (!rte_intr_dp_is_en(intr_handle) &&
+ !(gpie & TXGBE_GPIE_MSIX))
+ return;
+
+ if (rte_intr_allow_others(intr_handle))
+ vec = base = TXGBE_RX_VEC_START;
+
+ /* setup GPIE for MSI-x mode */
+ gpie = rd32(hw, TXGBE_GPIE);
+ gpie |= TXGBE_GPIE_MSIX;
+ wr32(hw, TXGBE_GPIE, gpie);
+
+ /* Populate the IVAR table and set the ITR values to the
+ * corresponding register.
+ */
+ if (rte_intr_dp_is_en(intr_handle)) {
+ for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
+ queue_id++) {
+ /* by default, 1:1 mapping */
+ txgbe_set_ivar_map(hw, 0, queue_id, vec);
+ intr_handle->intr_vec[queue_id] = vec;
+ if (vec < base + intr_handle->nb_efd - 1)
+ vec++;
+ }
+
+ txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
+ }
+ wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
+ TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
+ | TXGBE_ITR_WRDSA);
+}
+
static const struct eth_dev_ops txgbe_eth_dev_ops = {
.dev_infos_get = txgbe_dev_info_get,
};
diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h
index c81528295..2c13da38f 100644
--- a/drivers/net/txgbe/txgbe_ethdev.h
+++ b/drivers/net/txgbe/txgbe_ethdev.h
@@ -7,12 +7,21 @@
#include "base/txgbe.h"
+/* need update link, bit flag */
+#define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
+#define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
+#define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
+#define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
+#define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
+
/*
* Defines that were not part of txgbe_type.h as they are not used by the
* FreeBSD driver.
*/
#define TXGBE_HKEY_MAX_INDEX 10
+#define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
+
#define TXGBE_RSS_OFFLOAD_ALL ( \
ETH_RSS_IPV4 | \
ETH_RSS_NONFRAG_IPV4_TCP | \
@@ -24,16 +33,37 @@
ETH_RSS_IPV6_TCP_EX | \
ETH_RSS_IPV6_UDP_EX)
+#define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
+#define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
+
+/* structure for interrupt relative data */
+struct txgbe_interrupt {
+ uint32_t flags;
+ uint32_t mask_misc;
+ /* to save original mask during delayed handler */
+ uint32_t mask_misc_orig;
+ uint32_t mask[2];
+};
+
/*
* Structure to store private data for each driver instance (for each port).
*/
struct txgbe_adapter {
struct txgbe_hw hw;
+ struct txgbe_interrupt intr;
};
#define TXGBE_DEV_HW(dev) \
(&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
+#define TXGBE_DEV_INTR(dev) \
+ (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
+
+void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
+ uint8_t queue, uint8_t msix_vector);
+
+#define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
+#define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
#define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
/*
--
2.18.4
next prev parent reply other threads:[~2020-10-05 12:13 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-05 12:08 [dpdk-dev] [PATCH v2 00/56] net: txgbe PMD Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 01/56] net/txgbe: add build and doc infrastructure Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 02/56] net/txgbe: add ethdev probe and remove Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 03/56] net/txgbe: add device init and uninit Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 04/56] net/txgbe: add error types and registers Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 05/56] net/txgbe: add mac type and bus lan id Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 06/56] net/txgbe: add HW infrastructure and dummy function Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 07/56] net/txgbe: add EEPROM functions Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 08/56] net/txgbe: add HW init and reset operation Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 09/56] net/txgbe: add PHY init Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 10/56] net/txgbe: add module identify Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 11/56] net/txgbe: add PHY reset Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 12/56] net/txgbe: add info get operation Jiawen Wu
2020-10-05 12:08 ` Jiawen Wu [this message]
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 14/56] net/txgbe: add device configure operation Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 15/56] net/txgbe: add link status change Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 16/56] net/txgbe: add multi-speed link setup Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 17/56] net/txgbe: add autoc read and write Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 18/56] net/txgbe: add MAC address operations Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 19/56] net/txgbe: add unicast hash bitmap Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 20/56] net/txgbe: add RX and TX init Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 21/56] net/txgbe: add RX and TX queues setup and release Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 22/56] net/txgbe: add RX and TX start and stop Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 23/56] net/txgbe: add packet type Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 24/56] net/txgbe: fill simple transmit function Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 25/56] net/txgbe: fill transmit function with hardware offload Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 26/56] net/txgbe: fill TX prepare funtion Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 27/56] net/txgbe: fill receive functions Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 28/56] net/txgbe: add device start operation Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 29/56] net/txgbe: add RX and TX data path start and stop Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 30/56] net/txgbe: add device stop and close operations Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 31/56] net/txgbe: support RX interrupt Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 32/56] net/txgbe: add RX and TX queue info get Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 33/56] net/txgbe: add device stats get Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 34/56] net/txgbe: add device xstats get Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 35/56] net/txgbe: add queue stats mapping Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 36/56] net/txgbe: add VLAN handle support Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 37/56] net/txgbe: add SWFW semaphore and lock Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 38/56] net/txgbe: add PF module init and uninit for SRIOV Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 39/56] net/txgbe: add process mailbox operation Jiawen Wu
2020-10-06 11:05 ` Ferruh Yigit
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 40/56] net/txgbe: add PF module configure for SRIOV Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 41/56] net/txgbe: add VMDq configure Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 42/56] net/txgbe: add RSS support Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 43/56] net/txgbe: add DCB support Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 44/56] net/txgbe: add flow control support Jiawen Wu
2020-10-05 12:08 ` [dpdk-dev] [PATCH v2 45/56] net/txgbe: add FC auto negotiation support Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 46/56] net/txgbe: add priority flow control support Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 47/56] net/txgbe: add device promiscuous and allmulticast mode Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 48/56] net/txgbe: add MTU set operation Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 49/56] net/txgbe: add FW version get operation Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 50/56] net/txgbe: add EEPROM info " Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 51/56] net/txgbe: add register dump support Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 52/56] net/txgbe: support device LED on and off Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 53/56] net/txgbe: add mirror rule operations Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 54/56] net/txgbe: add PTP support Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 55/56] net/txgbe: add DCB info get operation Jiawen Wu
2020-10-05 12:09 ` [dpdk-dev] [PATCH v2 56/56] net/txgbe: add Rx and Tx descriptor status Jiawen Wu
2020-10-06 11:02 ` [dpdk-dev] [PATCH v2 00/56] net: txgbe PMD Ferruh Yigit
2020-10-09 3:03 ` jiawenwu
2020-10-09 9:47 ` Ferruh Yigit
2020-10-10 9:45 ` Jiawen Wu
2020-10-12 8:37 ` Ferruh Yigit
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