From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62289A04BC; Thu, 8 Oct 2020 12:35:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 50B951BF19; Thu, 8 Oct 2020 12:35:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 50E871BF19 for ; Thu, 8 Oct 2020 12:35:05 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 098AUJ6R024789; Thu, 8 Oct 2020 03:35:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=eyuD7ftOdMGVdY5yma6IccxyiRu99ke80/+6OYNOIgc=; b=DG2/l9zMbwKwvJ5A8c+ptPOfYdool/AjSVbK83HfG6FOdyO1HIdoSLLzfBQ5YRBSvx3n ql9PYUiEV6TZwEomJNdCmcR9vjnsTWmH6exqARs7JnC182pg7wIDK5Ovz8hjApCc0MaI 69PQlnnp4wjMSwrLYYsJZk75imrzOISHpuOlMl38exGcwwoXVsvvT7bCIFPl3uzO4Mh5 TezUejYmzGbKQD6xIK+kAr231kb1KJJ/DLbFXeclG3glv6s9/sU0M9drk2KlJadutXnH ZQzeSojaEWpsOqEX+5eqVRmfIOLHrsqcu2844p4O7IDAiJ2iiuHFsXUPxj/q9U0/iu5G cQ== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 33xpnq0dua-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 08 Oct 2020 03:35:03 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Oct 2020 03:35:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Oct 2020 03:35:02 -0700 Received: from hyd1349.t110.caveonetworks.com (unknown [10.29.45.13]) by maili.marvell.com (Postfix) with ESMTP id 598F73F7041; Thu, 8 Oct 2020 03:35:00 -0700 (PDT) From: Ankur Dwivedi To: CC: , , , , Ankur Dwivedi Date: Thu, 8 Oct 2020 16:04:34 +0530 Message-ID: <20201008103435.19187-3-adwivedi@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201008103435.19187-1-adwivedi@marvell.com> References: <20201008055423.32259-1-adwivedi@marvell.com> <20201008103435.19187-1-adwivedi@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-10-08_04:2020-10-08, 2020-10-08 signatures=0 Subject: [dpdk-dev] [PATCH v4 2/3] event/octeontx2: add crypto adapter framework X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The crypto adapter callback functions and associated data structures are added. Signed-off-by: Ankur Dwivedi --- drivers/crypto/octeontx2/meson.build | 1 + .../octeontx2/otx2_cryptodev_hw_access.h | 12 +++ .../crypto/octeontx2/otx2_cryptodev_mbox.h | 2 + drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 7 ++ .../rte_pmd_octeontx2_crypto_version.map | 9 +++ drivers/event/octeontx2/meson.build | 4 +- drivers/event/octeontx2/otx2_evdev.c | 4 + drivers/event/octeontx2/otx2_evdev.h | 11 +++ .../event/octeontx2/otx2_evdev_crypto_adptr.c | 81 +++++++++++++++++++ 9 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 drivers/event/octeontx2/otx2_evdev_crypto_adptr.c diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index 148ec184a..41114a5c3 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -10,6 +10,7 @@ deps += ['bus_pci'] deps += ['common_cpt'] deps += ['common_octeontx2'] deps += ['ethdev'] +deps += ['eventdev'] deps += ['security'] name = 'octeontx2_crypto' diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h index 43db6a642..a435818e0 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -42,6 +42,7 @@ #define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3) #define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3) +#define OTX2_CPT_AF_LF_CTL2(a) (0x29000ull | (uint64_t)(a) << 3) #define OTX2_CPT_LF_BAR2(vf, q_id) \ ((vf)->otx2_dev.bar2 + \ @@ -110,6 +111,17 @@ union otx2_cpt_af_lf_ctl { } s; }; +union otx2_cpt_af_lf_ctl2 { + uint64_t u; + struct { + uint64_t exe_no_swap : 1; + uint64_t exe_ldwb : 1; + uint64_t reserved_2_31 : 30; + uint64_t sso_pf_func : 16; + uint64_t nix_pf_func : 16; + } s; +}; + union otx2_cpt_lf_q_grp_ptr { uint64_t u; struct { diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h index 4bc057774..05efb4049 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h @@ -21,9 +21,11 @@ int otx2_cpt_queues_detach(const struct rte_cryptodev *dev); int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev); +__rte_internal int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg, uint64_t *val); +__rte_internal int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg, uint64_t val); diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h index 9d48da45f..96ff4eb41 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h @@ -6,6 +6,7 @@ #define _OTX2_CRYPTODEV_QP_H_ #include +#include #include #include @@ -30,6 +31,12 @@ struct otx2_cpt_qp { /**< Metabuf info required to support operations on the queue pair */ rte_iova_t iq_dma_addr; /**< Instruction queue address */ + struct rte_event ev; + /**< Event information required for binding cryptodev queue to + * eventdev queue. Used by crypto adapter. + */ + uint8_t ca_enable; + /**< Set when queue pair is added to crypto adapter */ }; #endif /* _OTX2_CRYPTODEV_QP_H_ */ diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map index 4a76d1d52..95ebda255 100644 --- a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map +++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map @@ -1,3 +1,12 @@ DPDK_21 { local: *; }; + +INTERNAL { + global: + + otx2_cpt_af_reg_read; + otx2_cpt_af_reg_write; + + local: *; +}; diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build index 0ade51cec..6dde86fc7 100644 --- a/drivers/event/octeontx2/meson.build +++ b/drivers/event/octeontx2/meson.build @@ -6,6 +6,7 @@ sources = files('otx2_worker.c', 'otx2_worker_dual.c', 'otx2_evdev.c', 'otx2_evdev_adptr.c', + 'otx2_evdev_crypto_adptr.c', 'otx2_evdev_irq.c', 'otx2_evdev_selftest.c', 'otx2_tim_evdev.c', @@ -24,6 +25,7 @@ foreach flag: extra_flags endif endforeach -deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2'] +deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2', 'pmd_octeontx2_crypto'] includes += include_directories('../../crypto/octeontx2') +includes += include_directories('../../common/cpt') diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index b8b57c388..461ad57f5 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -1587,6 +1587,10 @@ static struct rte_eventdev_ops otx2_sso_ops = { .timer_adapter_caps_get = otx2_tim_caps_get, + .crypto_adapter_caps_get = otx2_ca_caps_get, + .crypto_adapter_queue_pair_add = otx2_ca_qp_add, + .crypto_adapter_queue_pair_del = otx2_ca_qp_del, + .xstats_get = otx2_sso_xstats_get, .xstats_reset = otx2_sso_xstats_reset, .xstats_get_names = otx2_sso_xstats_get_names, diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 873724dd4..4bf715c03 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -388,6 +388,17 @@ int otx2_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eth_dev *eth_dev, int32_t tx_queue_id); +/* Event crypto adapter API's */ +int otx2_ca_caps_get(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, uint32_t *caps); + +int otx2_ca_qp_add(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, int32_t queue_pair_id, + const struct rte_event *event); + +int otx2_ca_qp_del(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, int32_t queue_pair_id); + /* Clean up API's */ typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev); void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id, diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c new file mode 100644 index 000000000..7197815ae --- /dev/null +++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include + +#include "otx2_cryptodev_hw_access.h" +#include "otx2_cryptodev_qp.h" +#include "otx2_cryptodev_mbox.h" +#include "otx2_evdev.h" + +int +otx2_ca_caps_get(const struct rte_eventdev *dev, + const struct rte_cryptodev *cdev, uint32_t *caps) +{ + RTE_SET_USED(dev); + RTE_SET_USED(cdev); + + *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | + RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW; + + return 0; +} + +int +otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, + int32_t queue_pair_id, const struct rte_event *event) +{ + struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev); + union otx2_cpt_af_lf_ctl2 af_lf_ctl2; + struct otx2_cpt_qp *qp; + int ret; + + qp = cdev->data->queue_pairs[queue_pair_id]; + + qp->ca_enable = 1; + rte_memcpy(&qp->ev, event, sizeof(struct rte_event)); + + ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + &af_lf_ctl2.u); + if (ret) + return ret; + + af_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get(); + ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + af_lf_ctl2.u); + if (ret) + return ret; + + sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F; + sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev); + + return 0; +} + +int +otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, + int32_t queue_pair_id) +{ + union otx2_cpt_af_lf_ctl2 af_lf_ctl2; + struct otx2_cpt_qp *qp; + int ret; + + RTE_SET_USED(dev); + + qp = cdev->data->queue_pairs[queue_pair_id]; + qp->ca_enable = 0; + memset(&qp->ev, 0, sizeof(struct rte_event)); + + ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + &af_lf_ctl2.u); + if (ret) + return ret; + + af_lf_ctl2.s.sso_pf_func = 0; + ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id), + af_lf_ctl2.u); + + return ret; +} -- 2.28.0