From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1598BA04BC; Fri, 9 Oct 2020 13:30:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4917D1D53D; Fri, 9 Oct 2020 13:30:06 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 8978F1D53C for ; Fri, 9 Oct 2020 13:30:03 +0200 (CEST) IronPort-SDR: Hig7xAULobUib9RzvZmciNMgtWVWo6OQYbb8sjE1OLFnLhCpOK3cjE6pD1HKpmZEmawL6wSFJb 3O/zTQQUxiqg== X-IronPort-AV: E=McAfee;i="6000,8403,9768"; a="229657313" X-IronPort-AV: E=Sophos;i="5.77,354,1596524400"; d="scan'208";a="229657313" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2020 04:30:03 -0700 IronPort-SDR: kzXWe/ravAcc4UHLMHnCn4MPF9JCWRSIZr5IZk84U5WfBa8Wq9QTwuUrFbYkaKxziIvmBxJEeb TtJbaqR0xpng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,354,1596524400"; d="scan'208";a="389099660" Received: from silpixa00399593.ir.intel.com (HELO silpixa00399593.ger.corp.intel.com) ([10.237.223.27]) by orsmga001.jf.intel.com with ESMTP; 09 Oct 2020 04:30:01 -0700 From: Pablo de Lara To: declan.doherty@intel.com Cc: dev@dpdk.org, Pablo de Lara Date: Fri, 9 Oct 2020 11:29:54 +0000 Message-Id: <20201009112954.189064-3-pablo.de.lara.guarch@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201009112954.189064-1-pablo.de.lara.guarch@intel.com> References: <20200921114508.275079-1-pablo.de.lara.guarch@intel.com> <20201009112954.189064-1-pablo.de.lara.guarch@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v5 3/3] crypto/aesni_mb: support KASUMI F8/F9 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for KASUMI-F8/F9 algorithms through the intel-ipsec-mb job API, allowing the mix of these algorithms with others. Signed-off-by: Pablo de Lara --- v5: - Rebased on top of crypto subtree v3/v4: - Fixed compilation when intel-ipsec-mb version is lower than 0.54 v2: - Added commit description --- doc/guides/cryptodevs/aesni_mb.rst | 2 + doc/guides/cryptodevs/features/aesni_mb.ini | 2 + doc/guides/rel_notes/release_20_11.rst | 1 + .../crypto/aesni_mb/aesni_mb_pmd_private.h | 13 ++++-- drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 34 +++++++++++++++ .../crypto/aesni_mb/rte_aesni_mb_pmd_ops.c | 41 +++++++++++++++++++ 6 files changed, 90 insertions(+), 3 deletions(-) diff --git a/doc/guides/cryptodevs/aesni_mb.rst b/doc/guides/cryptodevs/aesni_mb.rst index 18631f6db..abc10fbda 100644 --- a/doc/guides/cryptodevs/aesni_mb.rst +++ b/doc/guides/cryptodevs/aesni_mb.rst @@ -37,6 +37,7 @@ Cipher algorithms: * RTE_CRYPTO_CIPHER_AES256_ECB * RTE_CRYPTO_CIPHER_ZUC_EEA3 * RTE_CRYPTO_CIPHER_SNOW3G_UEA2 +* RTE_CRYPTO_CIPHER_KASUMI_F8 Hash algorithms: @@ -56,6 +57,7 @@ Hash algorithms: * RTE_CRYPTO_AUTH_SHA512 * RTE_CRYPTO_AUTH_ZUC_EIA3 * RTE_CRYPTO_AUTH_SNOW3G_UIA2 +* RTE_CRYPTO_AUTH_KASUMI_F9 AEAD algorithms: diff --git a/doc/guides/cryptodevs/features/aesni_mb.ini b/doc/guides/cryptodevs/features/aesni_mb.ini index ea37a6a58..356139d46 100644 --- a/doc/guides/cryptodevs/features/aesni_mb.ini +++ b/doc/guides/cryptodevs/features/aesni_mb.ini @@ -35,6 +35,7 @@ AES ECB (192) = Y AES ECB (256) = Y ZUC EEA3 = Y SNOW3G UEA2 = Y +KASUMI F8 = Y ; ; Supported authentication algorithms of the 'aesni_mb' crypto driver. @@ -56,6 +57,7 @@ AES CMAC (128) = Y AES GMAC = Y ZUC EIA3 = Y SNOW3G UIA2 = Y +KASUMI F9 = Y ; ; Supported AEAD algorithms of the 'aesni_mb' crypto driver. diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index da2fe9e44..015cea576 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -79,6 +79,7 @@ New Features * Added support for AES-ECB 128, 192 and 256. * Added support for ZUC-EEA3/EIA3 algorithms. * Added support for SNOW3G-UEA2/UIA2 algorithms. + * Added support for KASUMI-F8/F9 algorithms. * **Added Intel ACC100 bbdev PMD.** diff --git a/drivers/crypto/aesni_mb/aesni_mb_pmd_private.h b/drivers/crypto/aesni_mb/aesni_mb_pmd_private.h index 85039dbf2..9693bf985 100644 --- a/drivers/crypto/aesni_mb/aesni_mb_pmd_private.h +++ b/drivers/crypto/aesni_mb/aesni_mb_pmd_private.h @@ -57,7 +57,8 @@ static const unsigned auth_blocksize[] = { [PLAIN_SHA_512] = 128, #if IMB_VERSION(0, 53, 3) <= IMB_VERSION_NUM [IMB_AUTH_ZUC_EIA3_BITLEN] = 16, - [IMB_AUTH_SNOW3G_UIA2_BITLEN] = 16 + [IMB_AUTH_SNOW3G_UIA2_BITLEN] = 16, + [IMB_AUTH_KASUMI_UIA1] = 16 #endif }; @@ -92,7 +93,8 @@ static const unsigned auth_truncated_digest_byte_lengths[] = { [PLAIN_SHA_512] = 64, #if IMB_VERSION(0, 53, 3) <= IMB_VERSION_NUM [IMB_AUTH_ZUC_EIA3_BITLEN] = 4, - [IMB_AUTH_SNOW3G_UIA2_BITLEN] = 4 + [IMB_AUTH_SNOW3G_UIA2_BITLEN] = 4, + [IMB_AUTH_KASUMI_UIA1] = 4 #endif }; @@ -128,7 +130,8 @@ static const unsigned auth_digest_byte_lengths[] = { [PLAIN_SHA_512] = 64, #if IMB_VERSION(0, 53, 3) <= IMB_VERSION_NUM [IMB_AUTH_ZUC_EIA3_BITLEN] = 4, - [IMB_AUTH_SNOW3G_UIA2_BITLEN] = 4 + [IMB_AUTH_SNOW3G_UIA2_BITLEN] = 4, + [IMB_AUTH_KASUMI_UIA1] = 4 #endif /**< Vector mode dependent pointer table of the multi-buffer APIs */ @@ -244,6 +247,8 @@ struct aesni_mb_session { #if IMB_VERSION(0, 53, 3) <= IMB_VERSION_NUM snow3g_key_schedule_t pKeySched_snow3g_cipher; /**< SNOW3G scheduled cipher key */ + kasumi_key_sched_t pKeySched_kasumi_cipher; + /**< KASUMI scheduled cipher key */ #endif }; } cipher; @@ -289,6 +294,8 @@ struct aesni_mb_session { #if IMB_VERSION(0, 53, 3) <= IMB_VERSION_NUM snow3g_key_schedule_t pKeySched_snow3g_auth; /**< SNOW3G scheduled authentication key */ + kasumi_key_sched_t pKeySched_kasumi_auth; + /**< KASUMI scheduled authentication key */ #endif }; /** Generated digest size by the Multi-buffer library */ diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c index bb917b8ff..34a39ca99 100644 --- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c +++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c @@ -279,6 +279,19 @@ aesni_mb_set_session_auth_parameters(const MB_MGR *mb_mgr, IMB_SNOW3G_INIT_KEY_SCHED(mb_mgr, xform->auth.key.data, &sess->auth.pKeySched_snow3g_auth); return 0; + } else if (xform->auth.algo == RTE_CRYPTO_AUTH_KASUMI_F9) { + sess->auth.algo = IMB_AUTH_KASUMI_UIA1; + uint16_t kasumi_f9_digest_len = + get_truncated_digest_byte_length(IMB_AUTH_KASUMI_UIA1); + if (sess->auth.req_digest_len != kasumi_f9_digest_len) { + AESNI_MB_LOG(ERR, "Invalid digest size\n"); + return -EINVAL; + } + sess->auth.gen_digest_len = sess->auth.req_digest_len; + + IMB_KASUMI_INIT_F9_KEY_SCHED(mb_mgr, xform->auth.key.data, + &sess->auth.pKeySched_kasumi_auth); + return 0; } #endif @@ -417,6 +430,7 @@ aesni_mb_set_session_cipher_parameters(const MB_MGR *mb_mgr, #if IMB_VERSION(0, 53, 3) <= IMB_VERSION_NUM uint8_t is_zuc = 0; uint8_t is_snow3g = 0; + uint8_t is_kasumi = 0; #endif if (xform == NULL) { @@ -481,6 +495,10 @@ aesni_mb_set_session_cipher_parameters(const MB_MGR *mb_mgr, sess->cipher.mode = IMB_CIPHER_SNOW3G_UEA2_BITLEN; is_snow3g = 1; break; + case RTE_CRYPTO_CIPHER_KASUMI_F8: + sess->cipher.mode = IMB_CIPHER_KASUMI_UEA1_BITLEN; + is_kasumi = 1; + break; #endif default: AESNI_MB_LOG(ERR, "Unsupported cipher mode parameter"); @@ -597,6 +615,14 @@ aesni_mb_set_session_cipher_parameters(const MB_MGR *mb_mgr, sess->cipher.key_length_in_bytes = 16; IMB_SNOW3G_INIT_KEY_SCHED(mb_mgr, xform->cipher.key.data, &sess->cipher.pKeySched_snow3g_cipher); + } else if (is_kasumi) { + if (xform->cipher.key.length != 16) { + AESNI_MB_LOG(ERR, "Invalid cipher key length"); + return -EINVAL; + } + sess->cipher.key_length_in_bytes = 16; + IMB_KASUMI_INIT_F8_KEY_SCHED(mb_mgr, xform->cipher.key.data, + &sess->cipher.pKeySched_kasumi_cipher); #endif } else { if (xform->cipher.key.length != 8) { @@ -1251,6 +1277,9 @@ set_mb_job_params(JOB_AES_HMAC *job, struct aesni_mb_qp *qp, job->u.SNOW3G_UIA2._iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->auth_iv.offset); break; + case IMB_AUTH_KASUMI_UIA1: + job->u.KASUMI_UIA1._key = (void *) &session->auth.pKeySched_kasumi_auth; + break; #endif default: job->u.HMAC._hashed_auth_key_xor_ipad = session->auth.pads.inner; @@ -1282,6 +1311,9 @@ set_mb_job_params(JOB_AES_HMAC *job, struct aesni_mb_qp *qp, } else if (job->cipher_mode == IMB_CIPHER_SNOW3G_UEA2_BITLEN) { job->enc_keys = &session->cipher.pKeySched_snow3g_cipher; m_offset = 0; + } else if (job->cipher_mode == IMB_CIPHER_KASUMI_UEA1_BITLEN) { + job->enc_keys = &session->cipher.pKeySched_kasumi_cipher; + m_offset = 0; } #endif @@ -1383,6 +1415,8 @@ set_mb_job_params(JOB_AES_HMAC *job, struct aesni_mb_qp *qp, #if IMB_VERSION(0, 53, 3) <= IMB_VERSION_NUM if (job->cipher_mode == IMB_CIPHER_ZUC_EEA3) job->msg_len_to_cipher_in_bytes >>= 3; + else if (job->hash_alg == IMB_AUTH_KASUMI_UIA1) + job->msg_len_to_hash_in_bytes >>= 3; #endif /* Set user data to be crypto operation data struct */ diff --git a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c index 2b236b754..0f74be126 100644 --- a/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c +++ b/drivers/crypto/aesni_mb/rte_aesni_mb_pmd_ops.c @@ -606,6 +606,47 @@ static const struct rte_cryptodev_capabilities aesni_mb_pmd_capabilities[] = { }, } }, } }, + { /* KASUMI (F9) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_KASUMI_F9, + .block_size = 8, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .digest_size = { + .min = 4, + .max = 4, + .increment = 0 + }, + .iv_size = { 0 } + }, } + }, } + }, + { /* KASUMI (F8) */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, + {.cipher = { + .algo = RTE_CRYPTO_CIPHER_KASUMI_F8, + .block_size = 8, + .key_size = { + .min = 16, + .max = 16, + .increment = 0 + }, + .iv_size = { + .min = 8, + .max = 8, + .increment = 0 + } + }, } + }, } + }, #endif RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; -- 2.25.1