From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36D4BA04B6; Tue, 13 Oct 2020 11:07:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0610B1D635; Tue, 13 Oct 2020 11:07:18 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id BA3A21D559 for ; Tue, 13 Oct 2020 11:07:15 +0200 (CEST) IronPort-SDR: JP6yyfR3aYKrI0bS8NgJLjrU/Fpvu9O3ywqqy2ootAVS3L9qM9xwNu01er88PaalnD16+8jroz eV3YU0REWHlg== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="250572002" X-IronPort-AV: E=Sophos;i="5.77,369,1596524400"; d="scan'208";a="250572002" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 02:07:13 -0700 IronPort-SDR: C/s/89SXYCkyswid9RA9SYgusPOlFdNuwjNdMFPnaJTgOZbQ0Dw5Z3K4izphvWNOsriNwTQd98 mg87Y7t/faCA== X-IronPort-AV: E=Sophos;i="5.77,369,1596524400"; d="scan'208";a="530321019" Received: from bricha3-mobl.ger.corp.intel.com ([10.213.245.209]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 13 Oct 2020 02:07:11 -0700 Date: Tue, 13 Oct 2020 10:07:08 +0100 From: Bruce Richardson To: Mairtin o Loingsigh Cc: jasvinder.singh@intel.com, pablo.de.lara.guarch@intel.com, konstantin.ananyev@intel.com, dev@dpdk.org, brendan.ryan@intel.com, david.coyle@intel.com Message-ID: <20201013090708.GA1496@bricha3-MOBL.ger.corp.intel.com> References: <20201006162319.7981-1-mairtin.oloingsigh@intel.com> <20201009135045.8505-1-mairtin.oloingsigh@intel.com> <20201009135045.8505-2-mairtin.oloingsigh@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201009135045.8505-2-mairtin.oloingsigh@intel.com> Subject: Re: [dpdk-dev] [PATCH v5 1/2] net: add run-time architecture specific CRC selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Oct 09, 2020 at 02:50:44PM +0100, Mairtin o Loingsigh wrote: > This patch adds support for run-time selection of the optimal > architecture-specific CRC path, based on the supported instruction set(s) > of the CPU. > > The compiler option checks have been moved from the C files to the meson > script. The rte_cpu_get_flag_enabled function is called automatically by > the library at process initialization time to determine which > instructions the CPU supports, with the most optimal supported CRC path > ultimately selected. > > Signed-off-by: Mairtin o Loingsigh > Signed-off-by: David Coyle > Acked-by: Konstantin Ananyev > --- > doc/guides/rel_notes/release_20_11.rst | 4 + > lib/librte_net/meson.build | 34 ++++++- > lib/librte_net/net_crc.h | 34 +++++++ > lib/librte_net/{net_crc_neon.h => net_crc_neon.c} | 26 ++--- > lib/librte_net/{net_crc_sse.h => net_crc_sse.c} | 34 ++----- > lib/librte_net/rte_net_crc.c | 116 +++++++++++++++------- > 6 files changed, 168 insertions(+), 80 deletions(-) > create mode 100644 lib/librte_net/net_crc.h > rename lib/librte_net/{net_crc_neon.h => net_crc_neon.c} (95%) > rename lib/librte_net/{net_crc_sse.h => net_crc_sse.c} (94%) > > diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst > index 808bdc4e5..b77297f7e 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -55,6 +55,10 @@ New Features > Also, make sure to start the actual text at the margin. > ======================================================= > > +* **Updated CRC modules of rte_net library.** > + > + * Added run-time selection of the optimal architecture-specific CRC path. > + > * **Updated Broadcom bnxt driver.** > > Updated the Broadcom bnxt driver with new features and improvements, including: > diff --git a/lib/librte_net/meson.build b/lib/librte_net/meson.build > index 24ed8253b..fa439b9e5 100644 > --- a/lib/librte_net/meson.build > +++ b/lib/librte_net/meson.build > @@ -1,5 +1,5 @@ > # SPDX-License-Identifier: BSD-3-Clause > -# Copyright(c) 2017 Intel Corporation > +# Copyright(c) 2017-2020 Intel Corporation > > headers = files('rte_ip.h', > 'rte_tcp.h', > @@ -20,3 +20,35 @@ headers = files('rte_ip.h', > > sources = files('rte_arp.c', 'rte_ether.c', 'rte_net.c', 'rte_net_crc.c') > deps += ['mbuf'] > + > +if dpdk_conf.has('RTE_ARCH_X86_64') > + net_crc_sse42_cpu_support = ( > + cc.get_define('__PCLMUL__', args: machine_args) != '') > + net_crc_sse42_cc_support = ( > + cc.has_argument('-mpclmul') and cc.has_argument('-maes')) > + > + build_static_net_crc_sse42_lib = 0 > + > + if net_crc_sse42_cpu_support == true > + sources += files('net_crc_sse.c') > + cflags += ['-DCC_X86_64_SSE42_PCLMULQDQ_SUPPORT'] > + elif net_crc_sse42_cc_support == true > + build_static_net_crc_sse42_lib = 1 > + net_crc_sse42_lib_cflags = ['-mpclmul', '-maes'] > + cflags += ['-DCC_X86_64_SSE42_PCLMULQDQ_SUPPORT'] > + endif > + > + if build_static_net_crc_sse42_lib == 1 > + net_crc_sse42_lib = static_library( > + 'net_crc_sse42_lib', > + 'net_crc_sse.c', > + dependencies: static_rte_eal, > + c_args: [cflags, > + net_crc_sse42_lib_cflags]) > + objs += net_crc_sse42_lib.extract_objects('net_crc_sse.c') > + endif > +elif (dpdk_conf.has('RTE_ARCH_ARM64') and > + cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != '') > + sources += files('net_crc_neon.c') > + cflags += ['-DCC_ARM64_NEON_PMULL_SUPPORT'] > +endif This meson code looks ok to me. Not sure you needed the variable for "net_crc_sse42_lib_cflags", but generally looks good. Acked-by: Bruce Richardson