From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 46D13A04B7; Tue, 13 Oct 2020 12:41:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2CBEE1DADC; Tue, 13 Oct 2020 12:38:51 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id A45F31DAD1 for ; Tue, 13 Oct 2020 12:38:47 +0200 (CEST) IronPort-SDR: BlgFGhu9zM6DfOtvtXrKey1xHJMg5l2wQMtrETCCQ0iFrGkINRy6mLP3tG4Z+a/J+XGcUYRg7C JG2Ui9EtmSrA== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165998339" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="165998339" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 03:38:47 -0700 IronPort-SDR: iCXSoiIb0/JT3W1DYF4hPHIjnHDDodfmFE9A6dGpGwirQLrpHzsEtK9aRtHW4K0faXWYQlM+ia SWZyly4pytrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="463443033" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by orsmga004.jf.intel.com with ESMTP; 13 Oct 2020 03:38:45 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, --dry-run@dpdk.org, Ciara Power , Qiming Yang , Qi Zhang Date: Tue, 13 Oct 2020 11:38:09 +0100 Message-Id: <20201013103817.305423-10-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013103817.305423-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013103817.305423-1-ciara.power@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v4 09/17] net/ice: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qiming Yang Cc: Qi Zhang Signed-off-by: Ciara Power --- v4: Updated enum name. --- drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 93a0ac6918..0003ce2afe 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -2989,7 +2989,9 @@ ice_set_rx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->rx_vec_allowed = true; for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; @@ -2999,8 +3001,10 @@ ice_set_rx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { @@ -3167,7 +3171,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_tx_vec_dev_check(dev)) { + if (!ice_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_128) { ad->tx_vec_allowed = true; for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; @@ -3177,8 +3183,10 @@ ice_set_tx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_SIMD_256) use_avx2 = true; } else { -- 2.22.0