From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9DED1A04B7; Tue, 13 Oct 2020 13:08:50 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 53AF51DB03; Tue, 13 Oct 2020 13:05:15 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 0D73B1DB03 for ; Tue, 13 Oct 2020 13:05:13 +0200 (CEST) IronPort-SDR: /yFw+2/KnjfoBvG12n73lTqeQ3JKddvwcCx24Oulcisn8HjsdZX80opBQ0Gazjlv9+MrG3AySP 9S7kieE5nSlQ== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="153720468" X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="153720468" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2020 04:05:13 -0700 IronPort-SDR: YSIRZPXK6sNa67Ukun+n57JNS/8bqAe0DoR3EKdfrxZViqSLgjJQ9GNKbY/yecd0PwXmOoOEs3 eb77Ewnaj82A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,370,1596524400"; d="scan'208";a="299525166" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga007.fm.intel.com with ESMTP; 13 Oct 2020 04:05:08 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko , Viacheslav Ovsiienko , Matan Azrad , Shahaf Shuler Date: Tue, 13 Oct 2020 12:04:31 +0100 Message-Id: <20201013110437.309110-12-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201013110437.309110-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201013110437.309110-1-ciara.power@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v5 11/17] net/mlx5: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Matan Azrad Cc: Shahaf Shuler Cc: Viacheslav Ovsiienko Signed-off-by: Ciara Power Acked-by: Viacheslav Ovsiienko --- v4: Updated enum name. v2: Moved check for max bitwidth into existing check vec support function. --- drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index 711dcd35fa..49f1b61ff8 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -148,6 +148,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; uint32_t i; + if (rte_get_max_simd_bitwidth() < RTE_SIMD_128) + return -ENOTSUP; if (!priv->config.rx_vec_en) return -ENOTSUP; if (mlx5_mprq_enabled(dev)) -- 2.22.0