From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA2C7A04DB; Thu, 15 Oct 2020 12:31:16 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9871E1DE1E; Thu, 15 Oct 2020 12:31:15 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 09E4A1DE1E for ; Thu, 15 Oct 2020 12:31:12 +0200 (CEST) IronPort-SDR: R4cfNhmY+oY43FUTrL6w0waF5tRb7NEMkiKbOHKVR9xWozBs4Or/yGGQ9yKngPhixPZOim+vvm 7webUrb/Ak4Q== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="183856149" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="183856149" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:31:09 -0700 IronPort-SDR: anDv0E6YPFGqA5fN+hPjHNN1SMyu1l6B1rfcpKAnX3kwq5rpus9oAKGOUe6Iv3LiDV8s0o4UA7 xQ9UOMrAh3dw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="390932683" Received: from silpixa00399779.ir.intel.com (HELO silpixa00399779.ger.corp.intel.com) ([10.237.222.209]) by orsmga001.jf.intel.com with ESMTP; 15 Oct 2020 03:31:07 -0700 From: Harry van Haaren To: dev@dpdk.org Cc: ruifeng.wang@arm.com, david.marchand@redhat.com, jerinj@marvell.com, pbhagavatula@marvell.com, Harry van Haaren Date: Thu, 15 Oct 2020 11:32:37 +0100 Message-Id: <20201015103237.43497-1-harry.van.haaren@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200914151021.23806-1-harry.van.haaren@intel.com> References: <20200914151021.23806-1-harry.van.haaren@intel.com> Subject: [dpdk-dev] [PATCH v3] eal: add new prefetch write variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds new rte_prefetchX_write() variants, that suggest to the compiler to use a prefetch instruction with intention to write. As a compiler builtin, the compiler can choose based on compilation target what the best implementation for this instruction is. Three versions are provided, targeting the different levels of cache. Signed-off-by: Harry van Haaren Reviewed-by: Jerin Jacob Reviewed-by: Ruifeng Wang --- v3: - Add reviewed by tags from Jerin and Ruifeng, thanks! - Add __rte_experimental as they are new functions (David) This required adding the rte_compat.h include. - Rework return type to new line (Jerin) - Add calls in test_prefetch.c to new functions (David) - Add item to release notes (David) v2: - Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan) The integer constants passed to the builtin are not available as a #define value, and doing #defines just for this write variant does not seems a nice solution to me... particularly for those using IDEs where any #define value is auto-hinted for code-completion. --- app/test/test_prefetch.c | 4 ++ doc/guides/rel_notes/release_20_11.rst | 6 ++ lib/librte_eal/include/generic/rte_prefetch.h | 57 +++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/app/test/test_prefetch.c b/app/test/test_prefetch.c index 41f219af78..32e08f8afe 100644 --- a/app/test/test_prefetch.c +++ b/app/test/test_prefetch.c @@ -26,6 +26,10 @@ test_prefetch(void) rte_prefetch1(&a); rte_prefetch2(&a); + rte_prefetch0_write(&a); + rte_prefetch1_write(&a); + rte_prefetch2_write(&a); + return 0; } diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index 0925123e9c..8b51ef0dbc 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -62,6 +62,12 @@ New Features The functions are provided as a generic stubs and x86 specific implementation. +* **Added prefetch with intention to write APIs.** + + Added new prefetch function variants e.g. ``rte_prefetch0_write``, + which allow the programmer to prefetch a cache line and also indicate + the intention to write. + * **Updated CRC modules of the net library.** * Added runtime selection of the optimal architecture-specific CRC path. diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h index 6e47bdfbad..53d68c40f1 100644 --- a/lib/librte_eal/include/generic/rte_prefetch.h +++ b/lib/librte_eal/include/generic/rte_prefetch.h @@ -5,6 +5,8 @@ #ifndef _RTE_PREFETCH_H_ #define _RTE_PREFETCH_H_ +#include "rte_compat.h" + /** * @file * @@ -51,4 +53,59 @@ static inline void rte_prefetch2(const volatile void *p); */ static inline void rte_prefetch_non_temporal(const volatile void *p); +/** + * Prefetch a cache line into all cache levels, with intention to write. This + * prefetch variant hints to the CPU that the program is expecting to write to + * the cache line being prefetched. + * + * @param p Address to prefetch + */ +__rte_experimental +static inline void +rte_prefetch0_write(const void *p) +{ + /* 1 indicates intention to write, 3 sets target cache level to L1. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 3); +} + +/** + * Prefetch a cache line into all cache levels, except the 0th, with intention + * to write. This prefetch variant hints to the CPU that the program is + * expecting to write to the cache line being prefetched. + * + * @param p Address to prefetch + */ +__rte_experimental +static inline void +rte_prefetch1_write(const void *p) +{ + /* 1 indicates intention to write, 2 sets target cache level to L2. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 2); +} + +/** + * Prefetch a cache line into all cache levels, except the 0th and 1st, with + * intention to write. This prefetch variant hints to the CPU that the program + * is expecting to write to the cache line being prefetched. + * + * @param p Address to prefetch + */ +__rte_experimental +static inline void +rte_prefetch2_write(const void *p) +{ + /* 1 indicates intention to write, 1 sets target cache level to L3. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 1); +} + + #endif /* _RTE_PREFETCH_H_ */ -- 2.17.1