From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C1BD9A04DB; Thu, 15 Oct 2020 12:44:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CB17D1E4A5; Thu, 15 Oct 2020 12:39:10 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id C00F91E497 for ; Thu, 15 Oct 2020 12:39:05 +0200 (CEST) IronPort-SDR: 6SZHugyy7Hmo+kdAuwUVoXaKy6Yx5d91EcGKnlLU+G7AUgsF0eIWfnYsN1t2D6PqHQZKK/CWOM rhZj3bIlFwGQ== X-IronPort-AV: E=McAfee;i="6000,8403,9774"; a="227964303" X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="227964303" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2020 03:39:05 -0700 IronPort-SDR: n+hO8bATkXrczSHu0PDX2EvUXEv1hTJ+X7xnBkUV8MX08aFuizu8WuW2sl3M1kIXhK4U4ukAVC w7d1y7ymGWAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,378,1596524400"; d="scan'208";a="520728609" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.239]) by fmsmga006.fm.intel.com with ESMTP; 15 Oct 2020 03:39:03 -0700 From: Ciara Power To: dev@dpdk.org Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, Ciara Power Date: Thu, 15 Oct 2020 11:38:14 +0100 Message-Id: <20201015103814.253636-19-ciara.power@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20201015103814.253636-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20201015103814.253636-1-ciara.power@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v6 18/18] acl: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. These checks are added in the check alg helper functions. Cc: Konstantin Ananyev Signed-off-by: Ciara Power --- lib/librte_acl/rte_acl.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c index 7c2f60b2d6..4ec6c982c9 100644 --- a/lib/librte_acl/rte_acl.c +++ b/lib/librte_acl/rte_acl.c @@ -16,6 +16,8 @@ static struct rte_tailq_elem rte_acl_tailq = { }; EAL_REGISTER_TAILQ(rte_acl_tailq) +uint16_t max_simd_bitwidth; + #ifndef CC_AVX512_SUPPORT /* * If the compiler doesn't support AVX512 instructions, @@ -114,9 +116,13 @@ acl_check_alg_arm(enum rte_acl_classify_alg alg) { if (alg == RTE_ACL_CLASSIFY_NEON) { #if defined(RTE_ARCH_ARM64) - return 0; + if (max_simd_bitwidth >= RTE_SIMD_128) + return 0; + else + return -ENOTSUP; #elif defined(RTE_ARCH_ARM) - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) && + max_simd_bitwidth >= RTE_SIMD_128) return 0; return -ENOTSUP; #else @@ -136,7 +142,10 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg) { if (alg == RTE_ACL_CLASSIFY_ALTIVEC) { #if defined(RTE_ARCH_PPC_64) - return 0; + if (max_simd_bitwidth >= RTE_SIMD_128) + return 0; + else + return -ENOTSUP; #else return -ENOTSUP; #endif @@ -158,7 +167,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) && - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW)) + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) && + max_simd_bitwidth >= RTE_SIMD_512) return 0; #endif return -ENOTSUP; @@ -166,7 +176,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (alg == RTE_ACL_CLASSIFY_AVX2) { #ifdef CC_AVX2_SUPPORT - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) && + max_simd_bitwidth >= RTE_SIMD_256) return 0; #endif return -ENOTSUP; @@ -174,7 +185,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg) if (alg == RTE_ACL_CLASSIFY_SSE) { #ifdef RTE_ARCH_X86 - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1)) + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) && + max_simd_bitwidth >= RTE_SIMD_128) return 0; #endif return -ENOTSUP; @@ -406,6 +418,9 @@ rte_acl_create(const struct rte_acl_param *param) TAILQ_INSERT_TAIL(acl_list, te, next); } + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + exit: rte_mcfg_tailq_write_unlock(); return ctx; -- 2.22.0