DPDK patches and discussions
 help / color / mirror / Atom feed
From: Ciara Power <ciara.power@intel.com>
To: dev@dpdk.org
Cc: viktorin@rehivetech.com, ruifeng.wang@arm.com,
	jerinj@marvell.com, drc@linux.vnet.ibm.com,
	bruce.richardson@intel.com, konstantin.ananyev@intel.com,
	david.marchand@redhat.com, Ciara Power <ciara.power@intel.com>
Subject: [dpdk-dev] [PATCH v7 18/18] acl: add checks for max SIMD bitwidth
Date: Thu, 15 Oct 2020 16:22:59 +0100
Message-ID: <20201015152259.97562-19-ciara.power@intel.com> (raw)
In-Reply-To: <20201015152259.97562-1-ciara.power@intel.com>

When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path. These checks are added in the check alg helper functions.

Cc: Konstantin Ananyev <konstantin.ananyev@intel.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>

---
v7:
  - Removed global variable for max SIMD bitwidth.
  - Added helper function for checking AVX512 cpu flags.
  - Separated condition checking for the AVX512 algorithms to allow for
    checking 256/512 max SIMD bitwidth, respectively.
  - Added to docs to reflect the added changes in algorithm selection.
---
 .../prog_guide/packet_classif_access_ctrl.rst | 14 ++++--
 lib/librte_acl/rte_acl.c                      | 48 ++++++++++++++-----
 lib/librte_acl/rte_acl.h                      |  1 +
 3 files changed, 48 insertions(+), 15 deletions(-)

diff --git a/doc/guides/prog_guide/packet_classif_access_ctrl.rst b/doc/guides/prog_guide/packet_classif_access_ctrl.rst
index 7659af8eb5..72c193b17f 100644
--- a/doc/guides/prog_guide/packet_classif_access_ctrl.rst
+++ b/doc/guides/prog_guide/packet_classif_access_ctrl.rst
@@ -368,34 +368,40 @@ After rte_acl_build() over given AC context has finished successfully, it can be
 There are several implementations of classify algorithm:
 
 *   **RTE_ACL_CLASSIFY_SCALAR**: generic implementation, doesn't require any specific HW support.
+    Requires max SIMD bitwidth to be at least 64.
 
 *   **RTE_ACL_CLASSIFY_SSE**: vector implementation, can process up to 8 flows in parallel. Requires SSE 4.1 support.
+    Requires max SIMD bitwidth to be at least 128.
 
 *   **RTE_ACL_CLASSIFY_AVX2**: vector implementation, can process up to 16 flows in parallel. Requires AVX2 support.
+    Requires max SIMD bitwidth to be at least 256.
 
 *   **RTE_ACL_CLASSIFY_NEON**: vector implementation, can process up to 8 flows
-    in parallel. Requires NEON support.
+    in parallel. Requires NEON support. Requires max SIMD bitwidth to be at least 128.
 
 *   **RTE_ACL_CLASSIFY_ALTIVEC**: vector implementation, can process up to 8
-    flows in parallel. Requires ALTIVEC support.
+    flows in parallel. Requires ALTIVEC support. Requires max SIMD bitwidth to be at least 128.
 
 *   **RTE_ACL_CLASSIFY_AVX512X16**: vector implementation, can process up to 16
     flows in parallel. Uses 256-bit width SIMD registers.
-    Requires AVX512 support.
+    Requires AVX512 support. Requires max SIMD bitwidth to be at least 256.
 
 *   **RTE_ACL_CLASSIFY_AVX512X32**: vector implementation, can process up to 32
     flows in parallel. Uses 512-bit width SIMD registers.
-    Requires AVX512 support.
+    Requires AVX512 support. Requires max SIMD bitwidth to be at least 512.
 
 It is purely a runtime decision which method to choose, there is no build-time difference.
 All implementations operates over the same internal RT structures and use similar principles. The main difference is that vector implementations can manually exploit IA SIMD instructions and process several input data flows in parallel.
 At startup ACL library determines the highest available classify method for the given platform and sets it as default one. Though the user has an ability to override the default classifier function for a given ACL context or perform particular search using non-default classify method. In that case it is user responsibility to make sure that given platform supports selected classify implementation.
+The max SIMD bitwidth value set in EAL is also taken into consideration when determining if a classify method is supported, see :ref:`max_simd_bitwidth` for more information.
 
 .. note::
 
      Right now ``RTE_ACL_CLASSIFY_AVX512X32`` is not selected by default
      (due to possible frequency level change), but it can be selected at
      runtime by apps through the use of ACL API: ``rte_acl_set_ctx_classify``.
+     The max SIMD bitwidth value will also need to be set to 512 to enable this classify method.
+     See :doc:`../howto/avx512` for more information about setting this value.
 
 Application Programming Interface (API) Usage
 ---------------------------------------------
diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c
index 7c2f60b2d6..026d2e7430 100644
--- a/lib/librte_acl/rte_acl.c
+++ b/lib/librte_acl/rte_acl.c
@@ -114,9 +114,13 @@ acl_check_alg_arm(enum rte_acl_classify_alg alg)
 {
 	if (alg == RTE_ACL_CLASSIFY_NEON) {
 #if defined(RTE_ARCH_ARM64)
-		return 0;
+		if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128)
+			return 0;
+		else
+			return -ENOTSUP;
 #elif defined(RTE_ARCH_ARM)
-		if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
+		if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) &&
+				rte_get_max_simd_bitwidth() >= RTE_SIMD_128)
 			return 0;
 		return -ENOTSUP;
 #else
@@ -136,7 +140,10 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)
 {
 	if (alg == RTE_ACL_CLASSIFY_ALTIVEC) {
 #if defined(RTE_ARCH_PPC_64)
-		return 0;
+		if (rte_get_max_simd_bitwidth() >= RTE_SIMD_128)
+			return 0;
+		else
+			return -ENOTSUP;
 #else
 		return -ENOTSUP;
 #endif
@@ -145,6 +152,17 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)
 	return -EINVAL;
 }
 
+#ifdef CC_AVX512_SUPPORT
+static int
+acl_check_avx512_cpu_flags(void)
+{
+	return (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) &&
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) &&
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW));
+}
+#endif
+
 /*
  * Helper function for acl_check_alg.
  * Check support for x86 specific classify methods.
@@ -152,13 +170,19 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)
 static int
 acl_check_alg_x86(enum rte_acl_classify_alg alg)
 {
-	if (alg == RTE_ACL_CLASSIFY_AVX512X16 ||
-			alg == RTE_ACL_CLASSIFY_AVX512X32) {
+	if (alg == RTE_ACL_CLASSIFY_AVX512X32) {
 #ifdef CC_AVX512_SUPPORT
-		if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) &&
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) &&
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW))
+		if (acl_check_avx512_cpu_flags() != 0 &&
+			rte_get_max_simd_bitwidth() >= RTE_SIMD_512)
+			return 0;
+#endif
+		return -ENOTSUP;
+	}
+
+	if (alg == RTE_ACL_CLASSIFY_AVX512X16) {
+#ifdef CC_AVX512_SUPPORT
+		if (acl_check_avx512_cpu_flags() != 0 &&
+			rte_get_max_simd_bitwidth() >= RTE_SIMD_256)
 			return 0;
 #endif
 		return -ENOTSUP;
@@ -166,7 +190,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg)
 
 	if (alg == RTE_ACL_CLASSIFY_AVX2) {
 #ifdef CC_AVX2_SUPPORT
-		if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
+		if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) &&
+				rte_get_max_simd_bitwidth() >= RTE_SIMD_256)
 			return 0;
 #endif
 		return -ENOTSUP;
@@ -174,7 +199,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg)
 
 	if (alg == RTE_ACL_CLASSIFY_SSE) {
 #ifdef RTE_ARCH_X86
-		if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
+		if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) &&
+				rte_get_max_simd_bitwidth() >= RTE_SIMD_128)
 			return 0;
 #endif
 		return -ENOTSUP;
diff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h
index 1bfed00743..f7f5f08701 100644
--- a/lib/librte_acl/rte_acl.h
+++ b/lib/librte_acl/rte_acl.h
@@ -329,6 +329,7 @@ rte_acl_classify_alg(const struct rte_acl_ctx *ctx,
  *   New default classify algorithm for given ACL context.
  *   It is the caller responsibility to ensure that the value refers to the
  *   existing algorithm, and that it could be run on the given CPU.
+ *   The max SIMD bitwidth value in EAL must also allow for the chosen algorithm.
  * @return
  *   - -EINVAL if the parameters are invalid.
  *   - -ENOTSUP requested algorithm is not supported by given platform.
-- 
2.22.0


  parent reply	other threads:[~2020-10-15 15:30 UTC|newest]

Thread overview: 276+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-07 15:58 [dpdk-dev] [PATCH 20.11 00/12] add max SIMD bitwidth to EAL Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 01/12] eal: add max SIMD bitwidth Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 02/12] eal: add default SIMD bitwidth values Ciara Power
2020-08-07 16:31   ` David Christensen
2020-08-07 16:59     ` David Christensen
2020-08-12 11:28     ` Power, Ciara
2020-08-10  5:22   ` Ruifeng Wang
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 03/12] net/i40e: add checks for max SIMD bitwidth Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 04/12] net/axgbe: " Ciara Power
2020-08-07 17:49   ` Somalapuram, Amaranath
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 05/12] net/bnxt: " Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 06/12] net/enic: " Ciara Power
2020-08-10  4:50   ` Hyong Youb Kim (hyonkim)
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 07/12] net/fm10k: " Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 08/12] net/iavf: " Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 09/12] net/ice: " Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 10/12] net/ixgbe: " Ciara Power
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 11/12] net/mlx5: " Ciara Power
2020-08-10 17:26   ` Alexander Kozyrev
2020-08-07 15:58 ` [dpdk-dev] [PATCH 20.11 12/12] net/virtio: " Ciara Power
2020-08-07 16:19 ` [dpdk-dev] [PATCH 20.11 00/12] add max SIMD bitwidth to EAL Stephen Hemminger
2020-08-10  9:52   ` Power, Ciara
2020-08-11  5:36 ` Honnappa Nagarahalli
2020-08-12 11:39   ` Power, Ciara
2020-08-27 16:12 ` [dpdk-dev] [PATCH v2 00/17] " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 01/17] eal: add max SIMD bitwidth Ciara Power
2020-09-04  5:30     ` Honnappa Nagarahalli
2020-09-04  8:45       ` Bruce Richardson
2020-09-09 19:30         ` Honnappa Nagarahalli
2020-09-17 16:31           ` Kinsella, Ray
2020-09-17 16:43             ` Bruce Richardson
2020-09-18  2:13             ` Honnappa Nagarahalli
2020-09-18  8:35               ` Bruce Richardson
2020-09-06 22:01     ` Ananyev, Konstantin
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 02/17] eal: add default SIMD bitwidth values Ciara Power
2020-09-04  5:30     ` Honnappa Nagarahalli
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 03/17] doc: add detail on using max SIMD bitwidth Ciara Power
2020-09-06 22:20     ` Ananyev, Konstantin
2020-09-07  8:44       ` Bruce Richardson
2020-09-07 12:01         ` Ananyev, Konstantin
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 04/17] net/i40e: add checks for " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 05/17] net/axgbe: " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 06/17] net/bnxt: " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 07/17] net/enic: " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 08/17] net/fm10k: " Ciara Power
2020-10-07  5:01     ` Wang, Xiao W
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 09/17] net/iavf: " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 10/17] net/ice: " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 11/17] net/ixgbe: " Ciara Power
2020-08-27 16:12   ` [dpdk-dev] [PATCH v2 12/17] net/mlx5: " Ciara Power
2020-08-27 16:13   ` [dpdk-dev] [PATCH v2 13/17] net/virtio: " Ciara Power
2020-08-31  2:39     ` Xia, Chenbo
2020-08-27 16:13   ` [dpdk-dev] [PATCH v2 14/17] distributor: " Ciara Power
2020-08-27 16:13   ` [dpdk-dev] [PATCH v2 15/17] member: " Ciara Power
2020-08-27 16:13   ` [dpdk-dev] [PATCH v2 16/17] efd: " Ciara Power
2020-08-27 16:13   ` [dpdk-dev] [PATCH v2 17/17] net: " Ciara Power
2020-09-02 11:02     ` Singh, Jasvinder
2020-09-30 13:03 ` [dpdk-dev] [PATCH v3 00/18] add max SIMD bitwidth to EAL Ciara Power
2020-09-30 13:03   ` [dpdk-dev] [PATCH v3 01/18] eal: add max SIMD bitwidth Ciara Power
2020-10-01 14:49     ` Coyle, David
2020-10-06  9:32     ` Olivier Matz
2020-10-07 10:47       ` Power, Ciara
2020-10-07 10:52         ` Bruce Richardson
2020-10-07 11:10           ` Power, Ciara
2020-10-07 11:18         ` Olivier Matz
2020-10-08  9:25           ` Power, Ciara
2020-10-08 10:04             ` Olivier Matz
2020-10-08 10:58               ` Power, Ciara
2020-10-08 11:48                 ` Bruce Richardson
2020-10-08 13:03                   ` Olivier Matz
2020-10-06 11:50     ` Maxime Coquelin
2020-10-07 10:58       ` Power, Ciara
2020-10-08 13:07     ` Ananyev, Konstantin
2020-10-08 13:14       ` Bruce Richardson
2020-10-08 14:07         ` Ananyev, Konstantin
2020-10-08 14:18           ` Bruce Richardson
2020-10-08 14:26             ` Power, Ciara
2020-10-08 13:19     ` Ananyev, Konstantin
2020-10-08 15:28     ` David Marchand
2020-09-30 13:03   ` [dpdk-dev] [PATCH v3 02/18] eal: add default SIMD bitwidth values Ciara Power
2020-10-05 19:35     ` David Christensen
2020-10-08 13:17     ` Ananyev, Konstantin
2020-10-08 16:45     ` David Marchand
2020-09-30 13:03   ` [dpdk-dev] [PATCH v3 03/18] doc: add detail on using max SIMD bitwidth Ciara Power
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 04/18] net/i40e: add checks for " Ciara Power
2020-10-08 15:21     ` Ananyev, Konstantin
2020-10-08 16:05       ` Power, Ciara
2020-10-08 16:14         ` Ananyev, Konstantin
2020-10-09  3:02     ` Guo, Jia
2020-10-09 14:02       ` Power, Ciara
2020-10-10  2:07         ` Guo, Jia
2020-10-12  9:37           ` Bruce Richardson
2020-10-13  2:15             ` Guo, Jia
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 05/18] net/axgbe: " Ciara Power
2020-09-30 13:29     ` Somalapuram, Amaranath
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 06/18] net/bnxt: " Ciara Power
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 07/18] net/enic: " Ciara Power
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 08/18] net/fm10k: " Ciara Power
2020-10-09  0:18     ` Zhang, Qi Z
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 09/18] net/iavf: " Ciara Power
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 10/18] net/ice: " Ciara Power
2020-10-09  0:04     ` Zhang, Qi Z
2020-10-09  1:05       ` Zhang, Qi Z
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 11/18] net/ixgbe: " Ciara Power
2020-10-08 15:05     ` Ananyev, Konstantin
2020-10-10 13:13     ` Wang, Haiyue
2020-10-11 22:31       ` Ananyev, Konstantin
2020-10-12  1:29         ` Wang, Haiyue
2020-10-12  9:09           ` Ananyev, Konstantin
2020-10-12 16:04             ` Wang, Haiyue
2020-10-12 16:24               ` Ananyev, Konstantin
2020-10-13  1:12                 ` Wang, Haiyue
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 12/18] net/mlx5: " Ciara Power
2020-10-05  6:30     ` Slava Ovsiienko
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 13/18] net/virtio: " Ciara Power
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 14/18] distributor: " Ciara Power
2020-10-06 12:17     ` David Hunt
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 15/18] member: " Ciara Power
2020-10-07  0:51     ` Wang, Yipeng1
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 16/18] efd: " Ciara Power
2020-10-07  0:51     ` Wang, Yipeng1
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 17/18] net: " Ciara Power
2020-09-30 15:03     ` Coyle, David
2020-09-30 15:49       ` Singh, Jasvinder
2020-10-01 14:16         ` Coyle, David
2020-10-01 14:19           ` Power, Ciara
2020-10-06 10:00             ` Olivier Matz
2020-10-07 11:16               ` Power, Ciara
2020-10-08 14:55               ` Ananyev, Konstantin
2020-10-13 11:27                 ` Power, Ciara
2020-10-06  9:58     ` Olivier Matz
2020-09-30 13:04   ` [dpdk-dev] [PATCH v3 18/18] lpm: choose vector path at runtime Ciara Power
2020-09-30 13:54     ` Medvedkin, Vladimir
2020-10-08 14:40       ` Ananyev, Konstantin
2020-10-09 14:31         ` Power, Ciara
2020-10-11 22:49           ` Ananyev, Konstantin
2020-10-08 15:19     ` David Marchand
2020-10-09 12:37       ` David Marchand
2020-10-13 10:38 ` [dpdk-dev] [PATCH v4 00/17] add max SIMD bitwidth to EAL Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 01/17] eal: add max SIMD bitwidth Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 02/17] doc: add detail on using " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 03/17] net/i40e: add checks for " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 04/17] net/axgbe: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 05/17] net/bnxt: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 06/17] net/enic: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 07/17] net/fm10k: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 08/17] net/iavf: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 09/17] net/ice: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 10/17] net/ixgbe: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 11/17] net/mlx5: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 12/17] net/virtio: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 13/17] distributor: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 14/17] member: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 15/17] efd: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 16/17] net: " Ciara Power
2020-10-13 10:38   ` [dpdk-dev] [PATCH v4 17/17] node: choose vector path at runtime Ciara Power
2020-10-13 11:04 ` [dpdk-dev] [PATCH v5 00/17] add max SIMD bitwidth to EAL Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 01/17] eal: add max SIMD bitwidth Ciara Power
2020-10-13 11:58     ` Ananyev, Konstantin
2020-10-14  8:50     ` Ruifeng Wang
2020-10-14 14:19       ` Honnappa Nagarahalli
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 02/17] doc: add detail on using " Ciara Power
2020-10-14  8:24     ` Ruifeng Wang
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 03/17] net/i40e: add checks for " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 04/17] net/axgbe: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 05/17] net/bnxt: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 06/17] net/enic: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 07/17] net/fm10k: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 08/17] net/iavf: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 09/17] net/ice: " Ciara Power
2020-10-13 12:11     ` Zhang, Qi Z
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 10/17] net/ixgbe: " Ciara Power
2020-10-13 11:20     ` Wang, Haiyue
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 11/17] net/mlx5: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 12/17] net/virtio: " Ciara Power
2020-10-14  2:02     ` Xia, Chenbo
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 13/17] distributor: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 14/17] member: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 15/17] efd: " Ciara Power
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 16/17] net: " Ciara Power
2020-10-13 11:32     ` Olivier Matz
2020-10-13 13:07     ` Ananyev, Konstantin
2020-10-13 13:25       ` Ananyev, Konstantin
2020-10-13 13:57         ` Ananyev, Konstantin
2020-10-13 11:04   ` [dpdk-dev] [PATCH v5 17/17] node: choose vector path at runtime Ciara Power
2020-10-13 13:42     ` Ananyev, Konstantin
2020-10-14 10:05       ` Jerin Jacob
2020-10-14  8:28     ` Ruifeng Wang
2020-10-15 10:37 ` [dpdk-dev] [PATCH v6 00/18] add max SIMD bitwidth to EAL Ciara Power
2020-10-15 10:37   ` [dpdk-dev] [PATCH v6 01/18] eal: add max SIMD bitwidth Ciara Power
2020-10-15 10:37   ` [dpdk-dev] [PATCH v6 02/18] doc: add detail on using " Ciara Power
2020-10-15 13:12     ` Kevin Laatz
2020-10-15 10:37   ` [dpdk-dev] [PATCH v6 03/18] net/i40e: add checks for " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 04/18] net/axgbe: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 05/18] net/bnxt: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 06/18] net/enic: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 07/18] net/fm10k: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 08/18] net/iavf: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 09/18] net/ice: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 10/18] net/ixgbe: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 11/18] net/mlx5: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 12/18] net/virtio: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 13/18] distributor: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 14/18] member: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 15/18] efd: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 16/18] net: " Ciara Power
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 17/18] node: choose vector path at runtime Ciara Power
2020-10-15 11:18     ` [dpdk-dev] [EXT] " Nithin Dabilpuram
2020-10-15 10:38   ` [dpdk-dev] [PATCH v6 18/18] acl: add checks for max SIMD bitwidth Ciara Power
2020-10-15 12:31     ` Ananyev, Konstantin
2020-10-15 15:22 ` [dpdk-dev] [PATCH v7 00/18] add max SIMD bitwidth to EAL Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 01/18] eal: add max SIMD bitwidth Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 02/18] doc: add detail on using " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 03/18] net/i40e: add checks for " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 04/18] net/axgbe: " Ciara Power
2020-10-15 15:27     ` Somalapuram, Amaranath
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 05/18] net/bnxt: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 06/18] net/enic: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 07/18] net/fm10k: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 08/18] net/iavf: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 09/18] net/ice: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 10/18] net/ixgbe: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 11/18] net/mlx5: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 12/18] net/virtio: " Ciara Power
2020-10-15 15:30     ` Maxime Coquelin
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 13/18] distributor: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 14/18] member: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 15/18] efd: " Ciara Power
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 16/18] net: " Ciara Power
2020-10-15 17:20     ` Singh, Jasvinder
2020-10-15 15:22   ` [dpdk-dev] [PATCH v7 17/18] node: choose vector path at runtime Ciara Power
2020-10-15 15:32     ` Power, Ciara
2020-10-15 15:22   ` Ciara Power [this message]
2020-10-16  8:13 ` [dpdk-dev] [PATCH v8 00/18] add max SIMD bitwidth to EAL Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 01/18] eal: add max SIMD bitwidth Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 02/18] doc: add detail on using " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 03/18] net/i40e: add checks for " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 04/18] net/axgbe: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 05/18] net/bnxt: " Ciara Power
2020-10-16  9:06     ` Somnath Kotur
2020-10-16  9:10       ` David Marchand
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 06/18] net/enic: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 07/18] net/fm10k: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 08/18] net/iavf: " Ciara Power
2020-10-16 10:16     ` Bruce Richardson
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 09/18] net/ice: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 10/18] net/ixgbe: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 11/18] net/mlx5: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 12/18] net/virtio: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 13/18] distributor: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 14/18] member: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 15/18] efd: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 16/18] net: " Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 17/18] node: choose vector path at runtime Ciara Power
2020-10-16  8:13   ` [dpdk-dev] [PATCH v8 18/18] acl: add checks for max SIMD bitwidth Ciara Power
2020-10-16  8:54     ` Ananyev, Konstantin
2020-10-16 14:27 ` [dpdk-dev] [PATCH v9 00/18] add max SIMD bitwidth to EAL Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 01/18] eal: add max SIMD bitwidth Ciara Power
2020-10-16 15:45     ` Kinsella, Ray
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 02/18] doc: add detail on using " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 03/18] net/i40e: add checks for " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 04/18] net/axgbe: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 05/18] net/bnxt: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 06/18] net/enic: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 07/18] net/fm10k: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 08/18] net/iavf: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 09/18] net/ice: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 10/18] net/ixgbe: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 11/18] net/mlx5: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 12/18] net/virtio: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 13/18] distributor: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 14/18] member: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 15/18] efd: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 16/18] net: " Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 17/18] node: choose vector path at runtime Ciara Power
2020-10-16 14:27   ` [dpdk-dev] [PATCH v9 18/18] acl: add checks for max SIMD bitwidth Ciara Power

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201015152259.97562-19-ciara.power@intel.com \
    --to=ciara.power@intel.com \
    --cc=bruce.richardson@intel.com \
    --cc=david.marchand@redhat.com \
    --cc=dev@dpdk.org \
    --cc=drc@linux.vnet.ibm.com \
    --cc=jerinj@marvell.com \
    --cc=konstantin.ananyev@intel.com \
    --cc=ruifeng.wang@arm.com \
    --cc=viktorin@rehivetech.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

DPDK patches and discussions

This inbox may be cloned and mirrored by anyone:

	git clone --mirror https://inbox.dpdk.org/dev/0 dev/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 dev dev/ https://inbox.dpdk.org/dev \
		dev@dpdk.org
	public-inbox-index dev

Example config snippet for mirrors.
Newsgroup available over NNTP:
	nntp://inbox.dpdk.org/inbox.dpdk.dev


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git