From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 72027A04DC; Mon, 19 Oct 2020 10:56:20 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1379BC8CC; Mon, 19 Oct 2020 10:53:04 +0200 (CEST) Received: from smtpbg501.qq.com (smtpbg501.qq.com [203.205.250.101]) by dpdk.org (Postfix) with ESMTP id 369E9C82C for ; Mon, 19 Oct 2020 10:52:48 +0200 (CEST) X-QQ-mid: bizesmtp6t1603097561tvzqkvoe7 Received: from localhost.localdomain.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Mon, 19 Oct 2020 16:52:41 +0800 (CST) X-QQ-SSF: 01400000002000C0C000B00A0000000 X-QQ-FEAT: VGEHthcaPSSQZRYi8sTP67hzjHTw4PGY6tSG+fNCFF5HwOYm21nrpVXnnfHDR 9+p1+JOvWk3XlT5adpimvA7gRQMxJ3spaCMPKAO007NRvTZC43p0K4ELBod+5juHpiPeDqF Rdo4YBvLz8AJ9ZX3iToIaXkU+0E4J7XFBeZTlQ+4W69NBpfq9Mnu4A/i6jFDGCSNsc1+nxE z3x3ECMBIGzxdosY7KE8LQqqlnI7wDApYFtr06gVzXjYd6DAOXq3FIo23pq+ZbMfYcQx+7v 9g5BtCglffKx34V4mcExx1awuzSNJlE4tpdTyx31MQk67KkOfIoayJM7/jO8c2MjGJzU9wb ZKL7l8s2iPtD9Mj7Jwdi/BZQmE8Xg== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Date: Mon, 19 Oct 2020 16:53:28 +0800 Message-Id: <20201019085415.82207-12-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20201019085415.82207-1-jiawenwu@trustnetic.com> References: <20201019085415.82207-1-jiawenwu@trustnetic.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH v4 11/58] net/txgbe: add PHY reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add phy reset function, support read and write phy registers. Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_hw.c | 5 + drivers/net/txgbe/base/txgbe_phy.c | 226 +++++++++++++++++++++++++++++ drivers/net/txgbe/base/txgbe_phy.h | 10 ++ 3 files changed, 241 insertions(+) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index d2d12a929..598ef3e99 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -291,10 +291,15 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) /* PHY */ phy->identify = txgbe_identify_phy; phy->init = txgbe_init_phy_raptor; + phy->read_reg = txgbe_read_phy_reg; + phy->write_reg = txgbe_write_phy_reg; + phy->read_reg_mdi = txgbe_read_phy_reg_mdi; + phy->write_reg_mdi = txgbe_write_phy_reg_mdi; phy->read_i2c_byte = txgbe_read_i2c_byte; phy->write_i2c_byte = txgbe_write_i2c_byte; phy->read_i2c_eeprom = txgbe_read_i2c_eeprom; phy->write_i2c_eeprom = txgbe_write_i2c_eeprom; + phy->reset = txgbe_reset_phy; /* MAC */ mac->init_hw = txgbe_init_hw; diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index b36bffcac..347641ce9 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -111,6 +111,30 @@ s32 txgbe_identify_phy(struct txgbe_hw *hw) return err; } +/** + * txgbe_check_reset_blocked - check status of MNG FW veto bit + * @hw: pointer to the hardware structure + * + * This function checks the STAT.MNGVETO bit to see if there are + * any constraints on link from manageability. For MAC's that don't + * have this bit just return faluse since the link can not be blocked + * via this method. + **/ +s32 txgbe_check_reset_blocked(struct txgbe_hw *hw) +{ + u32 mmngc; + + DEBUGFUNC("txgbe_check_reset_blocked"); + + mmngc = rd32(hw, TXGBE_STAT); + if (mmngc & TXGBE_STAT_MNGVETO) { + DEBUGOUT("MNG_VETO bit detected.\n"); + return true; + } + + return false; +} + /** * txgbe_validate_phy_addr - Determines phy address is valid * @hw: pointer to hardware structure @@ -199,6 +223,208 @@ enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id) return phy_type; } +static s32 +txgbe_reset_extphy(struct txgbe_hw *hw) +{ + u16 ctrl = 0; + int err, i; + + err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, + TXGBE_MD_DEV_GENERAL, &ctrl); + if (err != 0) + return err; + ctrl |= TXGBE_MD_PORT_CTRL_RESET; + err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL, + TXGBE_MD_DEV_GENERAL, ctrl); + if (err != 0) + return err; + + /* + * Poll for reset bit to self-clear indicating reset is complete. + * Some PHYs could take up to 3 seconds to complete and need about + * 1.7 usec delay after the reset is complete. + */ + for (i = 0; i < 30; i++) { + msec_delay(100); + err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL, + TXGBE_MD_DEV_GENERAL, &ctrl); + if (err != 0) + return err; + + if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) { + usec_delay(2); + break; + } + } + + if (ctrl & TXGBE_MD_PORT_CTRL_RESET) { + err = TXGBE_ERR_RESET_FAILED; + DEBUGOUT("PHY reset polling failed to complete.\n"); + } + + return err; +} + +/** + * txgbe_reset_phy - Performs a PHY reset + * @hw: pointer to hardware structure + **/ +s32 txgbe_reset_phy(struct txgbe_hw *hw) +{ + s32 err = 0; + + DEBUGFUNC("txgbe_reset_phy"); + + if (hw->phy.type == txgbe_phy_unknown) + err = txgbe_identify_phy(hw); + + if (err != 0 || hw->phy.type == txgbe_phy_none) + return err; + + /* Don't reset PHY if it's shut down due to overtemp. */ + if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP) + return err; + + /* Blocked by MNG FW so bail */ + if (txgbe_check_reset_blocked(hw)) + return err; + + switch (hw->phy.type) { + case txgbe_phy_cu_mtd: + err = txgbe_reset_extphy(hw); + break; + default: + break; + } + + return err; +} + +/** + * txgbe_read_phy_mdi - Reads a value from a specified PHY register without + * the SWFW lock + * @hw: pointer to hardware structure + * @reg_addr: 32 bit address of PHY register to read + * @device_type: 5 bit device type + * @phy_data: Pointer to read data from PHY register + **/ +s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, + u16 *phy_data) +{ + u32 command, data; + + /* Setup and write the address cycle command */ + command = TXGBE_MDIOSCA_REG(reg_addr) | + TXGBE_MDIOSCA_DEV(device_type) | + TXGBE_MDIOSCA_PORT(hw->phy.addr); + wr32(hw, TXGBE_MDIOSCA, command); + + command = TXGBE_MDIOSCD_CMD_READ | + TXGBE_MDIOSCD_BUSY; + wr32(hw, TXGBE_MDIOSCD, command); + + /* + * Check every 10 usec to see if the address cycle completed. + * The MDI Command bit will clear when the operation is + * complete + */ + if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY, + 0, NULL, 100, 100)) { + DEBUGOUT("PHY address command did not complete\n"); + return TXGBE_ERR_PHY; + } + + data = rd32(hw, TXGBE_MDIOSCD); + *phy_data = (u16)TXGBD_MDIOSCD_DAT(data); + + return 0; +} + +/** + * txgbe_read_phy_reg - Reads a value from a specified PHY register + * using the SWFW lock - this function is needed in most cases + * @hw: pointer to hardware structure + * @reg_addr: 32 bit address of PHY register to read + * @device_type: 5 bit device type + * @phy_data: Pointer to read data from PHY register + **/ +s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr, + u32 device_type, u16 *phy_data) +{ + s32 err; + u32 gssr = hw->phy.phy_semaphore_mask; + + DEBUGFUNC("txgbe_read_phy_reg"); + + if (hw->mac.acquire_swfw_sync(hw, gssr)) + return TXGBE_ERR_SWFW_SYNC; + + err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data); + + hw->mac.release_swfw_sync(hw, gssr); + + return err; +} + +/** + * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register + * without SWFW lock + * @hw: pointer to hardware structure + * @reg_addr: 32 bit PHY register to write + * @device_type: 5 bit device type + * @phy_data: Data to write to the PHY register + **/ +s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, + u32 device_type, u16 phy_data) +{ + u32 command; + + /* write command */ + command = TXGBE_MDIOSCA_REG(reg_addr) | + TXGBE_MDIOSCA_DEV(device_type) | + TXGBE_MDIOSCA_PORT(hw->phy.addr); + wr32(hw, TXGBE_MDIOSCA, command); + + command = TXGBE_MDIOSCD_CMD_WRITE | + TXGBE_MDIOSCD_DAT(phy_data) | + TXGBE_MDIOSCD_BUSY; + wr32(hw, TXGBE_MDIOSCD, command); + + /* wait for completion */ + if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY, + 0, NULL, 100, 100)) { + TLOG_DEBUG("PHY write cmd didn't complete\n"); + return -TERR_PHY; + } + + return 0; +} + +/** + * txgbe_write_phy_reg - Writes a value to specified PHY register + * using SWFW lock- this function is needed in most cases + * @hw: pointer to hardware structure + * @reg_addr: 32 bit PHY register to write + * @device_type: 5 bit device type + * @phy_data: Data to write to the PHY register + **/ +s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr, + u32 device_type, u16 phy_data) +{ + s32 err; + u32 gssr = hw->phy.phy_semaphore_mask; + + DEBUGFUNC("txgbe_write_phy_reg"); + + if (hw->mac.acquire_swfw_sync(hw, gssr)) + err = TXGBE_ERR_SWFW_SYNC; + + err = hw->phy.write_reg_mdi(hw, reg_addr, device_type, + phy_data); + hw->mac.release_swfw_sync(hw, gssr); + + return err; +} /** * txgbe_identify_module - Identifies module type * @hw: pointer to hardware structure diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h index 3c3f2914a..750934e06 100644 --- a/drivers/net/txgbe/base/txgbe_phy.h +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -327,6 +327,16 @@ bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr); enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id); s32 txgbe_get_phy_id(struct txgbe_hw *hw); s32 txgbe_identify_phy(struct txgbe_hw *hw); +s32 txgbe_reset_phy(struct txgbe_hw *hw); +s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, + u16 *phy_data); +s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type, + u16 phy_data); +s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr, + u32 device_type, u16 *phy_data); +s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr, + u32 device_type, u16 phy_data); +s32 txgbe_check_reset_blocked(struct txgbe_hw *hw); /* PHY specific */ s32 txgbe_identify_module(struct txgbe_hw *hw); -- 2.18.4