From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5079A04DD; Fri, 23 Oct 2020 00:08:16 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3F8E672E5; Fri, 23 Oct 2020 00:06:30 +0200 (CEST) Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by dpdk.org (Postfix) with ESMTP id E2A2B7F6C for ; Fri, 23 Oct 2020 00:06:24 +0200 (CEST) Received: by mail-pg1-f169.google.com with SMTP id j7so1870602pgk.5 for ; Thu, 22 Oct 2020 15:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=rjZgvmZ7ABox95cB6cI2ZmGoVvkrp/J0mibaUewJwPU=; b=a2xF5w/9jJPHjYRtwUYt7pldBzIA8VayOjVwVd+xXugTk1gxNENdvCcH9eicrr/yXx 0cDxYZQ5TuCrWEdh3O45RT1RRP7gE3gntNnoxaSvi4CxqknGGvsQ8WzJ+PSrlSgIc+Yb hWwA1j0mOYH1J/MXHUezz8WO03BmjsaiyLwvw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=rjZgvmZ7ABox95cB6cI2ZmGoVvkrp/J0mibaUewJwPU=; b=rUf6l5u5zYjBZJ4nzOHJSl5uubMLit7fKgL5M0j4tfGKTT81MPmNVS/gvkvlvcjccf 8lT24keLsJmlbjc83Pzjq9oyEUtAAdPE7sbadsnhU02ho4CD3nyEDnyQ2aWybUY8i5Qh pP6tKZDe2fwHyk1T1YZG1Yu6YLOszDGq0fmrp1fIIYZdo5y/pZz5gGmMt2KeGENzq4m7 b9DfD+w0UwtdKxlIP/V45YRH6OaRXx6Ao7rLIhtytzcMbGMt5Pt2XYKNtUBSCI5g6W/s UKkmnlaetOI3/GTYc1hkm5ZloMdwJRd4ok2Ri60z1E2BbSASri5SxcAESOBiD7V8x7Dg Wemg== X-Gm-Message-State: AOAM530Y9Cf69NRExKLTC/1VU4dysBfsCE0efNQhNaofpVw1ZG55ebto IsAAbdOdDjzs4yMOx6GrEOYnzmas0eygAl7MZ9Lx3RFWVi9LtBJhICtOIEZNL52WYB3gedEEYzC 6GKswHelgtck7PPvJuxZuZTN49u9xjPfeyB5E61Uup57Wqm0RG2xSqdT+xtBKQtC3ZQ== X-Google-Smtp-Source: ABdhPJxnnm2KS0TQuJJ8OrLch05BWmVABJhsFwiofML2neRdLs0iWmL32LZ/xMsbwlOhrBGxG7MfQQ== X-Received: by 2002:a17:90a:3486:: with SMTP id p6mr4454732pjb.23.1603404382423; Thu, 22 Oct 2020 15:06:22 -0700 (PDT) Received: from localhost.localdomain ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id q14sm3214059pjp.43.2020.10.22.15.06.21 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Oct 2020 15:06:21 -0700 (PDT) From: Ajit Khaparde To: dev@dpdk.org Cc: Peter Spreadborough , Jay Ding , Farah Smith Date: Thu, 22 Oct 2020 15:05:33 -0700 Message-Id: <20201022220542.84166-2-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20201020215538.59242-1-ajit.khaparde@broadcom.com> References: <20201020215538.59242-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8bit X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: [dpdk-dev] [PATCH v3 01/11] net/bnxt: add stingray support to core layer X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Peter Spreadborough - Moved P4 specific code under the P4 directory - Added P45 skeleton code for SR to build on - Add SR support in TRUFLOW core layer. The TRUFLOW core or the tf-core is a shim layer which communicates with the CFA block in the hardware. Signed-off-by: Peter Spreadborough Signed-off-by: Jay Ding Reviewed-by: Farah Smith Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/hcapi/hcapi_cfa.h | 39 +++++-- drivers/net/bnxt/tf_core/cfa_resource_types.h | 84 +++++--------- drivers/net/bnxt/tf_core/tf_core.c | 3 +- drivers/net/bnxt/tf_core/tf_core.h | 2 +- drivers/net/bnxt/tf_core/tf_device.c | 9 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 25 ++++- drivers/net/bnxt/tf_core/tf_device_p4.h | 6 + drivers/net/bnxt/tf_core/tf_device_p45.h | 105 ++++++++++++++++++ drivers/net/bnxt/tf_core/tf_em.h | 6 - 9 files changed, 198 insertions(+), 81 deletions(-) create mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa.h b/drivers/net/bnxt/hcapi/hcapi_cfa.h index c7d87dec73..aa218d714d 100644 --- a/drivers/net/bnxt/hcapi/hcapi_cfa.h +++ b/drivers/net/bnxt/hcapi/hcapi_cfa.h @@ -14,7 +14,15 @@ #include "hcapi_cfa_defs.h" +#if CHIP_CFG == SR_A +#define SUPPORT_CFA_HW_P45 1 +#undef SUPPORT_CFA_HW_P4 +#define SUPPORT_CFA_HW_P4 0 +#elif CHIP_CFG == CMB_A #define SUPPORT_CFA_HW_P4 1 +#else +#error "Chip not supported" +#endif #if SUPPORT_CFA_HW_P4 && SUPPORT_CFA_HW_P58 && SUPPORT_CFA_HW_P59 #define SUPPORT_CFA_HW_ALL 1 @@ -81,17 +89,20 @@ struct hcapi_cfa_key_result { /* common CFA register access macros */ #define CFA_REG(x) OFFSETOF(cfa_reg_t, cfa_##x) -#ifndef REG_WR -#define REG_WR(_p, x, y) (*((uint32_t volatile *)(x)) = (y)) +#ifndef TF_REG_WR +#define TF_REG_WR(_p, x, y) (*((uint32_t volatile *)(x)) = (y)) #endif -#ifndef REG_RD -#define REG_RD(_p, x) (*((uint32_t volatile *)(x))) +#ifndef TF_REG_RD +#define TF_REG_RD(_p, x) (*((uint32_t volatile *)(x))) +#endif +#ifndef TF_CFA_REG_RD +#define TF_CFA_REG_RD(_p, x) \ + TF_REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x)) +#endif +#ifndef TF_CFA_REG_WR +#define TF_CFA_REG_WR(_p, x, y) \ + TF_REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y) #endif -#define CFA_REG_RD(_p, x) \ - REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x)) -#define CFA_REG_WR(_p, x, y) \ - REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y) - /* Constants used by Resource Manager Registration*/ #define RM_CLIENT_NAME_MAX_LEN 32 @@ -248,7 +259,15 @@ int hcapi_cfa_p4_mirror_hwop(struct hcapi_cfa_hwop *op, int hcapi_cfa_p4_global_cfg_hwop(struct hcapi_cfa_hwop *op, uint32_t type, struct hcapi_cfa_data *config); -#endif /* SUPPORT_CFA_HW_P4 */ +/* SUPPORT_CFA_HW_P4 */ +#elif SUPPORT_CFA_HW_P45 +int hcapi_cfa_p45_mirror_hwop(struct hcapi_cfa_hwop *op, + struct hcapi_cfa_data *mirror); +int hcapi_cfa_p45_global_cfg_hwop(struct hcapi_cfa_hwop *op, + uint32_t type, + struct hcapi_cfa_data *config); +/* SUPPORT_CFA_HW_P45 */ +#endif /** * HCAPI CFA device HW operation function callback definition * This is standardized function callback hook to install different diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h index 19838c393d..412204f7ed 100644 --- a/drivers/net/bnxt/tf_core/cfa_resource_types.h +++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019-2020 Broadcom + * Copyright(c) 2014-2018 Broadcom * All rights reserved. */ @@ -64,79 +64,47 @@ #define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM -/* Multicast Group */ -#define CFA_RESOURCE_TYPE_P58_MCG 0x0UL -/* Encap 8 byte record */ -#define CFA_RESOURCE_TYPE_P58_ENCAP_8B 0x1UL -/* Encap 16 byte record */ -#define CFA_RESOURCE_TYPE_P58_ENCAP_16B 0x2UL -/* Encap 64 byte record */ -#define CFA_RESOURCE_TYPE_P58_ENCAP_64B 0x3UL -/* Source Property MAC */ -#define CFA_RESOURCE_TYPE_P58_SP_MAC 0x4UL -/* Source Property MAC and IPv4 */ -#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV4 0x5UL -/* Source Property MAC and IPv6 */ -#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV6 0x6UL -/* Network Address Translation Port */ -#define CFA_RESOURCE_TYPE_P58_NAT_PORT 0x7UL -/* Network Address Translation IPv4 address */ -#define CFA_RESOURCE_TYPE_P58_NAT_IPV4 0x8UL /* Meter */ -#define CFA_RESOURCE_TYPE_P58_METER 0x9UL -/* Flow State */ -#define CFA_RESOURCE_TYPE_P58_FLOW_STATE 0xaUL -/* Full Action Records */ -#define CFA_RESOURCE_TYPE_P58_FULL_ACTION 0xbUL -/* Action Record Format 0 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_0_ACTION 0xcUL -/* Action Record Ext Format 0 */ -#define CFA_RESOURCE_TYPE_P58_EXT_FORMAT_0_ACTION 0xdUL -/* Action Record Format 1 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_1_ACTION 0xeUL -/* Action Record Format 2 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_2_ACTION 0xfUL -/* Action Record Format 3 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_3_ACTION 0x10UL -/* Action Record Format 4 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_4_ACTION 0x11UL -/* Action Record Format 5 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_5_ACTION 0x12UL -/* Action Record Format 6 */ -#define CFA_RESOURCE_TYPE_P58_FORMAT_6_ACTION 0x13UL +#define CFA_RESOURCE_TYPE_P58_METER 0x0UL +/* SRAM_Bank_0 */ +#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_0 0x1UL +/* SRAM_Bank_1 */ +#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_1 0x2UL +/* SRAM_Bank_2 */ +#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_2 0x3UL +/* SRAM_Bank_3 */ +#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 0x4UL /* L2 Context TCAM High priority entries */ -#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH 0x14UL +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH 0x5UL /* L2 Context TCAM Low priority entries */ -#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW 0x15UL +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW 0x6UL /* L2 Context REMAP high priority entries */ -#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x16UL +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x7UL /* L2 Context REMAP Low priority entries */ -#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW 0x17UL +#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW 0x8UL /* Profile Func */ -#define CFA_RESOURCE_TYPE_P58_PROF_FUNC 0x18UL +#define CFA_RESOURCE_TYPE_P58_PROF_FUNC 0x9UL /* Profile TCAM */ -#define CFA_RESOURCE_TYPE_P58_PROF_TCAM 0x19UL +#define CFA_RESOURCE_TYPE_P58_PROF_TCAM 0xaUL /* Exact Match Profile Id */ -#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID 0x1aUL +#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID 0xbUL /* Wildcard Profile Id */ -#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID 0x1bUL +#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID 0xcUL /* Exact Match Record */ -#define CFA_RESOURCE_TYPE_P58_EM_REC 0x1cUL +#define CFA_RESOURCE_TYPE_P58_EM_REC 0xdUL /* Wildcard TCAM */ -#define CFA_RESOURCE_TYPE_P58_WC_TCAM 0x1dUL +#define CFA_RESOURCE_TYPE_P58_WC_TCAM 0xeUL /* Meter profile */ -#define CFA_RESOURCE_TYPE_P58_METER_PROF 0x1eUL +#define CFA_RESOURCE_TYPE_P58_METER_PROF 0xfUL /* Meter */ -#define CFA_RESOURCE_TYPE_P58_MIRROR 0x1fUL -/* Source Property TCAM */ -#define CFA_RESOURCE_TYPE_P58_SP_TCAM 0x20UL +#define CFA_RESOURCE_TYPE_P58_MIRROR 0x10UL /* Exact Match Flexible Key Builder */ -#define CFA_RESOURCE_TYPE_P58_EM_FKB 0x21UL +#define CFA_RESOURCE_TYPE_P58_EM_FKB 0x11UL /* Wildcard Flexible Key Builder */ -#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x22UL +#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL /* VEB TCAM */ -#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x23UL -#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_VEB_TCAM +#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL +#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_VEB_TCAM /* Multicast Group */ diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c index 0dbde1de2d..788335b814 100644 --- a/drivers/net/bnxt/tf_core/tf_core.c +++ b/drivers/net/bnxt/tf_core/tf_core.c @@ -34,7 +34,8 @@ tf_open_session(struct tf *tfp, * side. It is assumed that the Firmware will be supported if * firmware open session succeeds. */ - if (parms->device_type != TF_DEVICE_TYPE_WH) { + if (parms->device_type != TF_DEVICE_TYPE_WH && + parms->device_type != TF_DEVICE_TYPE_SR) { TFP_DRV_LOG(ERR, "Unsupported device type %d\n", parms->device_type); diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h index db1093515c..65be8f54a4 100644 --- a/drivers/net/bnxt/tf_core/tf_core.h +++ b/drivers/net/bnxt/tf_core/tf_core.h @@ -10,7 +10,7 @@ #include #include #include -#include "hcapi/hcapi_cfa.h" +#include "hcapi/hcapi_cfa_defs.h" #include "tf_project.h" /** diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 1129440955..8389828018 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -47,7 +47,6 @@ tf_dev_bind_p4(struct tf *tfp, struct tf_if_tbl_cfg_parms if_tbl_cfg; struct tf_global_cfg_cfg_parms global_cfg; - dev_handle->type = TF_DEVICE_TYPE_WH; /* Initial function initialization */ dev_handle->ops = &tf_dev_ops_p4_init; @@ -90,7 +89,10 @@ tf_dev_bind_p4(struct tf *tfp, * EEM */ em_cfg.num_elements = TF_EM_TBL_TYPE_MAX; - em_cfg.cfg = tf_em_ext_p4; + if (dev_handle->type == TF_DEVICE_TYPE_WH) + em_cfg.cfg = tf_em_ext_p4; + else + em_cfg.cfg = tf_em_ext_p45; em_cfg.resources = resources; em_cfg.mem_type = TF_EEM_MEM_TYPE_HOST; rc = tf_em_ext_common_bind(tfp, &em_cfg); @@ -241,6 +243,8 @@ tf_dev_bind(struct tf *tfp __rte_unused, { switch (type) { case TF_DEVICE_TYPE_WH: + case TF_DEVICE_TYPE_SR: + dev_handle->type = type; return tf_dev_bind_p4(tfp, shadow_copy, resources, @@ -258,6 +262,7 @@ tf_dev_unbind(struct tf *tfp, { switch (dev_handle->type) { case TF_DEVICE_TYPE_WH: + case TF_DEVICE_TYPE_SR: return tf_dev_unbind_p4(tfp); default: TFP_DRV_LOG(ERR, diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index fe8dec3af7..0344565d72 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -28,13 +28,32 @@ * - (-EINVAL) on failure. */ static int -tf_dev_p4_get_max_types(struct tf *tfp __rte_unused, +tf_dev_p4_get_max_types(struct tf *tfp, uint16_t *max_types) { - if (max_types == NULL) + struct tf_session *tfs; + struct tf_dev_info *dev; + int rc; + + if (max_types == NULL || tfp == NULL) return -EINVAL; - *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1; + /* Retrieve the session information */ + rc = tf_session_get_session(tfp, &tfs); + if (rc) + return rc; + + /* Retrieve the device information */ + rc = tf_session_get_device(tfs, &dev); + if (rc) + return rc; + + if (dev->type == TF_DEVICE_TYPE_WH) + *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1; + else if (dev->type == TF_DEVICE_TYPE_SR) + *max_types = CFA_RESOURCE_TYPE_P45_LAST + 1; + else + return -ENODEV; return 0; } diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index 7e58469a09..aba28fe5f6 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -83,6 +83,12 @@ struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE }, }; +struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = { + /* CFA_RESOURCE_TYPE_P4_EM_REC */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE }, +}; + struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC }, /* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */ diff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h new file mode 100644 index 0000000000..016d6e254e --- /dev/null +++ b/drivers/net/bnxt/tf_core/tf_device_p45.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019-2020 Broadcom + * All rights reserved. + */ + +#ifndef _TF_DEVICE_P45_H_ +#define _TF_DEVICE_P45_H_ + +#include + +#include "tf_core.h" +#include "tf_rm.h" +#include "tf_if_tbl.h" +#include "tf_global_cfg.h" + +struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID }, + /* CFA_RESOURCE_TYPE_P45_L2_FUNC */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } +}; + +struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM }, + /* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_VEB_TCAM */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } +}; + +struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B }, + /* CFA_RESOURCE_TYPE_P45_ENCAP_32B */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR }, + /* CFA_RESOURCE_TYPE_P45_UPAR */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_EPOC */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_METADATA */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_CT_STATE */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_RANGE_PROF */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_LAG */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_EM_FBK */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_WC_FKB */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + /* CFA_RESOURCE_TYPE_P45_EXT */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID } +}; + +struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { + /* CFA_RESOURCE_TYPE_P45_EM_REC */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, + { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE }, +}; + +struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = { + { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC }, + /* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */ + { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }, +}; + +struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = { + { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT }, + { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR }, + { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR }, + { TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR }, + { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }, + { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID } +}; + +struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = { + { TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP }, + { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK }, +}; +#endif /* _TF_DEVICE_P45_H_ */ diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h index 2a67e47607..51b08138ea 100644 --- a/drivers/net/bnxt/tf_core/tf_em.h +++ b/drivers/net/bnxt/tf_core/tf_em.h @@ -9,12 +9,6 @@ #include "tf_core.h" #include "tf_session.h" - -#define SUPPORT_CFA_HW_P4 1 -#define SUPPORT_CFA_HW_P58 0 -#define SUPPORT_CFA_HW_P59 0 -#define SUPPORT_CFA_HW_ALL 0 - #include "hcapi/hcapi_cfa_defs.h" #define TF_EM_MIN_ENTRIES (1 << 15) /* 32K */ -- 2.21.1 (Apple Git-122.3)