From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EC6BA04B5; Sun, 25 Oct 2020 02:26:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 982461E35; Sun, 25 Oct 2020 02:26:06 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 23F3E106B for ; Sun, 25 Oct 2020 02:26:02 +0200 (CEST) IronPort-SDR: Q87XHbX5F7mtc/MmRMWb1RVy3okmo99Q3fGi9bsvXA2VCBl1+xIWKfihqVlVVI0knp6+7nq9pU Lvsn5ftDiqTQ== X-IronPort-AV: E=McAfee;i="6000,8403,9784"; a="167927026" X-IronPort-AV: E=Sophos;i="5.77,414,1596524400"; d="scan'208";a="167927026" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2020 17:26:01 -0700 IronPort-SDR: jKVttwV+sq/dyiPLUdaS5uoCfevV9Bxt/8lmLGnhUtlq6NXF2GgMIgWIlzzxt2psVyjltKIzZt X1yCUrUMm+DQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,414,1596524400"; d="scan'208";a="359984002" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by FMSMGA003.fm.intel.com with ESMTP; 24 Oct 2020 17:26:00 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Amir Shay Date: Sun, 25 Oct 2020 08:29:34 +0800 Message-Id: <20201025002953.1680999-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20201025002953.1680999-1-qi.z.zhang@intel.com> References: <20201025002953.1680999-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v2 02/21] net/ice/base: add NVM Write Response flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added NVM Write Admin Command (0x703) ARQ response flags - as returned in "Response flags" field. Three flags are supported: POR, PERST and EMPR. All indicate the type of reset required to get the NVM bank update effective. Signed-off-by: Amir Shay Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index bc71ec5317..9db50de11c 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1654,6 +1654,9 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) #define ICE_AQC_NVM_FLASH_ONLY BIT(7) +#define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ +#define ICE_AQC_NVM_PERST_FLAG 1 +#define ICE_AQC_NVM_EMPR_FLAG 2 __le16 module_typeid; __le16 length; #define ICE_AQC_NVM_ERASE_LEN 0xFFFF -- 2.25.4