[dpdk-dev] [PATCH 4/4] common/cpt: remove redundant structure

[Archana Muniganti <marchana@marvell.com>]

Replaced structure 'rid' which has single field with its
field itself.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
---
 drivers/common/cpt/cpt_common.h                   |  7 +------
 drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 10 +++++-----
 drivers/crypto/octeontx/otx_cryptodev_ops.c       | 13 +++++++------
 drivers/crypto/octeontx2/otx2_cryptodev_ops.c     | 13 ++++++-------
 4 files changed, 19 insertions(+), 24 deletions(-)

diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h
index f61495e458..7fea0ca879 100644
--- a/drivers/common/cpt/cpt_common.h
+++ b/drivers/common/cpt/cpt_common.h
@@ -27,11 +27,6 @@ struct cpt_qp_meta_info {
 	int lb_mlen;
 };
 
-struct rid {
-	/** Request id of a crypto operation */
-	uintptr_t rid;
-};
-
 /*
  * Pending queue structure
  *
@@ -40,7 +35,7 @@ struct pending_queue {
 	/** Pending requests count */
 	uint64_t pending_count;
 	/** Array of pending requests */
-	struct rid *rid_queue;
+	uintptr_t *req_queue;
 	/** Tail of queue to be used for enqueue */
 	uint16_t enq_tail;
 	/** Head of queue to be used for dequeue */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
index ce546c2ffe..c6b1a5197d 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c
@@ -535,7 +535,7 @@ otx_cpt_get_resource(const struct rte_cryptodev *dev, uint8_t group,
 	len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);
 
 	/* For pending queue */
-	len += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	len += qlen * sizeof(uintptr_t);
 
 	/* So that instruction queues start as pg size aligned */
 	len = RTE_ALIGN(len, pg_sz);
@@ -570,14 +570,14 @@ otx_cpt_get_resource(const struct rte_cryptodev *dev, uint8_t group,
 	}
 
 	/* Pending queue setup */
-	cptvf->pqueue.rid_queue = (struct rid *)mem;
+	cptvf->pqueue.req_queue = (uintptr_t *)mem;
 	cptvf->pqueue.enq_tail = 0;
 	cptvf->pqueue.deq_head = 0;
 	cptvf->pqueue.pending_count = 0;
 
-	mem +=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
-	len -=  qlen * RTE_ALIGN(sizeof(struct rid), 8);
-	dma_addr += qlen * RTE_ALIGN(sizeof(struct rid), 8);
+	mem +=  qlen * sizeof(uintptr_t);
+	len -=  qlen * sizeof(uintptr_t);
+	dma_addr += qlen * sizeof(uintptr_t);
 
 	/* Alignment wastage */
 	used_len = alloc_len - len;
diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c
index 0a0c50a363..9f731f8cc9 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c
@@ -430,7 +430,7 @@ otx_cpt_request_enqueue(struct cpt_instance *instance,
 	/* Default mode of software queue */
 	mark_cpt_inst(instance);
 
-	pqueue->rid_queue[pqueue->enq_tail].rid = (uintptr_t)user_req;
+	pqueue->req_queue[pqueue->enq_tail] = (uintptr_t)user_req;
 
 	/* We will use soft queue length here to limit requests */
 	MOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);
@@ -823,7 +823,6 @@ otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,
 	struct cpt_instance *instance = (struct cpt_instance *)qptr;
 	struct cpt_request_info *user_req;
 	struct cpt_vf *cptvf = (struct cpt_vf *)instance;
-	struct rid *rid_e;
 	uint8_t cc[nb_ops];
 	int i, count, pcount;
 	uint8_t ret;
@@ -837,11 +836,13 @@ otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops,
 	count = (nb_ops > pcount) ? pcount : nb_ops;
 
 	for (i = 0; i < count; i++) {
-		rid_e = &pqueue->rid_queue[pqueue->deq_head];
-		user_req = (struct cpt_request_info *)(rid_e->rid);
+		user_req = (struct cpt_request_info *)
+				pqueue->req_queue[pqueue->deq_head];
 
-		if (likely((i+1) < count))
-			rte_prefetch_non_temporal((void *)rid_e[1].rid);
+		if (likely((i+1) < count)) {
+			rte_prefetch_non_temporal(
+				(void *)pqueue->req_queue[i+1]);
+		}
 
 		ret = check_nb_command_id(user_req, instance);
 
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
index fe76fe38c2..c337398242 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -192,7 +192,7 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
 	size_div40 = (iq_len + 40 - 1) / 40 + 1;
 
 	/* For pending queue */
-	len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
+	len = iq_len * sizeof(uintptr_t);
 
 	/* Space for instruction group memory */
 	len += size_div40 * 16;
@@ -229,12 +229,12 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
 	}
 
 	/* Initialize pending queue */
-	qp->pend_q.rid_queue = (struct rid *)va;
+	qp->pend_q.req_queue = (uintptr_t *)va;
 	qp->pend_q.enq_tail = 0;
 	qp->pend_q.deq_head = 0;
 	qp->pend_q.pending_count = 0;
 
-	used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
+	used_len = iq_len * sizeof(uintptr_t);
 	used_len += size_div40 * 16;
 	used_len = RTE_ALIGN(used_len, pg_sz);
 	iova += used_len;
@@ -520,7 +520,7 @@ otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
 		lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
 	} while (lmt_status == 0);
 
-	pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
+	pend_q->req_queue[pend_q->enq_tail] = (uintptr_t)req;
 
 	/* We will use soft queue length here to limit requests */
 	MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
@@ -977,7 +977,6 @@ otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 	struct cpt_request_info *req;
 	struct rte_crypto_op *cop;
 	uint8_t cc[nb_ops];
-	struct rid *rid;
 	uintptr_t *rsp;
 	void *metabuf;
 
@@ -989,8 +988,8 @@ otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 		nb_ops = nb_pending;
 
 	for (i = 0; i < nb_ops; i++) {
-		rid = &pend_q->rid_queue[pend_q->deq_head];
-		req = (struct cpt_request_info *)(rid->rid);
+		req = (struct cpt_request_info *)
+				pend_q->req_queue[pend_q->deq_head];
 
 		cc[i] = otx2_cpt_compcode_get(req);
 
-- 
2.22.0