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From: Bruce Richardson <bruce.richardson@intel.com>
To: dev@dpdk.org
Cc: kevin.laatz@intel.com, Bruce Richardson <bruce.richardson@intel.com>
Subject: [dpdk-dev] [PATCH] raw/ioat: fix queue index calculation
Date: Tue,  3 Nov 2020 14:48:58 +0000
Message-ID: <20201103144858.1317742-1-bruce.richardson@intel.com> (raw)

Coverity flags a possible problem where the 8-bit wq_idx value may have
errors when shifted and sign-extended to 64-bits. Since this can only occur
if the shift index is larger than any expected value from hardware, it's
unlikely to cause any real problems, but we can eliminate any
possible errors, and the coverity issue, by explicitly typecasting
the uint8_t value to 64-bits before any shift operations occur.

Coverity issue: 363695
Fixes: a33969462135 ("raw/ioat: fix work-queue config size")

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
 drivers/raw/ioat/idxd_pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/raw/ioat/idxd_pci.c b/drivers/raw/ioat/idxd_pci.c
index 99ecfbbb4..7bc125014 100644
--- a/drivers/raw/ioat/idxd_pci.c
+++ b/drivers/raw/ioat/idxd_pci.c
@@ -47,7 +47,8 @@ idxd_pci_dev_command(struct idxd_rawdev *idxd, enum rte_idxd_cmds command)
 static uint32_t *
 idxd_get_wq_cfg(struct idxd_pci_common *pci, uint8_t wq_idx)
-	return RTE_PTR_ADD(pci->wq_regs_base, wq_idx << (5 + pci->wq_cfg_sz));
+	return RTE_PTR_ADD(pci->wq_regs_base,
+			(uint64_t)wq_idx << (5 + pci->wq_cfg_sz));
 static int

             reply	other threads:[~2020-11-03 14:49 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03 14:48 Bruce Richardson [this message]
2020-11-03 20:21 ` Thomas Monjalon
2020-11-03 21:51   ` Thomas Monjalon
2020-11-04  9:43     ` Bruce Richardson
2020-11-05 10:41 ` [dpdk-dev] [PATCH v2] " Bruce Richardson
2020-11-13 14:32   ` Thomas Monjalon

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