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From: Natanael Copa <ncopa@alpinelinux.org>
To: dev@dpdk.org,
Ferruh Yigit <ferruh.yigit@intel.com>
Cc: Natanael Copa <ncopa@alpinelinux.org>,
stable@dpdk.org
Date: Thu, 5 Nov 2020 22:17:11 +0100
Message-Id: <20201105211716.25181-4-ncopa@alpinelinux.org>
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<20201105211716.25181-1-ncopa@alpinelinux.org>
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Subject: [dpdk-dev] [PATCH v4 3/8] bus/pci: add fallback for out* for non
GNU libc
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Add a fallback for non-GNU libc systems like musl libc for the
non-standard functions outl_p, outw_p and outb_p.
This solves the following buildtime errors when building with musl libc:
pci_uio.c:(.text+0xaa1): undefined reference to `outw_p'
pci_uio.c:(.text+0xac5): undefined reference to `outl_p'
pci_uio.c:(.text+0xadf): undefined reference to `outb_p'
We also handle the non-x86 with macros to factor out various ifdefs in
the code.
Bugzilla ID: 35
Fixes: c752998b5e2e ("pci: introduce library and driver")
Cc: stable@dpdk.org
Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
---
drivers/bus/pci/linux/pci_uio.c | 95 ++++++++++++++++++++++-----------
1 file changed, 64 insertions(+), 31 deletions(-)
diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_=
uio.c
index f3305a2f2..626c8a2cc 100644
--- a/drivers/bus/pci/linux/pci_uio.c
+++ b/drivers/bus/pci/linux/pci_uio.c
@@ -14,7 +14,64 @@
=20
#if defined(RTE_ARCH_X86)
#include <sys/io.h>
-#endif
+
+#define pci_uio_inl(reg) inl(reg)
+#define pci_uio_inw(reg) inw(reg)
+#define pci_uio_inb(reg) inb(reg)
+
+#else /* RTE_ARCH_X86 */
+
+#define pci_uio_inl(reg) (*(volatile uint32_t *)(reg))
+#define pci_uio_inw(reg) (*(volatile uint16_t *)(reg))
+#define pci_uio_inb(reg) (*(volatile uint8_t *)(reg))
+
+#endif /* RTE_ARCH_X86 */
+
+
+#if defined(RTE_ARCH_X86)
+static inline void
+pci_uio_outl_p(unsigned int value, unsigned short int port)
+{
+#if defined(__GLIBC__)
+ outl_p(value, port);
+#else /* __GLIBC__ */
+ __asm__ __volatile__ ("outl %0,%w1\noutb %%al,$0x80" : : "a" (value),
+ "Nd" (port));
+#endif /* __GLIBC__ */
+}
+#else /* RTE_ARCH_X86 */
+#define pci_uio_outl_p(value, reg) (*(volatile uint32_t *)(reg) =3D (val=
ue))
+#endif /* RTE_ARCH_X86 */
+
+#if defined(RTE_ARCH_X86)
+static inline void
+pci_uio_outw_p(unsigned short int value, unsigned short int port)
+{
+#if defined(__GLIBC__)
+ outw_p(value, port);
+#else /* __GLIBC__ */
+ __asm__ __volatile__ ("outw %w0,%w1\noutb %%al,$0x80" : : "a" (value),
+ "Nd" (port));
+#endif /* __GLIBC__ */
+}
+#else /* RTE_ARCH_X86 */
+#define pci_uio_outw_p(value, reg) (*(volatile uint16_t *)(reg) =3D (val=
ue))
+#endif /* RTE_ARCH_X86 */
+
+#if defined(RTE_ARCH_X86)
+static inline void
+pci_uio_outb_p(unsigned char value, unsigned short int port)
+{
+#if defined(__GLIBC__)
+ outb_p(value, port);
+#else /* __GLIBC__ */
+ __asm__ __volatile__ ("outb %b0,%w1\noutb %%al,$0x80" : : "a" (value),
+ "Nd" (port));
+#endif /* __GLIBC__ */
+}
+#else /* RTE_ARCH_X86 */
+#define pci_uio_outb_p(value, reg) (*(volatile uint8_t *)(reg) =3D (valu=
e))
+#endif /* RTE_ARCH_X86 */
=20
#include <rte_string_fns.h>
#include <rte_log.h>
@@ -500,25 +557,13 @@ pci_uio_ioport_read(struct rte_pci_ioport *p,
for (d =3D data; len > 0; d +=3D size, reg +=3D size, len -=3D size) {
if (len >=3D 4) {
size =3D 4;
-#if defined(RTE_ARCH_X86)
- *(uint32_t *)d =3D inl(reg);
-#else
- *(uint32_t *)d =3D *(volatile uint32_t *)reg;
-#endif
+ *(uint32_t *)d =3D pci_uio_inl(reg);
} else if (len >=3D 2) {
size =3D 2;
-#if defined(RTE_ARCH_X86)
- *(uint16_t *)d =3D inw(reg);
-#else
- *(uint16_t *)d =3D *(volatile uint16_t *)reg;
-#endif
+ *(uint16_t *)d =3D pci_uio_inw(reg);
} else {
size =3D 1;
-#if defined(RTE_ARCH_X86)
- *d =3D inb(reg);
-#else
- *d =3D *(volatile uint8_t *)reg;
-#endif
+ *d =3D pci_uio_inb(reg);
}
}
}
@@ -534,25 +579,13 @@ pci_uio_ioport_write(struct rte_pci_ioport *p,
for (s =3D data; len > 0; s +=3D size, reg +=3D size, len -=3D size) {
if (len >=3D 4) {
size =3D 4;
-#if defined(RTE_ARCH_X86)
- outl_p(*(const uint32_t *)s, reg);
-#else
- *(volatile uint32_t *)reg =3D *(const uint32_t *)s;
-#endif
+ pci_uio_outl_p(*(const uint32_t *)s, reg);
} else if (len >=3D 2) {
size =3D 2;
-#if defined(RTE_ARCH_X86)
- outw_p(*(const uint16_t *)s, reg);
-#else
- *(volatile uint16_t *)reg =3D *(const uint16_t *)s;
-#endif
+ pci_uio_outw_p(*(const uint16_t *)s, reg);
} else {
size =3D 1;
-#if defined(RTE_ARCH_X86)
- outb_p(*s, reg);
-#else
- *(volatile uint8_t *)reg =3D *s;
-#endif
+ pci_uio_outb_p(*s, reg);
}
}
}
--=20
2.29.2