From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E876AA0545; Thu, 12 Nov 2020 03:39:53 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BDE4D592B; Thu, 12 Nov 2020 03:39:51 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id D4918569B for ; Thu, 12 Nov 2020 03:39:49 +0100 (CET) IronPort-SDR: XH/LNMdPt6z6HYXLzmxkXQRyAjpxp7buebekqQfoc/FdnL9eFUTxCFt6gijqLYQ51MzJADGbyz EKUY37wYYFPQ== X-IronPort-AV: E=McAfee;i="6000,8403,9802"; a="169464498" X-IronPort-AV: E=Sophos;i="5.77,471,1596524400"; d="scan'208";a="169464498" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2020 18:39:43 -0800 IronPort-SDR: TJE4kagwy5okb1MhTwUpu+SwzqGOXktEK5/DUznnqRNiO9mH2k6EXkQGynKcRZyMM73uQLAiYK xzk+QCFFVq2A== X-IronPort-AV: E=Sophos;i="5.77,471,1596524400"; d="scan'208";a="542062772" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Nov 2020 18:39:41 -0800 From: "Zhang,Alvin" To: qi.z.zhang@intel.com, leyi.rong@intel.com Cc: dev@dpdk.org, Alvin Zhang Date: Thu, 12 Nov 2020 10:39:33 +0800 Message-Id: <20201112023933.27360-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH] net/ice: support flow mark ID in avx512 path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Alvin Zhang Support flow director mark ID parsing from flexible Rx descriptor in avx512 path. Signed-off-by: Alvin Zhang --- drivers/net/ice/ice_rxtx_vec_avx512.c | 61 +++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c index af6b324..215e6b5 100644 --- a/drivers/net/ice/ice_rxtx_vec_avx512.c +++ b/drivers/net/ice/ice_rxtx_vec_avx512.c @@ -128,6 +128,25 @@ ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id); } +static inline __m256i +ice_flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7) +{ +#define FDID_MIS_MAGIC 0xFFFFFFFF + RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2)); + RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13)); + const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR | + PKT_RX_FDIR_ID); + /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */ + const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC); + __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7, + fdir_mis_mask); + /* this XOR op results to bit-reverse the fdir_mask */ + fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask); + const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit); + + return fdir_flags; +} + static inline uint16_t _ice_recv_raw_pkts_vec_avx512(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts, @@ -444,6 +463,48 @@ const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags, rss_vlan_flags); + if (rxq->fdir_enabled) { + const __m256i fdir_id4_7 = + _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5); + + const __m256i fdir_id0_3 = + _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1); + + const __m256i fdir_id0_7 = + _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3); + + const __m256i fdir_flags = + ice_flex_rxd_to_fdir_flags_vec_avx2(fdir_id0_7); + + /* merge with fdir_flags */ + mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags); + + /* write to mbuf: have to use scalar store here */ + rx_pkts[i + 0]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 3); + + rx_pkts[i + 1]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 7); + + rx_pkts[i + 2]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 2); + + rx_pkts[i + 3]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 6); + + rx_pkts[i + 4]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 1); + + rx_pkts[i + 5]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 5); + + rx_pkts[i + 6]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 0); + + rx_pkts[i + 7]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 4); + } /* if() on fdir_enabled */ + #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC /** * needs to load 2nd 16B of each desc for RSS hash parsing, -- 1.8.3.1