From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A803EA0545; Fri, 13 Nov 2020 03:51:32 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EDCED56A3; Fri, 13 Nov 2020 03:51:30 +0100 (CET) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 0CEB31DB8 for ; Fri, 13 Nov 2020 03:51:27 +0100 (CET) IronPort-SDR: FFHBJfe3vsT5NC/I1AHtu4VA1RERhbmRWjDMgQ6/8tOXDp75CBC1T5zUeG6JDZTu6pLNRgwC8J YeXa3eN0aBfA== X-IronPort-AV: E=McAfee;i="6000,8403,9803"; a="157437592" X-IronPort-AV: E=Sophos;i="5.77,473,1596524400"; d="scan'208";a="157437592" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2020 18:51:25 -0800 IronPort-SDR: 8FsC6fiIrmE0plQX4X2GFLmmnC/GFiyDHJEq36Hukppl7muRNZhh3NP1gD7VfUR/P5SI0P222z UcOoAmN3+KBw== X-IronPort-AV: E=Sophos;i="5.77,473,1596524400"; d="scan'208";a="532406890" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2020 18:51:23 -0800 From: "Zhang,Alvin" To: qi.z.zhang@intel.com, leyi.rong@intel.com, wenzhuo.lu@intel.com Cc: dev@dpdk.org, Alvin Zhang Date: Fri, 13 Nov 2020 10:51:18 +0800 Message-Id: <20201113025118.25300-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20201113022506.23076-1-alvinx.zhang@intel.com> References: <20201113022506.23076-1-alvinx.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3] net/ice: support flow mark ID in avx512 path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Alvin Zhang Support flow director mark ID parsing from flexible Rx descriptor in avx512 path. Signed-off-by: Alvin Zhang --- v2: Update codes according to comments. v3: Rename the function ice_flex_rxd_to_fdir_flags_vec_avx with ice_flex_rxd_to_fdir_flags_vec_avx512. --- drivers/net/ice/ice_rxtx_vec_avx512.c | 66 +++++++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c index af6b324..df5d2be 100644 --- a/drivers/net/ice/ice_rxtx_vec_avx512.c +++ b/drivers/net/ice/ice_rxtx_vec_avx512.c @@ -128,6 +128,25 @@ ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id); } +static inline __m256i +ice_flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7) +{ +#define FDID_MIS_MAGIC 0xFFFFFFFF + RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2)); + RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13)); + const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR | + PKT_RX_FDIR_ID); + /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */ + const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC); + __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7, + fdir_mis_mask); + /* this XOR op results to bit-reverse the fdir_mask */ + fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask); + const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit); + + return fdir_flags; +} + static inline uint16_t _ice_recv_raw_pkts_vec_avx512(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts, @@ -441,8 +460,51 @@ rss_vlan_flag_bits); /* merge flags */ - const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags, - rss_vlan_flags); + __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags, + rss_vlan_flags); + + if (rxq->fdir_enabled) { + const __m256i fdir_id4_7 = + _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5); + + const __m256i fdir_id0_3 = + _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1); + + const __m256i fdir_id0_7 = + _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3); + + const __m256i fdir_flags = + ice_flex_rxd_to_fdir_flags_vec_avx512 + (fdir_id0_7); + + /* merge with fdir_flags */ + mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags); + + /* write to mbuf: have to use scalar store here */ + rx_pkts[i + 0]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 3); + + rx_pkts[i + 1]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 7); + + rx_pkts[i + 2]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 2); + + rx_pkts[i + 3]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 6); + + rx_pkts[i + 4]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 1); + + rx_pkts[i + 5]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 5); + + rx_pkts[i + 6]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 0); + + rx_pkts[i + 7]->hash.fdir.hi = + _mm256_extract_epi32(fdir_id0_7, 4); + } /* if() on fdir_enabled */ #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC /** -- 1.8.3.1