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* [dpdk-dev] [PATCH] net/mlx5: fix packet padding config for RxQ via DevX
@ 2020-11-15 14:25 Alexander Kozyrev
  2020-11-17 10:52 ` Raslan Darawsheh
  0 siblings, 1 reply; 2+ messages in thread
From: Alexander Kozyrev @ 2020-11-15 14:25 UTC (permalink / raw)
  To: dev; +Cc: stable, rasland, dekelp, matan

Received packets can be aligned to the size of the cache line on
PCI transactions. This could improve performance by avoiding
partial cache line writes in exchange for increased PCI bandwidth.

This feature is supposed to be controlled by the rxq_pkt_pad_en
devarg and it is true for an RxQ created via the Verbs API.
But in the DevX API case, it is erroneously controlled by the
rxq_cqe_pad_en devarg instead, which is in charge of the CQE
padding instead and should not control the RxQ creation.

Fix DevX RxQ creation by using the proper configuration flag for
Rx packet padding that is being set by the rxq_pkt_pad_en devarg.

Fixes: dc9ceff73c ("net/mlx5: create advanced RxQ via DevX")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/mlx5_devx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index e9ceda5caf..34044fcb0c 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -294,7 +294,7 @@ static void
 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
 		       struct mlx5_devx_wq_attr *wq_attr)
 {
-	wq_attr->end_padding_mode = priv->config.cqe_pad ?
+	wq_attr->end_padding_mode = priv->config.hw_padding ?
 					MLX5_WQ_END_PAD_MODE_ALIGN :
 					MLX5_WQ_END_PAD_MODE_NONE;
 	wq_attr->pd = priv->sh->pdn;
-- 
2.24.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [dpdk-dev] [PATCH] net/mlx5: fix packet padding config for RxQ via DevX
  2020-11-15 14:25 [dpdk-dev] [PATCH] net/mlx5: fix packet padding config for RxQ via DevX Alexander Kozyrev
@ 2020-11-17 10:52 ` Raslan Darawsheh
  0 siblings, 0 replies; 2+ messages in thread
From: Raslan Darawsheh @ 2020-11-17 10:52 UTC (permalink / raw)
  To: Alexander Kozyrev, dev; +Cc: stable, Dekel Peled, Matan Azrad

Hi,

> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Sunday, November 15, 2020 4:26 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Dekel Peled
> <dekelp@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Subject: [PATCH] net/mlx5: fix packet padding config for RxQ via DevX
> 
> Received packets can be aligned to the size of the cache line on
> PCI transactions. This could improve performance by avoiding
> partial cache line writes in exchange for increased PCI bandwidth.
> 
> This feature is supposed to be controlled by the rxq_pkt_pad_en
> devarg and it is true for an RxQ created via the Verbs API.
> But in the DevX API case, it is erroneously controlled by the
> rxq_cqe_pad_en devarg instead, which is in charge of the CQE
> padding instead and should not control the RxQ creation.
> 
> Fix DevX RxQ creation by using the proper configuration flag for
> Rx packet padding that is being set by the rxq_pkt_pad_en devarg.
> 
> Fixes: dc9ceff73c ("net/mlx5: create advanced RxQ via DevX")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2020-11-17 10:52 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
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2020-11-15 14:25 [dpdk-dev] [PATCH] net/mlx5: fix packet padding config for RxQ via DevX Alexander Kozyrev
2020-11-17 10:52 ` Raslan Darawsheh

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