From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 69C34A04DD; Thu, 19 Nov 2020 13:23:48 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 449454C90; Thu, 19 Nov 2020 13:23:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id B6622F3E for ; Thu, 19 Nov 2020 13:23:45 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0AJCBew2032764 for ; Thu, 19 Nov 2020 04:23:43 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Q/7mUvegJLThOujqvrvz3F6dR18BRrANMvQQEXNtyFw=; b=J5D1fs1TnWHb+ITM1z/Jam4DsoMzH6addPlaPXZ/bQogOUMu9DURb9o4x1QvuN4mAC0D t92BrdCvtqSBbnNcGQ5P/04Nb/NcxT82xLMAYRDOdqf8XmFyFCAJWUZaTYRjsYTNaZsC 4DTTcVCZCBki8pYs+Xc8PBW4NkBveLrULgnW8xTz9cOZ9YjNMS2NcDqRZVbXVx0TQhLb efF3JHBbTty1s0yKwKGZ4pcBFDqj/tSqyeyVc3JEBGzzcq6vn1ukTfRyrgRQn68FrA/i SmjDddRroofpUEdmy2uP/jxuJw+jNairxNk2Rw/2X2sTWlZCT2I8LmKAN43/9SdPCmfR Cw== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 34w7ncudtk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 19 Nov 2020 04:23:43 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 Nov 2020 04:23:42 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 Nov 2020 04:23:42 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.170.178]) by maili.marvell.com (Postfix) with ESMTP id 662B03F7040; Thu, 19 Nov 2020 04:23:40 -0800 (PST) From: To: , Pavan Nikhilesh CC: Date: Thu, 19 Nov 2020 17:53:35 +0530 Message-ID: <20201119122336.5079-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-19_08:2020-11-19, 2020-11-19 signatures=0 Subject: [dpdk-dev] [PATCH 1/2] event/octeontx2: remove selftest from dev args X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Since selftest now depends on dynamic mbuf fields it is not feasible to run selftest on device probe. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev.c | 8 -------- drivers/event/octeontx2/otx2_evdev.h | 1 - 2 files changed, 9 deletions(-) diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index b31c26e95..c1a5916cd 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -1606,7 +1606,6 @@ static struct rte_eventdev_ops otx2_sso_ops = { #define OTX2_SSO_XAE_CNT "xae_cnt" #define OTX2_SSO_SINGLE_WS "single_ws" #define OTX2_SSO_GGRP_QOS "qos" -#define OTX2_SSO_SELFTEST "selftest" static void parse_queue_param(char *value, void *opaque) @@ -1696,8 +1695,6 @@ sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs) if (kvlist == NULL) return; - rte_kvargs_process(kvlist, OTX2_SSO_SELFTEST, &parse_kvargs_flag, - &dev->selftest); rte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value, &dev->xae_cnt); rte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag, @@ -1813,10 +1810,6 @@ otx2_sso_init(struct rte_eventdev *event_dev) otx2_sso_dbg("Initializing %s max_queues=%d max_ports=%d", event_dev->data->name, dev->max_event_queues, dev->max_event_ports); - if (dev->selftest) { - event_dev->dev->driver = &pci_sso.driver; - event_dev->dev_ops->dev_selftest(); - } otx2_tim_init(pci_dev, (struct otx2_dev *)dev); @@ -1866,5 +1859,4 @@ RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT "=" OTX2_SSO_SINGLE_WS "=1" OTX2_SSO_GGRP_QOS "=" - OTX2_SSO_SELFTEST "=1" OTX2_NPA_LOCK_MASK "=<1-65535>"); diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 547e29d4a..210ee89f1 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -147,7 +147,6 @@ struct otx2_sso_evdev { uint64_t *timer_adptr_sz; /* Dev args */ uint8_t dual_ws; - uint8_t selftest; uint32_t xae_cnt; uint8_t qos_queue_cnt; struct otx2_sso_qos *qos_parse_data; -- 2.17.1