From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from dpdk.org (dpdk.org [92.243.14.124])
	by inbox.dpdk.org (Postfix) with ESMTP id 418F1A04B1;
	Tue, 24 Nov 2020 09:10:40 +0100 (CET)
Received: from [92.243.14.124] (localhost [127.0.0.1])
	by dpdk.org (Postfix) with ESMTP id B5AD2C914;
	Tue, 24 Nov 2020 09:10:37 +0100 (CET)
Received: from hqnvemgate26.nvidia.com (hqnvemgate26.nvidia.com
 [216.228.121.65]) by dpdk.org (Postfix) with ESMTP id EDE81C90C
 for <dev@dpdk.org>; Tue, 24 Nov 2020 09:10:35 +0100 (CET)
Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by
 hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA)
 id <B5fbcbffc0000>; Tue, 24 Nov 2020 00:10:36 -0800
Received: from nvidia.com (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13)
 with Microsoft SMTP Server (TLS) id 15.0.1473.3;
 Tue, 24 Nov 2020 08:10:31 +0000
From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
CC: <getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,
 <thomas@monjalon.net>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, "Shahaf
 Shuler" <shahafs@nvidia.com>, Michael Baum <michaelba@nvidia.com>
Date: Tue, 24 Nov 2020 10:10:13 +0200
Message-ID: <20201124081013.1912-1-getelson@nvidia.com>
X-Mailer: git-send-email 2.29.2
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain
X-Originating-IP: [10.124.1.5]
X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To
 HQMAIL107.nvidia.com (172.20.187.13)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
 t=1606205436; bh=02HoFPyW8da/UHm9cWTbx+6jhmQ8/4UDp/6NW7IuU1c=;
 h=From:To:CC:Subject:Date:Message-ID:X-Mailer:MIME-Version:
 Content-Transfer-Encoding:Content-Type:X-Originating-IP:
 X-ClientProxiedBy;
 b=HgER14liUHEqtk+8nxqH2EB8FONKU2ldPUd7cSoZ53E97DVBOp49VUO7hBo/qqsYI
 xl74wlA/0Ow/Ghd0o6rc8UPrH0RImOqD1isKRY0QvYcbaCL0upl8TK5wmZOv4YLzx0
 DcfYHHgng2OGnJBfrJ7I3IRocSiATrjxC0HdlP5a4CFYeM5EnxLwYFbsDR5n8BVfLz
 jQ9mRMfBtbH9rL/UaqbbmatZA2ywUNlK6+EsuxYXeZd/cLKPCgTEkEmFgobCciOv0s
 ZRXDJjDeeim7Sm0605Ry7nFTPvAA/fZytcHcuU+CrFO4xC4T5C/d38jPjSR8KIfrvu
 SfBMyCmDFUHIQ==
Subject: [dpdk-dev] [PATCH] net/mlx5: fix DevX resources memory management.
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

Invalid memory release order of DevX resources caused PMD crash.

1. SQ and CQ memory must be unregistered with DevX before it is freed.
2. SQ objects reference to a CQ ones. Hence, SQ should be destroyed in
   advance of CQ it references to.

Fixes: 6deb19e1b2d2 ("net/mlx5: separate Rx queue object creations")
Fixes: 88f2e3f18cc7 ("net/mlx5: rearrange SQ and CQ creation in DevX
module")

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5_devx.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index 73ee147246..de9b204075 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -154,14 +154,14 @@ mlx5_rxq_release_devx_rq_resources(struct mlx5_rxq_ct=
rl *rxq_ctrl)
 {
 	struct mlx5_devx_dbr_page *dbr_page =3D rxq_ctrl->rq_dbrec_page;
=20
-	if (rxq_ctrl->rxq.wqes) {
-		mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
-		rxq_ctrl->rxq.wqes =3D NULL;
-	}
 	if (rxq_ctrl->wq_umem) {
 		mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
 		rxq_ctrl->wq_umem =3D NULL;
 	}
+	if (rxq_ctrl->rxq.wqes) {
+		mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
+		rxq_ctrl->rxq.wqes =3D NULL;
+	}
 	if (dbr_page) {
 		claim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,
 					    mlx5_os_get_umem_id(dbr_page->umem),
@@ -181,14 +181,14 @@ mlx5_rxq_release_devx_cq_resources(struct mlx5_rxq_ct=
rl *rxq_ctrl)
 {
 	struct mlx5_devx_dbr_page *dbr_page =3D rxq_ctrl->cq_dbrec_page;
=20
-	if (rxq_ctrl->rxq.cqes) {
-		rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);
-		rxq_ctrl->rxq.cqes =3D NULL;
-	}
 	if (rxq_ctrl->cq_umem) {
 		mlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);
 		rxq_ctrl->cq_umem =3D NULL;
 	}
+	if (rxq_ctrl->rxq.cqes) {
+		rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);
+		rxq_ctrl->rxq.cqes =3D NULL;
+	}
 	if (dbr_page) {
 		claim_zero(mlx5_release_dbr(&rxq_ctrl->priv->dbrpgs,
 					    mlx5_os_get_umem_id(dbr_page->umem),
@@ -1174,8 +1174,8 @@ mlx5_txq_release_devx_cq_resources(struct mlx5_txq_ob=
j *txq_obj)
 static void
 mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)
 {
-	mlx5_txq_release_devx_cq_resources(txq_obj);
 	mlx5_txq_release_devx_sq_resources(txq_obj);
+	mlx5_txq_release_devx_cq_resources(txq_obj);
 }
=20
 /**
--=20
2.29.2