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From: Qi Zhang <qi.z.zhang@intel.com>
To: qiming.yang@intel.com
Cc: dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,
	Jacob Keller <jacob.e.keller@intel.com>
Subject: [dpdk-dev] [PATCH 04/27] net/ice/base: refactor interface for flash read
Date: Tue, 15 Dec 2020 14:04:56 +0800
Message-ID: <20201215060519.302145-5-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20201215060519.302145-1-qi.z.zhang@intel.com>

The ice_read_flash_module interface for reading from the various NVM
modules was introduced.

It's purpose is two-fold. First, it enables reading data from the CSS
header, used to allow accessing the image security revisions. Second, it
allowed reading from either the 1st or the 2nd NVM bank. This interface
was necessary because the device has two copies of each module. Only one
bank is active at a time, but it could be different for each module. The
driver had to determine which bank was active and then use that to
calculate the offset into the flash to read.

Future plans include allowing access to read not just from the active
flash bank, but also the inactive bank. This will be useful for enabling
display of the version information for a pending flash update.

The current abstraction in ice_read_flash_module is to specify the exact
bank to read. This requires callers to know whether to read from the 1st
or 2nd flash bank. This is the wrong abstraction level, since in most
cases the decision point from a caller's perspective is whether to read
from the active bank or the inactive bank.

Add a new ice_bank_select enumeration, used to indicate whether a flow
wants to read from the active, or inactive flash bank. Refactor
ice_read_flash_module to take this new enumeration instead of a raw
flash bank.

Have ice_read_flash_module select which bank to read from based on the
cached data we load during NVM initialization. With this change, it will
be come easier to implement reading version data from the inactive flash
banks in a future change.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_nvm.c  | 116 ++++++++++++++++++++++----------
 drivers/net/ice/base/ice_type.h |   9 +++
 2 files changed, 91 insertions(+), 34 deletions(-)

diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 7b76af7b6f..facfaf1a41 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -212,6 +212,74 @@ void ice_release_nvm(struct ice_hw *hw)
 	ice_release_res(hw, ICE_NVM_RES_ID);
 }
 
+/**
+ * ice_get_flash_bank_offset - Get offset into requested flash bank
+ * @hw: pointer to the HW structure
+ * @bank: whether to read from the active or inactive flash bank
+ * @module: the module to read from
+ *
+ * Based on the module, lookup the module offset from the beginning of the
+ * flash.
+ *
+ * Returns the flash offset. Note that a value of zero is invalid and must be
+ * treated as an error.
+ */
+static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module)
+{
+	struct ice_bank_info *banks = &hw->flash.banks;
+	enum ice_flash_bank active_bank;
+	bool second_bank_active;
+	u32 offset, size;
+
+	switch (module) {
+	case ICE_SR_1ST_NVM_BANK_PTR:
+		offset = banks->nvm_ptr;
+		size = banks->nvm_size;
+		active_bank = banks->nvm_bank;
+		break;
+	case ICE_SR_1ST_OROM_BANK_PTR:
+		offset = banks->orom_ptr;
+		size = banks->orom_size;
+		active_bank = banks->orom_bank;
+		break;
+	case ICE_SR_NETLIST_BANK_PTR:
+		offset = banks->netlist_ptr;
+		size = banks->netlist_size;
+		active_bank = banks->netlist_bank;
+		break;
+	default:
+		ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash module: 0x%04x\n", module);
+		return 0;
+	}
+
+	switch (active_bank) {
+	case ICE_1ST_FLASH_BANK:
+		second_bank_active = false;
+		break;
+	case ICE_2ND_FLASH_BANK:
+		second_bank_active = true;
+		break;
+	default:
+		ice_debug(hw, ICE_DBG_NVM, "Unexpected value for active flash bank: %u\n",
+			  active_bank);
+		return 0;
+	}
+
+	/* The second flash bank is stored immediately following the first
+	 * bank. Based on whether the 1st or 2nd bank is active, and whether
+	 * we want the active or inactive bank, calculate the desired offset.
+	 */
+	switch (bank) {
+	case ICE_ACTIVE_FLASH_BANK:
+		return offset + (second_bank_active ? size : 0);
+	case ICE_INACTIVE_FLASH_BANK:
+		return offset + (second_bank_active ? 0 : size);
+	}
+
+	ice_debug(hw, ICE_DBG_NVM, "Unexpected value for flash bank selection: %u\n", bank);
+	return 0;
+}
+
 /**
  * ice_read_flash_module - Read a word from one of the main NVM modules
  * @hw: pointer to the HW structure
@@ -220,49 +288,29 @@ void ice_release_nvm(struct ice_hw *hw)
  * @offset: the offset into the module in words
  * @data: storage for the word read from the flash
  *
- * Read a word from the specified bank of the module. The bank must be either
- * the 1st or 2nd bank. The word will be read using flat NVM access, and
- * relies on the hw->flash.banks data being setup by
- * ice_determine_active_flash_banks() during initialization.
+ * Read data from the specified flash module. The bank parameter indicates
+ * whether or not to read from the active bank or the inactive bank of that
+ * module.
+ *
+ * The word will be read using flat NVM access, and relies on the
+ * hw->flash.banks data being setup by ice_determine_active_flash_banks()
+ * during initialization.
  */
 static enum ice_status
-ice_read_flash_module(struct ice_hw *hw, enum ice_flash_bank bank, u16 module,
+ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module,
 		      u32 offset, u16 *data)
 {
-	struct ice_bank_info *banks = &hw->flash.banks;
 	u32 bytes = sizeof(u16);
 	enum ice_status status;
 	__le16 data_local;
-	bool second_bank;
 	u32 start;
 
 	ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
 
-	switch (bank) {
-	case ICE_1ST_FLASH_BANK:
-		second_bank = false;
-		break;
-	case ICE_2ND_FLASH_BANK:
-		second_bank = true;
-		break;
-	case ICE_INVALID_FLASH_BANK:
-	default:
-		ice_debug(hw, ICE_DBG_NVM, "Unexpected flash bank %u\n", bank);
-		return ICE_ERR_PARAM;
-	}
-
-	switch (module) {
-	case ICE_SR_1ST_NVM_BANK_PTR:
-		start = banks->nvm_ptr + (second_bank ? banks->nvm_size : 0);
-		break;
-	case ICE_SR_1ST_OROM_BANK_PTR:
-		start = banks->orom_ptr + (second_bank ? banks->orom_size : 0);
-		break;
-	case ICE_SR_NETLIST_BANK_PTR:
-		start = banks->netlist_ptr + (second_bank ? banks->netlist_size : 0);
-		break;
-	default:
-		ice_debug(hw, ICE_DBG_NVM, "Unexpected flash module 0x%04x\n", module);
+	start = ice_get_flash_bank_offset(hw, bank, module);
+	if (!start) {
+		ice_debug(hw, ICE_DBG_NVM, "Unable to calculate flash bank offset for module 0x%04x\n",
+			  module);
 		return ICE_ERR_PARAM;
 	}
 
@@ -292,7 +340,7 @@ ice_read_flash_module(struct ice_hw *hw, enum ice_flash_bank bank, u16 module,
 static enum ice_status
 ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data)
 {
-	return ice_read_flash_module(hw, hw->flash.banks.nvm_bank,
+	return ice_read_flash_module(hw, ICE_ACTIVE_FLASH_BANK,
 				     ICE_SR_1ST_NVM_BANK_PTR, offset, data);
 }
 
@@ -309,7 +357,7 @@ ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data)
 static enum ice_status
 ice_read_active_orom_module(struct ice_hw *hw, u32 offset, u16 *data)
 {
-	return ice_read_flash_module(hw, hw->flash.banks.orom_bank,
+	return ice_read_flash_module(hw, ICE_ACTIVE_FLASH_BANK,
 				     ICE_SR_1ST_OROM_BANK_PTR, offset, data);
 }
 
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 3b54ce92e1..b0f70c15dd 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -537,6 +537,15 @@ enum ice_flash_bank {
 	ICE_2ND_FLASH_BANK,
 };
 
+/* Enumeration of which flash bank is desired to read from, either the active
+ * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
+ * code which just wants to read the active or inactive flash bank.
+ */
+enum ice_bank_select {
+	ICE_ACTIVE_FLASH_BANK,
+	ICE_INACTIVE_FLASH_BANK,
+};
+
 /* information for accessing NVM, OROM, and Netlist flash banks */
 struct ice_bank_info {
 	u32 nvm_ptr;				/* Pointer to 1st NVM bank */
-- 
2.26.2


  parent reply	other threads:[~2020-12-15  6:02 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-15  6:04 [dpdk-dev] [PATCH 00/27] ice base code update Qi Zhang
2020-12-15  6:04 ` [dpdk-dev] [PATCH 01/27] net/ice/base: modify ptype map for UDP Qi Zhang
2020-12-15  6:04 ` [dpdk-dev] [PATCH 02/27] net/ice/base: increased control queue timeout Qi Zhang
2020-12-15  6:04 ` [dpdk-dev] [PATCH 03/27] net/ice/base: read more security revision options Qi Zhang
2020-12-15  6:04 ` Qi Zhang [this message]
2020-12-15  6:04 ` [dpdk-dev] [PATCH 05/27] net/ice/base: allow reading inactive flash security revision Qi Zhang
2020-12-15  6:04 ` [dpdk-dev] [PATCH 06/27] net/ice/base: allow reading arbitrary size data with flash read Qi Zhang
2020-12-15  6:04 ` [dpdk-dev] [PATCH 07/27] net/ice/base: read Option ROM combo version from CIVD section Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 08/27] net/ice/base: implement inactive NVM version get Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 09/27] net/ice/base: support GTP filtering via advanced switch filter Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 10/27] net/ice/base: cleanup some macros Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 11/27] net/ice/base: add definitions for FW health status codes Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 12/27] net/ice/base: add function for NVM checksum verification Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 13/27] net/ice/base: add condition to copy module info into memory Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 14/27] net/ice/base: add interface to support configuring VLAN mode Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 15/27] net/ice/base: support VXLAN VNI field in FDIR Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 16/27] net/ice/base: fix incorrect tunnel destroy Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 17/27] net/ice/base: add functionality to check if DVM is supported Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 18/27] net/ice/base: resend some AQ commands when EBUSY Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 19/27] net/ice/base: change get PHY capability error level Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 20/27] net/ice/base: modify recursive way of adding nodes Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 21/27] net/ice/base: fix for dereference of null pointer Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 22/27] net/ice/base: use Mode 4 to get PHY Abilites Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 23/27] net/ice/base: align macro names to the specification Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 24/27] net/ice/base: add eCPRI over MAC type 0 flow support Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 25/27] net/ice/base: add eCPRI over UDP " Qi Zhang
2021-01-05 16:24   ` Ferruh Yigit
2020-12-15  6:05 ` [dpdk-dev] [PATCH 26/27] net/ice/base: remove unused struct member Qi Zhang
2020-12-15  6:05 ` [dpdk-dev] [PATCH 27/27] net/ice/base: change a structure Qi Zhang
2020-12-24  3:16 ` [dpdk-dev] [PATCH 00/27] ice base code update Yang, Qiming
2020-12-28 10:34   ` Zhang, Qi Z
2021-01-05 16:22     ` Ferruh Yigit

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