From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A638FA09EF; Wed, 16 Dec 2020 15:26:26 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8F47BC9E2; Wed, 16 Dec 2020 15:25:33 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id DB2B8C9CE for ; Wed, 16 Dec 2020 15:25:30 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 16 Dec 2020 16:25:26 +0200 Received: from nvidia.com (c-236-2-60-065.mtl.labs.mlnx [10.236.2.65]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BGEPF6e015188; Wed, 16 Dec 2020 16:25:25 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, rasland@nvidia.com Date: Wed, 16 Dec 2020 16:25:08 +0200 Message-Id: <20201216142511.13660-4-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201216142511.13660-1-shirik@nvidia.com> References: <1599118768-13265-1-git-send-email-shirik@nvidia.com> <20201216142511.13660-1-shirik@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [RFC 3/6] common/mlx5: add matcher fields for GTP extensions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is a preparation step to support GTP extension header. In this patch we add the matcher fields that will be used to match on the GTP extension header. Signed-off-by: Shiri Kuzin --- drivers/common/mlx5/mlx5_prm.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 58d180486e..2878223ed9 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -791,7 +791,12 @@ struct mlx5_ifc_fte_match_set_misc3_bits { u8 gtpu_teid[0x20]; u8 gtpu_msg_type[0x08]; u8 gtpu_msg_flags[0x08]; - u8 reserved_at_170[0x90]; + u8 reserved_at_170[0x10]; + u8 gtpu_dw_2[0x20]; + u8 gtpu_first_ext_dw_0[0x20]; + u8 gtpu_dw_0[0x20]; + u8 reserved_at_240[0x20]; + }; struct mlx5_ifc_fte_match_set_misc4_bits { -- 2.21.0