From: "Nalla, Pradeep" <pnalla@marvell.com>
To: "Nalla, Pradeep" <pnalla@marvell.com>,
Radha Mohan Chintakuntla <radhac@marvell.com>,
Veerasenareddy Burru <vburru@marvell.com>
Cc: <jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH 15/15] net/octeontx_ep: Input output reset.
Date: Thu, 31 Dec 2020 07:22:47 +0000 [thread overview]
Message-ID: <20201231072247.5719-16-pnalla@marvell.com> (raw)
In-Reply-To: <20201231072247.5719-1-pnalla@marvell.com>
From: "Nalla Pradeep" <pnalla@marvell.com>
Function to allow resetting input and output queues are added. Supports
both otx and otx2 endpoints.
Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
---
drivers/net/octeontx_ep/otx2_ep_vf.c | 120 ++++++++++++++++++++++
drivers/net/octeontx_ep/otx_ep_vf.c | 143 +++++++++++++++++++++++++++
2 files changed, 263 insertions(+)
diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c
index 0fb8c26a5e..095c43b05a 100644
--- a/drivers/net/octeontx_ep/otx2_ep_vf.c
+++ b/drivers/net/octeontx_ep/otx2_ep_vf.c
@@ -7,6 +7,96 @@
#include "otx_ep_common.h"
#include "otx2_ep_vf.h"
+static int
+otx2_vf_reset_iq(struct otx_ep_device *otx_ep, int q_no)
+{
+ uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
+ volatile uint64_t d64 = 0ull;
+
+ /* There is no RST for a ring.
+ * Clear all registers one by one after disabling the ring
+ */
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));
+
+ d64 = 0xFFFFFFFF; /* ~0ull */
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
+
+ while ((d64 != 0) && loop--) {
+ otx2_write64(d64, otx_ep->hw_addr +
+ SDP_VF_R_IN_INSTR_DBELL(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = otx2_read64(otx_ep->hw_addr +
+ SDP_VF_R_IN_INSTR_DBELL(q_no));
+ }
+
+ loop = SDP_VF_BUSY_LOOP_COUNT;
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));
+ while ((d64 != 0) && loop--) {
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CNTS(q_no));
+ }
+
+ d64 = 0ull;
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));
+
+ return 0;
+}
+
+static int
+otx2_vf_reset_oq(struct otx_ep_device *otx_ep, int q_no)
+{
+ uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
+ volatile uint64_t d64 = 0ull;
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));
+
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));
+
+ d64 = 0xFFFFFFFF;
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
+
+ while ((d64 != 0) && loop--) {
+ otx2_write64(d64, otx_ep->hw_addr +
+ SDP_VF_R_OUT_SLIST_DBELL(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = otx2_read64(otx_ep->hw_addr +
+ SDP_VF_R_OUT_SLIST_DBELL(q_no));
+ }
+
+ loop = SDP_VF_BUSY_LOOP_COUNT;
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
+ while ((d64 != 0) && (loop--)) {
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
+ }
+
+ d64 = 0ull;
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));
+ otx2_write64(d64, otx_ep->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));
+
+ return 0;
+}
+
static void
otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
{
@@ -52,11 +142,39 @@ otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
}
+static int
+otx2_vf_reset_input_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+
+ otx_ep_dbg("%s :", __func__);
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)
+ otx2_vf_reset_iq(otx_ep, q_no);
+
+ return 0;
+}
+
+static int
+otx2_vf_reset_output_queues(struct otx_ep_device *otx_ep)
+{
+ uint64_t q_no = 0ull;
+
+ otx_ep_dbg(" %s :", __func__);
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)
+ otx2_vf_reset_oq(otx_ep, q_no);
+
+ return 0;
+}
+
static void
otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)
{
uint64_t q_no = 0ull;
+ otx2_vf_reset_input_queues(otx_ep);
+
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx2_vf_setup_global_iq_reg(otx_ep, q_no);
}
@@ -66,6 +184,8 @@ otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)
{
uint32_t q_no;
+ otx2_vf_reset_output_queues(otx_ep);
+
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx2_vf_setup_global_oq_reg(otx_ep, q_no);
}
diff --git a/drivers/net/octeontx_ep/otx_ep_vf.c b/drivers/net/octeontx_ep/otx_ep_vf.c
index a7c9d48dbc..0280802aa1 100644
--- a/drivers/net/octeontx_ep/otx_ep_vf.c
+++ b/drivers/net/octeontx_ep/otx_ep_vf.c
@@ -11,6 +11,114 @@
#include "otx_ep_common.h"
#include "otx_ep_vf.h"
+#ifdef OTX_EP_RESET_IOQ
+static int
+otx_ep_reset_iq(struct otx_ep_device *otx_ep, int q_no)
+{
+ uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ volatile uint64_t d64 = 0ull;
+
+ /* There is no RST for a ring.
+ * Clear all registers one by one after disabling the ring
+ */
+
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_ENABLE(q_no));
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_BADDR(q_no));
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_RSIZE(q_no));
+
+ d64 = 0xFFFFFFFF; /* ~0ull */
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INSTR_DBELL(q_no));
+ d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_INSTR_DBELL(q_no));
+
+ while ((d64 != 0) && loop--) {
+ otx_ep_write64(d64, otx_ep->hw_addr,
+ OTX_EP_R_IN_INSTR_DBELL(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = rte_read64(otx_ep->hw_addr +
+ OTX_EP_R_IN_INSTR_DBELL(q_no));
+ }
+ if (loop == 0) {
+ otx_ep_err("dbell reset failed\n");
+ return -1;
+ }
+
+ loop = OTX_EP_BUSY_LOOP_COUNT;
+ d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CNTS(q_no));
+ while ((d64 != 0) && loop--) {
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_CNTS(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_IN_CNTS(q_no));
+ }
+ if (loop == 0) {
+ otx_ep_err("cnt reset failed\n");
+ return -1;
+ }
+
+ d64 = 0ull;
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_INT_LEVELS(q_no));
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_PKT_CNT(q_no));
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_IN_BYTE_CNT(q_no));
+
+ return 0;
+}
+
+static int
+otx_ep_reset_oq(struct otx_ep_device *otx_ep, int q_no)
+{
+ uint64_t loop = OTX_EP_BUSY_LOOP_COUNT;
+ volatile uint64_t d64 = 0ull;
+
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_ENABLE(q_no));
+
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_BADDR(q_no));
+
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_RSIZE(q_no));
+
+ d64 = 0xFFFFFFFF;
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_SLIST_DBELL(q_no));
+ d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_SLIST_DBELL(q_no));
+
+ while ((d64 != 0) && loop--) {
+ otx_ep_write64(d64, otx_ep->hw_addr,
+ OTX_EP_R_OUT_SLIST_DBELL(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = rte_read64(otx_ep->hw_addr +
+ OTX_EP_R_OUT_SLIST_DBELL(q_no));
+ }
+ if (loop == 0) {
+ otx_ep_err("dbell reset failed\n");
+ return -1;
+ }
+
+ loop = OTX_EP_BUSY_LOOP_COUNT;
+ d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CNTS(q_no));
+ while ((d64 != 0) && (loop--)) {
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_CNTS(q_no));
+
+ rte_delay_ms(1);
+
+ d64 = rte_read64(otx_ep->hw_addr + OTX_EP_R_OUT_CNTS(q_no));
+ }
+ if (loop == 0) {
+ otx_ep_err("cnt reset failed\n");
+ return -1;
+ }
+
+
+ d64 = 0ull;
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_INT_LEVELS(q_no));
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_PKT_CNT(q_no));
+ otx_ep_write64(d64, otx_ep->hw_addr, OTX_EP_R_OUT_BYTE_CNT(q_no));
+
+ return 0;
+}
+#endif
static void
otx_ep_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
@@ -64,11 +172,42 @@ otx_ep_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
otx_ep_write64(reg_val, otx_ep->hw_addr, OTX_EP_R_OUT_CONTROL(q_no));
}
+#ifdef OTX_EP_RESET_IOQ
+static int
+otx_ep_reset_input_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+
+ otx_ep_dbg("%s :\n", __func__);
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)
+ otx_ep_reset_iq(otx_ep, q_no);
+
+ return 0;
+}
+
+static int
+otx_ep_reset_output_queues(struct otx_ep_device *otx_ep)
+{
+ uint64_t q_no = 0ull;
+
+ otx_ep_dbg(" %s :\n", __func__);
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++)
+ otx_ep_reset_oq(otx_ep, q_no);
+
+ return 0;
+}
+#endif
+
static void
otx_ep_setup_global_input_regs(struct otx_ep_device *otx_ep)
{
uint64_t q_no = 0ull;
+#ifdef OTX_EP_RESET_IOQ
+ otx_ep_reset_input_queues(otx_ep);
+#endif
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx_ep_setup_global_iq_reg(otx_ep, q_no);
}
@@ -78,8 +217,12 @@ otx_ep_setup_global_output_regs(struct otx_ep_device *otx_ep)
{
uint32_t q_no;
+#ifdef OTX_EP_RESET_IOQ
+ otx_ep_reset_output_queues(otx_ep);
+#endif
for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
otx_ep_setup_global_oq_reg(otx_ep, q_no);
+
}
static int
--
2.17.1
next prev parent reply other threads:[~2020-12-31 7:25 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-31 7:22 [dpdk-dev] [PATCH 00/15] Octeon Tx/Tx2 Endpoint pmd Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 01/15] net/octeontx_ep: add build and doc infrastructure Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 02/15] net/octeontx_ep: add ethdev probe and remove Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 03/15] net/octeontx_ep: add device init and uninit Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 04/15] net/octeontx_ep: Added basic device setup Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 05/15] net/octeontx_ep: Add dev info get and configure Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 06/15] net/octeontx_ep: Added rxq setup and release Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 07/15] net/octeontx_ep: Added tx queue " Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 08/15] net/octeontx_ep: Setting up iq and oq registers Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 09/15] net/octeontx_ep: Added dev start and stop Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 10/15] net/octeontx_ep: Receive data path function added Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 11/15] net/octeontx_ep: Transmit " Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 12/15] net/octeontx_ep: INFO PTR mode support added Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 13/15] net/octeontx_ep: stats get/reset and link update Nalla, Pradeep
2020-12-31 7:22 ` [dpdk-dev] [PATCH 14/15] net/octeontx_ep: rx queue interrupt Nalla, Pradeep
2020-12-31 7:22 ` Nalla, Pradeep [this message]
2021-01-04 11:51 ` [dpdk-dev] [PATCH 00/15] Octeon Tx/Tx2 Endpoint pmd Ferruh Yigit
2021-01-05 14:43 ` [dpdk-dev] [EXT] " Pradeep Kumar Nalla
2021-01-05 15:29 ` Ferruh Yigit
2021-01-06 11:35 ` Pradeep Kumar Nalla
2021-01-06 11:58 ` Jerin Jacob
2021-01-06 14:24 ` Ferruh Yigit
2021-01-06 14:43 ` Jerin Jacob
2021-01-06 15:30 ` Pradeep Kumar Nalla
2021-01-06 18:13 ` Ferruh Yigit
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