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From: Ajit Khaparde <ajitkhaparde@gmail.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com, Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Subject: [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family
Date: Mon, 11 Jan 2021 09:43:55 -0800
Message-ID: <20210111174400.10606-2-ajit.khaparde@broadcom.com> (raw)
In-Reply-To: <20210111174400.10606-1-ajit.khaparde@broadcom.com>

From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>

The new chip (Stingray 2) is part of the P5 chip family with a number
of changes:

1. Implement the epoch doorbell bit for 58818 chip. With the new doorbell
   infrastructure and the unbounded index logic, now set the epoch
   doorbell bit to support proper doorbell operation on the new chip.
   Toggle epoch bit of all rings when it's wrapped to support doorbell
   overflow checking.
2. Get the legacy doorbell size from firmware. Legacy doorbell support has
   been removed in Stingray 2. So, the fast path doorbell pages start from
   the base of the BAR. Drivers need to use legacy_l2_db_space_size_kb
   field in the hwrm_func_qcfg_output response to get the legacy doorbell
   page offset from the BAR.
3. Set VALID doorbell bit on 58818 chip family. This class of chip has
   a valid doorbell bit added and it needs to be set.
4. Use "chip_num" returned by firmware. The "chip_num" field in the
   HWRM_VER_GET output returns the chip number. Use this value to identify
   chip category for 58818 chip family.
5. Added device ids for Stingray2 PF/VF devices.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 doc/guides/rel_notes/release_21_02.rst |  6 ++++++
 drivers/net/bnxt/bnxt.h                | 15 +++++++++++++++
 drivers/net/bnxt/bnxt_cpr.h            |  7 ++++++-
 drivers/net/bnxt/bnxt_ethdev.c         |  9 +++++++++
 drivers/net/bnxt/bnxt_hwrm.c           |  6 ++++++
 drivers/net/bnxt/bnxt_ring.c           | 19 +++++++++++++++----
 6 files changed, 57 insertions(+), 5 deletions(-)

diff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst
index 706cbf8f0..b1bb2d867 100644
--- a/doc/guides/rel_notes/release_21_02.rst
+++ b/doc/guides/rel_notes/release_21_02.rst
@@ -55,6 +55,12 @@ New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Updated Broadcom bnxt driver.**
+
+  Updated the Broadcom bnxt driver with fixes and improvements, including:
+
+  * Added support for Stingray2 device.
+
 
 Removed Items
 -------------
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 8374e9fad..0d3998f20 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -66,6 +66,10 @@
 #define BROADCOM_DEV_ID_58804		0xd804
 #define BROADCOM_DEV_ID_58808		0x16f0
 #define BROADCOM_DEV_ID_58802_VF	0xd800
+#define BROADCOM_DEV_ID_58812		0xd812
+#define BROADCOM_DEV_ID_58814		0xd814
+#define BROADCOM_DEV_ID_58818		0xd818
+#define BROADCOM_DEV_ID_58818_VF	0xd82e
 
 #define BROADCOM_DEV_957508_N2100	0x5208
 #define IS_BNXT_DEV_957508_N2100(bp)	\
@@ -367,14 +371,20 @@ struct bnxt_coal {
 };
 
 /* 64-bit doorbell */
+#define DBR_EPOCH_MASK				0x01000000UL
+#define DBR_EPOCH_SFT				24
 #define DBR_XID_SFT				32
 #define DBR_PATH_L2				(0x1ULL << 56)
+#define DBR_VALID				(0x1ULL << 58)
 #define DBR_TYPE_SQ				(0x0ULL << 60)
 #define DBR_TYPE_SRQ				(0x2ULL << 60)
 #define DBR_TYPE_CQ				(0x4ULL << 60)
 #define DBR_TYPE_NQ				(0xaULL << 60)
 #define DBR_TYPE_NQ_ARM				(0xbULL << 60)
 
+#define DB_PF_OFFSET			0x10000
+#define DB_VF_OFFSET			0x4000
+
 #define BNXT_RSS_TBL_SIZE_P5		512U
 #define BNXT_RSS_ENTRIES_PER_CTX_P5	64
 #define BNXT_MAX_RSS_CTXTS_P5 \
@@ -601,6 +611,7 @@ struct bnxt {
 	struct rte_eth_dev		*eth_dev;
 	struct rte_pci_device		*pdev;
 	void				*doorbell_base;
+	int				legacy_db_size;
 
 	uint32_t		flags;
 #define BNXT_FLAG_REGISTERED		BIT(0)
@@ -649,6 +660,10 @@ struct bnxt {
 #define BNXT_TRUFLOW_EN(bp)	((bp)->flags & BNXT_FLAG_TRUFLOW_EN)
 #define BNXT_GFID_ENABLED(bp)	((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 
+	uint16_t		chip_num;
+#define CHIP_NUM_58818		0xd818
+#define BNXT_CHIP_SR2(bp)	((bp)->chip_num == CHIP_NUM_58818)
+
 	uint32_t		fw_cap;
 #define BNXT_FW_CAP_HOT_RESET		BIT(0)
 #define BNXT_FW_CAP_IF_CHANGE		BIT(1)
diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h
index a763f6006..30635fcc1 100644
--- a/drivers/net/bnxt/bnxt_cpr.h
+++ b/drivers/net/bnxt/bnxt_cpr.h
@@ -81,9 +81,14 @@ struct bnxt_db_info {
 	};
 	bool                    db_64;
 	uint32_t		db_ring_mask;
+	uint32_t		db_epoch_mask;
+	uint32_t		db_epoch_shift;
 };
 
-#define DB_RING_IDX(db, idx)	((idx) & (db)->db_ring_mask)
+#define DB_EPOCH(db, idx)	(((idx) & (db)->db_epoch_mask) <<	\
+				 ((db)->db_epoch_shift))
+#define DB_RING_IDX(db, idx)	(((idx) & (db)->db_ring_mask) |		\
+				 DB_EPOCH(db, idx))
 
 struct bnxt_ring;
 struct bnxt_cp_ring_info {
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 0788d263d..02ab87bba 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -80,6 +80,10 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
 	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
+	{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
 	{ .vendor_id = 0, /* sentinel */ },
 };
 
@@ -3979,6 +3983,7 @@ static bool bnxt_vf_pciid(uint16_t device_id)
 	case BROADCOM_DEV_ID_58802_VF:
 	case BROADCOM_DEV_ID_57500_VF1:
 	case BROADCOM_DEV_ID_57500_VF2:
+	case BROADCOM_DEV_ID_58818_VF:
 		/* FALLTHROUGH */
 		return true;
 	default:
@@ -4001,6 +4006,10 @@ static bool bnxt_p5_device(uint16_t device_id)
 	case BROADCOM_DEV_ID_57502_MF2:
 	case BROADCOM_DEV_ID_57500_VF1:
 	case BROADCOM_DEV_ID_57500_VF2:
+	case BROADCOM_DEV_ID_58812:
+	case BROADCOM_DEV_ID_58814:
+	case BROADCOM_DEV_ID_58818:
+	case BROADCOM_DEV_ID_58818_VF:
 		/* FALLTHROUGH */
 		return true;
 	default:
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 73647fba8..36c229de1 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1129,6 +1129,9 @@ int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
 		PMD_DRV_LOG(ERR, "Unsupported request length\n");
 		rc = -EINVAL;
 	}
+
+	bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
+
 	bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 	bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
 	if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
@@ -3207,6 +3210,9 @@ int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
 		break;
 	}
 
+	bp->legacy_db_size =
+		rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
+
 	HWRM_UNLOCK();
 
 	return rc;
diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c
index adddf9bc4..75b541bdc 100644
--- a/drivers/net/bnxt/bnxt_ring.c
+++ b/drivers/net/bnxt/bnxt_ring.c
@@ -346,10 +346,7 @@ static void bnxt_set_db(struct bnxt *bp,
 			uint32_t ring_mask)
 {
 	if (BNXT_CHIP_P5(bp)) {
-		if (BNXT_PF(bp))
-			db->doorbell = (char *)bp->doorbell_base + 0x10000;
-		else
-			db->doorbell = (char *)bp->doorbell_base + 0x4000;
+		int db_offset = DB_PF_OFFSET;
 		switch (ring_type) {
 		case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 			db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
@@ -365,6 +362,14 @@ static void bnxt_set_db(struct bnxt *bp,
 			db->db_key64 = DBR_PATH_L2;
 			break;
 		}
+		if (BNXT_CHIP_SR2(bp)) {
+			db->db_key64 |= DBR_VALID;
+			db_offset = bp->legacy_db_size;
+		} else if (BNXT_VF(bp)) {
+			db_offset = DB_VF_OFFSET;
+		}
+
+		db->doorbell = (char *)bp->doorbell_base + db_offset;
 		db->db_key64 |= (uint64_t)fid << DBR_XID_SFT;
 		db->db_64 = true;
 	} else {
@@ -383,6 +388,12 @@ static void bnxt_set_db(struct bnxt *bp,
 		db->db_64 = false;
 	}
 	db->db_ring_mask = ring_mask;
+
+	if (BNXT_CHIP_SR2(bp)) {
+		db->db_epoch_mask = db->db_ring_mask + 1;
+		db->db_epoch_shift = DBR_EPOCH_SFT -
+					rte_log2_u32(db->db_epoch_mask);
+	}
 }
 
 static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index,
-- 
2.21.1 (Apple Git-122.3)


  reply	other threads:[~2021-01-11 17:44 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-20  5:24 [dpdk-dev] [PATCH 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
2020-12-20  5:24 ` [dpdk-dev] [PATCH 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-03  3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde
2021-01-03  3:46   ` [dpdk-dev] [PATCH v2 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-08  5:12   ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-08  5:12     ` [dpdk-dev] [PATCH v3 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-08  5:13     ` [dpdk-dev] [PATCH v3 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
2021-01-08  5:13     ` [dpdk-dev] [PATCH v3 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-11 17:43     ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
2021-01-11 17:43       ` Ajit Khaparde [this message]
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde
2021-01-11 17:43       ` [dpdk-dev] [PATCH v4 5/6] net/bnxt: modify context memory allocation Ajit Khaparde
2021-01-11 17:44       ` [dpdk-dev] [PATCH v4 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde
2021-01-12  3:39       ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde

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