From: Ajit Khaparde <ajitkhaparde@gmail.com> To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Subject: [dpdk-dev] [PATCH v4 2/6] net/bnxt: add new RX checksum mode Date: Mon, 11 Jan 2021 09:43:56 -0800 Message-ID: <20210111174400.10606-3-ajit.khaparde@broadcom.com> (raw) In-Reply-To: <20210111174400.10606-1-ajit.khaparde@broadcom.com> From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> The 58818 chips support two different checksum modes. Host driver has to register with FW which checksum mode it prefers to use. DPDK driver want to use "cs_all_ok_mode=1". FW advertises the support of the different checksum modes on per VNIC basis in the HWRM_VNIC_QCAPS response. Driver should use HWRM_VNIC_CFG to configure the needed checksum mode. Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> --- drivers/net/bnxt/bnxt.h | 1 + drivers/net/bnxt/bnxt_hwrm.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 0d3998f20..14f52b2c4 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -679,6 +679,7 @@ struct bnxt { uint32_t vnic_cap_flags; #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0) #define BNXT_VNIC_CAP_OUTER_RSS BIT(1) +#define BNXT_VNIC_CAP_RX_CMPL_V2 BIT(2) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; unsigned int rx_num_qs_per_vnic; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index 36c229de1..350fe2f97 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -860,6 +860,9 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP) bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS; + if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP) + bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2; + bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported); HWRM_UNLOCK(); @@ -1961,6 +1964,11 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic) rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id); enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID | HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID; + if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) { + enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE; + req.rx_csum_v2_mode = + HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK; + } goto config_mru; } -- 2.21.1 (Apple Git-122.3)
next prev parent reply other threads:[~2021-01-11 17:44 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-20 5:24 [dpdk-dev] [PATCH 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde 2020-12-20 5:24 ` [dpdk-dev] [PATCH 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde 2020-12-20 5:24 ` [dpdk-dev] [PATCH 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde 2020-12-20 5:24 ` [dpdk-dev] [PATCH 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde 2020-12-20 5:24 ` [dpdk-dev] [PATCH 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde 2020-12-20 5:24 ` [dpdk-dev] [PATCH 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde 2020-12-20 5:24 ` [dpdk-dev] [PATCH 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde 2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde 2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde 2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde 2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde 2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde 2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 5/6] net/bnxt: modify context memory allocation code Ajit Khaparde 2021-01-03 3:46 ` [dpdk-dev] [PATCH v2 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde 2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde 2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde 2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 2/6] net/bnxt: add new RX checksum mode Ajit Khaparde 2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde 2021-01-08 5:12 ` [dpdk-dev] [PATCH v3 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde 2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 5/6] net/bnxt: modify context memory allocation Ajit Khaparde 2021-01-08 5:13 ` [dpdk-dev] [PATCH v3 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde 2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde 2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 1/6] net/bnxt: add support for 58818 chip family Ajit Khaparde 2021-01-11 17:43 ` Ajit Khaparde [this message] 2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 3/6] net/bnxt: modify VNIC accounting Ajit Khaparde 2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 4/6] net/bnxt: add LRO support for SR2 chip Ajit Khaparde 2021-01-11 17:43 ` [dpdk-dev] [PATCH v4 5/6] net/bnxt: modify context memory allocation Ajit Khaparde 2021-01-11 17:44 ` [dpdk-dev] [PATCH v4 6/6] net/bnxt: add Rx logic for 58818 chips Ajit Khaparde 2021-01-12 3:39 ` [dpdk-dev] [PATCH v4 0/6] net/bnxt: add support for Stingray2 Ajit Khaparde
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